CN106684118A - Switching power-semiconductor device and manufacturing method thereof - Google Patents
Switching power-semiconductor device and manufacturing method thereof Download PDFInfo
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- CN106684118A CN106684118A CN201710104456.6A CN201710104456A CN106684118A CN 106684118 A CN106684118 A CN 106684118A CN 201710104456 A CN201710104456 A CN 201710104456A CN 106684118 A CN106684118 A CN 106684118A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
The invention relates to the technical filed of a power semiconductor device, in particular to a switching power semiconductor and a manufacturing method thereof. The device comprises a silicon layer and a metal layer connected with the silicon layer, wherein the silicon lay comprises a relative first surface and a second surface on the opposite side, and the first surface comprises an active area and a junction termination area, and the active area is surrounded by the junction termination area. The second surface comprises a first ion doping region according to the junction termination area and a second ion doping region according to the junction termination area which ion doping concentration is lower than the first ion doping region, the second ion doping region is surrounded by the first ion doping region. The switching power semiconductor and a manufacturing method thereof has the advantages that the free carrier concentration and current density in the device junction termination area is reduced, the collision ionization and dynamic avalanche breakdown is cut down, the edge cell latch-up damage due to the concentration of the current is decreased and the integral safety area of the device is expanded.
Description
Technical field
The present invention relates to power semiconductor device technology field, more particularly to a kind of switching power semiconductor device and its
Manufacture method.
Background technology
In the knot terminal area of the exemplary power device such as MOSFET, IGBT, FRD, field limiting ring is typically all included
Structure, field plate structure, its effect is to aid in device and can bear higher reverse pressure.In device shut-off or reversely restoring process
In, current convergence phenomenon as shown in Figure 1 is susceptible to, specially because ion implanting covers whole chip back regions
(i.e. 3 positions are same ion concentration injection region in Fig. 1) forms current convergence in knot terminal area.And internal field compared with
High region has the high carrier of comparison (few son) concentration, produces higher ionization by collision and dynamic avalanche, affects (reduction)
The safety operation area (SOA) of device.
To avoid above-mentioned phenomenon, the most frequently used effective way is the free carrier concentration for reducing knot end, so as to subtract
Few ionization by collision and dynamic avalanche puncture.Specific practice is the ion implantation dosage for reducing chip back, to reduce chip back
The injection efficiency of launch site, so as to reduce stream to the purpose of the concentration of electric charges of chip front side active area.But so can cause
Amount of charge in whole chip body is few, transmits the ability of electric current and reduces, namely the conducting resistance increase of device.
The power semiconductor chips back side needs higher doping content, back metal is formed well with silicon substrate
Ohmic contact.Typically one layer of higher ion implanting of concentration is done in chip back, is subsequently also performed to a furnace anneal,
With the purpose for reaching activation injection ion and repairing implant damage.Due to the restriction of chip front side metal level, furnace anneal temperature
Low, the ion-activated rate of injection is low, therefore needs the ion implanting of high dose.But high dose ion injection can be caused to silicon substrate
Damage, cause element leakage big.Also, if furnace anneal temperature is low, the ability damaged is repaired also than relatively low, remain in a large number
Damage can also cause the electric leakage of device.
The content of the invention
Cause to produce higher collision in knot terminal area formation current convergence for what power semiconductor was present
Element leakage that ionization and dynamic avalanche or damage cause, the problems such as safety operation area is not good, embodiments provide
A kind of switching power semiconductor device.
Correspondingly, the manufacture method that the embodiment of the present invention additionally provides the switching power semiconductor device.
In order to reach foregoing invention purpose, the embodiment of the present invention employs following technical scheme：
A kind of switching power semiconductor device, including silicon layer, the silicon layer has relative first surface and the second table
Face, the first surface is divided into active region and knot terminal area, described also including the metal level for being incorporated into the second surface
It is that the knot terminal area surrounds around active region；The second surface is divided into and the active region just corresponding first
Ion implantation region and with the just corresponding dopant ion bulk concentration in the knot terminal area be less than first ion implantation region
The second ion implantation region, be that second ion implantation region is surrounded around first ion implantation region, it is described
The area of the first ion implantation region is less than or equal to the area of the active region, what first ion implantation region contained
Injection plasma levels are more than the order of magnitude of injection plasma levels at least one that second ion implantation region contains.
Correspondingly, the manufacture method of switching power semiconductor device described above, at least comprises the following steps：
1) semi-finished product that Facad structure is completed according to common process are carried out into reduction processing；
2) ion implantation doping process is carried out to the second surface；
3) second surface region annealing corresponding with the active region is passed through using laser annealing technique
The region that the laser annealing is processed forms the first ion implantation region ion implantation region；
4) furnace anneal process is carried out without the region that the laser annealing is processed to the second surface, is made through described
The region of furnace anneal process forms the second ion implantation region ion implantation region；
5) deposition processes of metal level are carried out in the chip back.
The switching power semiconductor device that the above embodiment of the present invention is provided, the ion doping of second surface is divided into
The different doped region of plasma levels, wherein the first ion implantation region is the higher doped region of plasma levels, and
Define that the first ion implantation region is faced with active region, the second ion implantation region is faced with knot terminal area, the
Area of the area of one ion implantation region less than or equal to active region, it is ensured that metal forms good ohm and connects with silicon layer
Touch, reduce the static parameters such as the conducting resistance of device and static function, reduce the free carrier concentration of device junction terminal area
And electric current density, reduce ionization by collision and dynamic avalanche punctures, reduce the latch-up that edge cellular is produced due to current convergence
Damage, so as to improve the general safety working area of device.
The manufacture method of the switching power semiconductor device that the above embodiment of the present invention is provided, using laser annealing and stove
Pipe annealing two-step process is sent out, form the distribution of the different doped region of plasma levels of second surface, it is to avoid conventional lithographic
Technique, greatly simplify the back process of power semiconductor, the device of acquisition can effectively solve the problem that knot terminal area by
In the caused Problem of Failure of current convergence, the conductive capability of device is improve, reduce the conducting resistance of device.
Description of the drawings
Fig. 1 is ordinary power semiconductor device termination environment current convergence phenomenon schematic diagram；
Fig. 2 switching power semiconductor device structure front views provided in an embodiment of the present invention；
Fig. 3 switching power semiconductor device structure electric current flowing schematic diagrams provided in an embodiment of the present invention；
Fig. 4 switching power semiconductor device first surface schematic diagrams provided in an embodiment of the present invention；
Fig. 5 switching power semiconductor device second surface schematic diagrams provided in an embodiment of the present invention；
Fig. 6 switching power manufacturing method of semiconductor device schematic flow sheets provided in an embodiment of the present invention.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, and
It is not used in the restriction present invention.
As shown in Fig. 2,3,4,5, the embodiment of the present invention provides a kind of switching power semiconductor device.
The switching power semiconductor device includes silicon layer 1, and the silicon layer 1 is included with relative first surface and the
Two surfaces, the first surface is divided into active region 11 and knot terminal area 12, is the knot around the active region 11
Terminal area 12 surrounds；The second surface be divided into just corresponding first ion implantation region 13 of the active region 11 and with
Second ion doped region of the just corresponding plasma levels in the knot terminal area 12 less than first ion implantation region 13
Domain 14, is that second ion implantation region 14 is surrounded around first ion implantation region 13, and first ion is mixed
The area in miscellaneous region 13 is less than or equal to the area of the active region 11, the first ion implantation region ion implantation region
The 13 injection ion concentrations for containing are more than the injection ion concentration that the second ion implantation region ion implantation region 14 contains
At least one order of magnitude；The second surface also incorporates metal level 2.
In embodiments of the present invention, the first surface mentioned is the chip front side that this area is often said, second surface is
Chip back, is write as first surface, second surface and is in order at convenient style of writing, and the expressed meaning is substantially.
Preferably, the silicon layer 1 is any one in silicon dioxide layer, silicon nitride layer, polysilicon layer.
Preferably, the metal level 2 is any one in Ti+Ni+Ag layers, Al+Ti+Ni+Ag layers, Ti+Au layers.It is therein
Ti (titanium) and Al (aluminum metal) can form good Ohmic contact with the silicon materials at the device back side, reduce the conducting of device
Resistance；Ni metals are as barrier layer or are transition zone, with good cementability, can prevent again upper and lower in encapsulation process
The resistance carried on the back the phase counterdiffusion between layer gold and cause increases.The metals such as Ag, Au due to its good electric conductivity, heat conductivity, and
Its good solderability between base plate for packaging, generally serves as the outermost layer of power device back metal.The metal level 2 is folded to be set
On the second surface.
The thickness of the silicon layer 1 is 50 μm~1000 μm, corresponds respectively to the pressure as little as 600V of blocking and blocking high pressure
Up to the product of 10000V.
The thickness of the metal level 2 sets 1.4 μm~2.7 μm.
Specifically, Ti (titanium) and Al (aluminum metal) thickness are usually 0.1 μm~0.2 μm, and Ti can be with the device back side
Silicon materials form good Ohmic contact；Used as barrier layer, usual thickness is 0.3 μm~0.5 μm to Ni metals, can prevent envelope
Phase counterdiffusion during dress between upper and lower back of the body layer gold.The metals such as Ag, Au guarantee with base plate for packaging welding well, and control material
Cost, usual thickness is 1 μm~2 μm.
Preferably, the minimum range at the edge of the active region 11 to the edge of the silicon layer 1 is c, and first ion is mixed
The minimum range at the edge of miscellaneous region 13 to the edge of the silicon layer 1 is d.In other words the edge of the silicon layer 1 reaches the active region
The distance (width of knot terminal area 12) at edge 11 is c, and the edge of the silicon layer 1 reaches first ion implantation region 13
Distance (the second ion implantation region 14) is d.
That is, active region 11 is just relative with the first ion implantation region 13, but the area of active region 11 is big
In or equal to the first ion implantation region 13.On the one hand ensure that the metal level 2 of second surface and silicon layer 1 form good
Ohmic contact, and reduce the associated static such as conducting resistance of device parameter and quiescent dissipation；On the other hand, the first ion doping
The area in region 13 is less than active region 11, it is possible to reduce, to knot terminal area 12, reduction is touched for free carrier and electric current density
Hit ionization and dynamic avalanche punctures, reduce edge cellular because the latch-up that current convergence is produced is damaged, device is improved on the whole
The safety operation area of part.
The bulk concentration of the described above injection ion for containing, during the product of molding is referred in the present invention, first from
The bulk concentration of the injection ion possessed on sub- doped region 13, the injection ion possessed on the second ion implantation region 14
Bulk concentration.
Preferably, the bulk concentration of the ion of the injection that first ion implantation region 13 possesses is 1.0E17cm-3
~1.0E19cm-3, the bulk concentration of the ion of the injection that second ion implantation region 14 possesses is 1.0E15cm-3~
1.0E16cm-3.What the bulk concentration of the injection ion that the first ion implantation region 13 possesses possessed than the second ion implantation region 14
The bulk concentration of injection ion is higher by an order of magnitude, and with reference to the area of active region 11 the first ion doped region is more than or equal to
The area in domain 13, can effectively reduce free carrier and electric current density to knot terminal area 12, reduce ionization by collision and move
State avalanche breakdown, reduces edge cellular because the latch-up that current convergence is produced is damaged, and the safe work of device is improved on the whole
Make area.
Preferably, the type of the injection ion is N-type or p-type.The N-type ion is in P elements, arsenic element
It is at least one.This dvielement can reach 80%~100% activity ratio so that the ion overwhelming majority of injection becomes effective
Ion, improves the stability of device products parameter, and the defect produced by ion implantation technology can also be obtained well
Repair, reduce element leakage especially hot operation when the probability leaked electricity.
At least one of the p-type ion in boron element, boron difluoride.This dvielement can reach 80%~
100% activity ratio so that the ion overwhelming majority of injection becomes effective ion, improves stablizing for device products parameter
Property, and the defect produced by ion implantation technology can also be repaired well, reduce element leakage especially high temperature
The probability leaked electricity during work.
The above embodiment of the present invention, the ion doping of second surface is divided into active region 11, the knot with first surface
Two different regions of the corresponding dopant ion bulk concentration in terminal area 12, wherein the first ion implantation region 13 is gas ions
The higher doped region of concentration, it is ensured that metal forms good Ohmic contact with silicon layer, reduces the static state such as the conducting resistance of device
Parameter and static function, the second ion implantation region is the relatively low doped region of plasma levels, reduces the transmitting in the region
Injection efficiency, so as to reduce the free carrier concentration and electric current density of device junction terminal area 12, reduces ionization by collision and moves
State avalanche breakdown, reduces edge cellular because the latch-up that current convergence is produced is damaged, so as to improve the general safety of device
Working area.
Correspondingly, on the premise of above-described embodiment, the embodiment of the present invention additionally provides above-mentioned switching power quasiconductor
The manufacture method of device.
As shown in fig. 6, in one embodiment, the manufacture method of above-mentioned switching power semiconductor device is at least including following
Step：
1) semi-finished product that Facad structure is completed according to common process are carried out into reduction processing；
2) ion implantation doping process is carried out to the second surface；
3) second surface region annealing corresponding with the active region is passed through using laser annealing technique
The region that the laser annealing is processed forms the first ion implantation region；
4) furnace anneal process is carried out without the region that the laser annealing is processed to the second surface, is made through described
The region of furnace anneal process forms the second ion implantation region；
5) deposition processes of metal level are carried out in the second surface.
The manufacturing process of above-mentioned switching power semiconductor device is further described in detail below.
Wherein, as shown in fig. 6, in step 1) in, Facad structure here is exactly first surface mentioned above, that is,
Chip front side；Having completed the semi-finished product of Facad structure can voluntarily produce, it is also possible to obtain by other means, and the present invention is not
It is limited.
Step 1) in, reduction processing is carried out to the second surface of semi-finished product, including first to chip being ground reduction processing,
Then by the way of acid solution carries out batch immersion or monolithic sprinkling to semi-finished product, by grinding at thinning and acid soak
Reason, removes all of dielectric layer material of chip back, and removes the stress produced during grinding.
In one embodiment, acid solution is the aqueous solution of at least one of sulphuric acid, nitric acid, acetic acid, Fluohydric acid., is not limited certainly
In above-mentioned cited acid.It is every can remove second surface dielectric layer material be respectively provided with feasibility.Here sour water-soluble
Liquid, concentration is not limited, and can determine the concentration of acid according to specific needs.
Preferably, step 2) in, ion implantation doping is processed, and the ionic type of injection is N-type or p-type.Wherein, N-type
At least one of the ion in P elements, arsenic element.This dvielement can reach 80%~100% activity ratio so that note
The ion overwhelming majority for entering becomes effective ion, improves the stability of device products parameter, and ion implantation technology institute
The defect of generation can also be repaired well, reduce element leakage especially hot operation when the probability leaked electricity.
At least one of the p-type ion in boron element, boron difluoride.This dvielement can reach 80%~100%
Activity ratio so that the ion overwhelming majority of injection becomes effective ion, improves the stability of device products parameter, and from
Defect produced by sub- injection technology can also be repaired well, reduce element leakage especially hot operation when leak electricity
Probability.
The implantation dosage of above-mentioned ion is 1.0E13cm-2~1.0E14cm-2, belong to high concentration ion and inject, and here
Implantation dosage refer to unit area injection population of ions, therefore inject after obtain through laser annealing or furnace anneal
Injection ion bulk concentration refer to the concentration that implantation dosage is obtained divided by volume.High concentration ion injects, and is on the one hand conducive to
Metal level forms good Ohmic contact with silicon layer, reduces associated static parameter and the quiescent dissipations such as conducting resistance, on the other hand,
The activity ratio that follow-up furnace anneal can be avoided to bring because temperature is relatively low is too low.
Preferably, step 3) in, the laser light intensity of laser annealing is 0.5Jcm-2~5.0Jcm-2, the laser
Energy density be 1Jcm-2~10Jcm-2, laser beam spot is 0.1 × 1.0mm2~1.0 × 10.0mm2, during laser annealing
A length of 0.1~1.0 μ s.Laser annealing under the conditions of being somebody's turn to do, can quickly realize injecting the high activation amount of ion, so as to form high body
The doped region of concentration；In addition, laser annealing defect repair ability is strong, the damage caused to silicon is little, and element leakage is little.
Laser annealing is carried out regioselectivity scanning to second surface and is moved back using the automatically scanning pattern of laser annealing apparatus
Fire, selected region is as shown in Figure 5.
Step 4) in, the temperature of the furnace anneal is 400 DEG C~500 DEG C, a length of 10min~60min during furnace anneal,
And made annealing treatment in nitrogen atmosphere.Conventional furnace anneal, activity ratio is low, therefore in first being formed using laser annealing
The higher doped region of heart plasma levels, then using furnace anneal, realize the higher doped region of plasma levels (i.e.
One ion implantation region) the relatively low doped region of plasma levels (i.e. the second ion implantation region) distribution.Second surface
Plasma levels it is relatively low doped region correspondence first surface device junction terminal area, due to low bulk concentration doped region from
Daughter concentration is low, therefore, its transmitting injection efficiency is low, so as to reduce the free carrier concentration and electricity of device junction terminal area
Current density, reduces edge cellular because the latch-up that current convergence is produced is damaged, so as to the general safety for improving device works
Area.
Step 5) in, the deposition processes of metal level are general using conventional multiple layer metal material, such as Ti+Ni+Ag, Al+Ti
Any one in+Ni+Ag, Ti+Au.Certainly, this cited several metal material are not limited to.The thickness of the metal level for being deposited
It is set as 1.4 μm~2.7 μm.Specifically, Ti (titanium) and Al (aluminum metal) thickness are usually 0.1 μm~0.2 μm, and Ti can
Good Ohmic contact is formed with the silicon materials at the device back side；Used as barrier layer, usual thickness is 0.3 μm~0.5 μm to Ni metals,
Phase counterdiffusion when can prevent from encapsulating between upper and lower back of the body layer gold.The metals such as Ag, Au guarantee with base plate for packaging welding well,
And control material cost, usual thickness is 1 μm~2 μm.
Specifically using electron beam evaporation or magnetron sputtering technique, and suitable alloying technology condition, give birth to metal level
It is longer than second surface, it is ensured that the metal level of generation can form good alloy contact with second surface, so as to meet follow-up chip
Bonding, the demand of encapsulation.
The manufacture method of the switching power semiconductor device that the above embodiment of the present invention is provided, compared with prior art,
Photoetching treatment (photoetching treatment includes some row technical processs such as gluing, exposure, development) need not be carried out, power is simplified and is partly led
The back process of body device；In addition, the doping content injection of common process needs to be realized by adjusting ion implantation dosage, it is high
Implantation dosage needs high line ion implantation device, and low implantation dosage needs bottom line ion implantation device, and the present invention is adopted
Use double annealing technique, it is only necessary to using disposable implantation dosage, so as to omit injection machine equipment, reduce equipment investment
And the operation cost of equipment.The device of acquisition can effectively solve the problem that caused failure is asked due to current convergence for knot terminal area
Topic, improves the conductive capability of device, reduces the conducting resistance of device, is suitable to popularization and application.
In order to preferably embody switching power semiconductor device provided in an embodiment of the present invention and preparation method thereof, below
Further illustrated by embodiment.
Embodiment 1
A kind of manufacture method of switching power semiconductor device, comprises the steps：
1) the qualified semi-finished product for having completed front technique are chosen；
2) carrying out second surface to semi-finished product carries out reduction processing, thinning including being first ground to second surface, then
Adopt mass concentration carries out immersion treatment for 98% aqueous sulfuric acid, and a length of 10 minutes during immersion, this step acid soak is processed
Effect be the white residue that produces and to remove the stress produced during grinding when removing grinding.Cleaning is then taken out, semi-finished product table is removed
The spent acid in face；
3) to step 2) the semi-finished product chip that obtains carries out P elements ion implanting, and implantation dosage is 1.0E14cm-2；
4) regioselectivity scan process is carried out to second surface using laser annealing apparatus, scans the center of second surface
Position, the region scanned is suitable with the active region of first surface and corresponding, and particular location is as shown in figure 5, adjust laser light
Intensity is 4.0Jcm-2, the energy density of laser is 8Jcm-2, laser beam spot is 0.8 × 10.0mm2, and during laser annealing
A length of 1.0 μ s, obtain the first ion implantation region；
5) semi-finished product after laser annealing is processed are placed in boiler tube under the atmosphere of nitrogen, carry out furnace anneal process,
The temperature of furnace anneal is set as 450 DEG C, anneal duration is 30min, formation is centered around overseas second in the first ion doped region
Ion implantation region (as shown in Figure 5)；
6) after furnace anneal process, using conventional magnetron sputtering technique, in one layer of gold of second surface magnetron sputtering
Category layer, the metal level is Ti+Au layers, and the thickness of Ti metal levels is 0.12 μm, and the thickness of Au metal levels is 1.0 μm.
Expanded electric-resistivity method (SRP methods, SpreadingResistance Profiles) detection, what the present embodiment made opens
The bulk concentration of the dopant ion of the first ion implantation region that pass type power semiconductor laser annealing technique is formed after processing
For 1.0E18cm-3；The bulk concentration of the dopant ion of the second ion implantation region is 3.0E15cm-3；By the electricity of measurement device
Stream, voltage response, the saturation conduction voltage (conducting resistance) that can calculate device is 2.2V (correspondence 30A 1700V
IGBT products).
Embodiment 2
A kind of manufacture method of switching power semiconductor device, comprises the steps：
1) the qualified semi-finished product for having completed front technique are chosen；
2) carrying out second surface to semi-finished product carries out reduction processing, thinning including being first ground to second surface, then
The aqueous solution for adopting mass concentration and mixing with the Fluohydric acid. that mass concentration is 42% for 90% nitric acid carries out immersion treatment, soaks
Shi Changwei 12 minutes, the white residue that the effect that this step acid soak is processed is produced when being removal grinding and answering for producing when removing grinding
Power.Cleaning is then taken out, the spent acid of surface of semi-finished is removed；
3) to step 2) the semi-finished product chip that obtains carries out boron element ion implanting, and implantation dosage is 3.0E13cm-2；
4) regioselectivity scan process is carried out to second surface using laser annealing apparatus, scans second surface centre bit
Put, the region scanned is suitable with the active region of first surface and corresponding, particular location is as shown in figure 5, adjust laser intensity
Spend for 5.0Jcm-2, the energy density of laser is 10Jcm-2, laser beam spot is 1.0 × 10.0mm2, and during laser annealing
A length of 0.8 μ s, obtain the first ion implantation region；
5) semi-finished product after laser annealing is processed are placed in boiler tube under the atmosphere of nitrogen, carry out furnace anneal process,
The temperature of furnace anneal is set as 500 DEG C, anneal duration is 60min, formation is centered around overseas second in the first ion doped region
Ion implantation region (as shown in Figure 5)；
6) after furnace anneal process, using conventional magnetron sputtering technique, in one layer of gold of second surface magnetron sputtering
Category layer, the metal level is Al+Ti+Ni+Ag layers, and the thickness of Al metal levels is 0.12 μm, and the thickness of Ti metal levels is 0.10 μm,
The thickness of Ni metal levels is 0.4 μm, and the thickness of Ag metal levels is 1.0 μm.
Expanded electric-resistivity method (SRP methods, SpreadingResistance Profiles) detection, what the present embodiment made opens
The bulk concentration of the dopant ion of the first ion implantation region that pass type power semiconductor laser annealing technique is formed after processing
For 1.0E19cm-3；The bulk concentration of the dopant ion of the second ion implantation region is 3.0E16cm-3；By the electricity of measurement device
Stream, voltage response, the saturation conduction voltage (conducting resistance) that can calculate device is 2.0V (correspondence 50A 1200V
IGBT products).
Presently preferred embodiments of the present invention is the foregoing is only, not to limit the present invention, all essences in the present invention
Any modification, equivalent or improvement made within god and principle etc., should be included within the scope of the present invention.
Claims (10)
1. a kind of switching power semiconductor device, including silicon layer, the silicon layer has relative first surface and second surface,
The first surface is divided into active region and knot terminal area, also including the metal level for being incorporated into the second surface, its feature
It is：It is that the knot terminal area surrounds around the active region；The second surface is divided into the active region just
Corresponding first ion implantation region and with the just corresponding dopant ion bulk concentration in the knot terminal area less than described first from
Second ion implantation region of sub- doped region, is second ion implantation region around first ion implantation region
Surround, the area of first ion implantation region is less than or equal to the area of the active region, first ion doping
The injection plasma levels that region is contained are more than the injection plasma levels at least one that second ion implantation region contains
The order of magnitude.
2. switching power semiconductor device as claimed in claim 1, it is characterised in that：The active area edges are to described
The minimum range at silicon layer edge is c, and the minimum range at the first ion implantation region edge to the silicon layer edge is d, institute
The difference for stating d and c is not less than 10 μm.
3. switching power semiconductor device as claimed in claim 1, it is characterised in that：First ion implantation region contains
The bulk concentration of some injection ions is 1.0E17cm-3~1.0E19cm-3, the injection that second ion implantation region contains from
The bulk concentration of son is 1.0E15cm-3~1.0E16cm-3。
4. switching power semiconductor device as claimed in claim 1, it is characterised in that：The silicon layer be silicon dioxide layer,
Any one in silicon nitride layer, polysilicon layer；The metal level is in Ti+Ni+Ag layers, Al+Ti+Ni+Ag layers, Ti+Au layers
Any one.
5. switching power semiconductor device as claimed in claim 4, it is characterised in that：The thickness of the silicon layer be 50 μm~
1000μm；And/or the thickness of the metal level is 1.4 μm~2.7 μm.
6. the switching power semiconductor device as described in any one of claims 1 to 3, it is characterised in that：The injection ion
Type be N-type or p-type；At least one of the N-type ion in P elements, arsenic element；And/or the p-type ion comes
At least one from boron element, boron difluoride.
7. the manufacture method of the switching power semiconductor device as described in any one of claim 1~6, at least including following step
Suddenly：
1) semi-finished product that Facad structure is completed according to common process are carried out into reduction processing；
2) ion implantation doping process is carried out to the second surface；
3) using laser annealing technique to second surface region annealing corresponding with the active region, through described
The region that laser annealing is processed forms the first ion implantation region；
4) furnace anneal process is carried out without the region that the laser annealing is processed to the second surface, is made through the boiler tube
The region of annealing forms the second ion implantation region；
5) deposition processes of metal level are carried out in the second surface.
8. the manufacture method of switching power semiconductor device as claimed in claim 7, it is characterised in that：The laser annealing
Laser light intensity be 0.5Jcm-2~5.0Jcm-2, the energy density of the laser is 1Jcm-2~10Jcm-2, swash
Beam spot is 0.1 × 1.0mm2~1.0 × 10.0mm2, a length of 0.1~1.0 μ s during laser annealing；And/or the furnace anneal
Temperature is 400 DEG C~500 DEG C, a length of 10min~60min during furnace anneal.
9. the manufacture method of switching power device as claimed in claim 7, it is characterised in that：The implantation dosage of the ion
For 1.0E13cm-2~1.0E14cm-2。
10. the manufacture method of switching power device as claimed in claim 7, it is characterised in that：The reduction processing includes
Grind reduction processing and batch immersion or monolithic sprinkling process are carried out to the semi-finished product using acid solution；The acid solution is sulfur
The aqueous solution of at least one of acid, nitric acid, acetic acid, Fluohydric acid..
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107649785A (en) * | 2017-09-22 | 2018-02-02 | 北京世纪金光半导体有限公司 | A kind of wafer thining method and device |
| WO2021259088A1 (en) * | 2020-06-24 | 2021-12-30 | 全球能源互联网研究院有限公司 | Igbt device backside structure and preparation method therefor, and igbt device |
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| US20120248566A1 (en) * | 2011-03-29 | 2012-10-04 | Alpha And Omega Semiconductor Incorporated | Configuration and method to generate saddle junction electric field in edge termination |
| CN103489910A (en) * | 2013-09-17 | 2014-01-01 | 电子科技大学 | Power semiconductor device and manufacturing method thereof |
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| US6351024B1 (en) * | 1998-02-05 | 2002-02-26 | Siemens Aktiengesellschaft | Power semiconductor diode |
| CN101558500A (en) * | 2006-10-05 | 2009-10-14 | Abb技术有限公司 | Power semiconductor device |
| US20120248566A1 (en) * | 2011-03-29 | 2012-10-04 | Alpha And Omega Semiconductor Incorporated | Configuration and method to generate saddle junction electric field in edge termination |
| CN103839805A (en) * | 2012-11-23 | 2014-06-04 | 中国科学院微电子研究所 | Preparation method of power device |
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| WO2021259088A1 (en) * | 2020-06-24 | 2021-12-30 | 全球能源互联网研究院有限公司 | Igbt device backside structure and preparation method therefor, and igbt device |
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