CN202888149U - Full-pressure-welding packaging high-voltage semiconductor device - Google Patents
Full-pressure-welding packaging high-voltage semiconductor device Download PDFInfo
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- CN202888149U CN202888149U CN 201220591187 CN201220591187U CN202888149U CN 202888149 U CN202888149 U CN 202888149U CN 201220591187 CN201220591187 CN 201220591187 CN 201220591187 U CN201220591187 U CN 201220591187U CN 202888149 U CN202888149 U CN 202888149U
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- voltage
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- molybdenum disk
- closure
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Abstract
The utility model relates to a full-pressure-welding packaging high-voltage semiconductor device, belonging to the technical field of high-voltage semiconductor devices. The utility model mainly solves the problem of welding stress and welding voids since the existing chip and electrode plate are welded by a welding flux at high temperature. The utility model is mainly characterized in that a tube shell lower seal part, a lower molybdenum disk, a semiconductor chip, an upper molybdenum disk, a gate pole lead component and a tube shell upper seal part are sequentially in pressure welding contact; the center of the tube shell upper seal part is provided with a mounting hole; the center of the upper molybdenum disk is provided with a locating hole; and the gate pole lead component is clamped in the locating hole. The utility model can eliminate deformation and stress generated by chip high-temperature welding, can satisfy the requirements for high-voltage semiconductor devices of which the voltage is higher than 5000V or the chip diameter is greater than 4 inches. The utility model is mainly used as a high-voltage semiconductor device in the fields of high-voltage soft-startup power sources, high-voltage static reactive compensation power sources, high-voltage pulse power sources, high-voltage direct-current transmission and the like.
Description
Technical field
The utility model relates to high-voltage semi-conductor device, is specially total head and connects the encapsulation high-voltage semi-conductor device, is mainly used in the fields such as high pressure soft starting power supply, high voltage static reactive power compensation power supply, high-voltage pulse power power-supply, high voltage direct current transmission.
Background technology
Traditional semiconductor device chip manufacturing, adopt chip and electrode slice to form by scolder high temperature weldering knot, there are welding stress and welding cavity, but along with improving constantly of semiconductor device voltage and continuing to increase of chip diameter, particularly the chip diameter reaches that 4 inch are above, voltage reaches 5000V when above, the deformational stress of high-temperature soldering chip makes its reliability can't satisfy the requirement of high-voltage product and large current product, is badly in need of adopting new semiconductor device structure and new semiconductor process techniques to satisfy new demand.
Summary of the invention
The utility model is for above-mentioned deficiency, the semiconductor device of brand-new internal structure is provided---total head connects the encapsulation high-voltage semi-conductor device, eliminate deformation and stress that the chip high-temperature soldering produces, can satisfy the high-voltage semi-conductor device requirement that voltage 5000V is above or chip diameter 4 inch are above.
The utility model is achieved through the following technical solutions: a kind of total head connects the encapsulation high-voltage semi-conductor device, comprise closure on closure under the shell, lower molybdenum disk, semiconductor chip, upper molybdenum disk, gate lead assembly and the shell, it is characterized in that: the closure center is provided with installing hole on the described shell; Described upper molybdenum disk center is provided with location hole, and the gate lead assembly snaps in this location hole; Under the shell on closure, lower molybdenum disk, semiconductor chip, upper molybdenum disk, gate lead assembly and the shell closure be followed successively by crimping and contact.When above-mentioned parts are pressed outer electrode or radiator at element dress, be subjected to the external pressure effect between the closure on closure and the shell under the shell and internal part realization total head is contacted.
Form seal chamber under the shell described in the utility model technical solution on closure and the shell in the closure, be filled with the inert gas that pressure is lower than external pressure in the sealing cavity, thereby both guaranteed that each parts was in contact with one another well, prevented again the chip high voltage sparking.
The two negative angle table top moulding in two sides are adopted in the edge table top moulding of two PN junctions of the semiconductor chip described in the utility model technical solution; The negative angle of two each face of negative angle table top moulding in two sides can be the negative angle that the angle of a negative angle or two different angles consists of, and negative angle θ size is: 0.5 °≤θ≤35 °.
The two negative angle table tops in two sides, semiconductor chip edge described in the utility model technical solution are provided with the cylindrical insulation protection falope ring of annular right-angle, and two-sided surperficial table top protection adopts organic protective material of multilayer high-purity high-insulativity to carry out surface passivation.
Falope ring superficies described in the utility model technical solution are provided with groove, increase creepage distance.
On the upper and lower surface of the upper molybdenum disk described in the utility model technical solution, lower molybdenum disk and the shell under closure, the shell the inside and outside table top of closure be abradant surface, facial plane degree and the depth of parallelism require less than 20 μ m.
Upper molybdenum disk described in the utility model technical solution, the Coating passivation layer of lower molybdenum disk prevent the thermal oxidation of upper and lower molybdenum disk.
Semiconductor chip anode and cathode surface-coated thickness described in the utility model technical solution is the metal conducting layer of 10 μ m ∽, 50 μ m.
Lower molybdenum disk center described in the utility model technical solution is provided with the location blind hole; The closure center is provided with installing blind under the described shell; Reference column is installed in the installing blind, and cooperates with the location blind hole.
The wafer original material of the semiconductor chip described in the utility model technical solution is N-type＜100〉crystal orientation high resistant monocrystalline silicon piece or N-type＜111〉crystal orientation high resistant monocrystalline silicon piece, and adopt phosphorus oxychloride absorption technique technology that original single-chip is carried out pre-absorption and process; Semiconductor core wafer interior microscopic vertical structure is by P
+P
1N
1P
2N
2Symmetrical structure consists of, wherein, and P
1District, P
2The P that the district diffuses to form for double-deck Al
1District, P
2The district.
The utility model is owing to adopting the total head that is made of closure on closure, lower molybdenum disk, semiconductor chip, upper molybdenum disk, gate lead assembly and the shell under the shell to connect the encapsulation high-voltage semi-conductor device, thereby semiconductor chip and the direct crimping of upper and lower molybdenum disk and high temperature weldering knot again, the deformation and the stress that have produced with regard to having eliminated chip high temperature weldering knot like this, and then guaranteed stability and the reliability of device property, be conducive to semiconductor device to larger diameter, more high voltage development; Add semiconductor chip production with original silicon chip preferred＜100〉crystal orientation high resistant silicon chips, with routine＜that 111〉crystal orientation silicon chips are compared crimp strength is higher, also is difficult for broken with regard to having guaranteed semiconductor chip to have better compression strength.
The utility model is owing to adopting the table top moulding at two PN junction edges of semiconductor chip, and the two negative angle table top formative technologies in employing two sides, reduced surface field intensity, be conducive to the raising of semiconductor chip puncture voltage, its table top moulding angle θ size is: 0.5 °≤θ≤35 °; With the moulding of single face table top compare, both simple easy realizations on technique are conducive to again mesa surfaces protection, have reduced simultaneously the loss of cathode plane, anode surface conductive area, are beneficial to the chip through-current capability and improve; Two negative angle shaped and two positive angle moulding are compared, and puncture voltage increases slow, and relative stability is good, are difficult for puncturing.
The utility model since in semiconductor core wafer interior microscopic vertical structure by P
+P
1N
1P
2N
2Symmetrical structure, and P
+P
1N
1P
2N
2Symmetrical structure adopts every kind of impurity source of AL-AL-P-B to deposit respectively, advance respectively diffusion, repeatedly oxidation photoetching formation, P
1District, P
2The district is by adopting the double-deck Al diffusion technique of high surfaces concentration, carry out respectively twice high vacuum Al pre-deposition and twice high temperature Al and advance diffusion, form a low concentration and deeply tie Al and secondary high concentration shallow junction Al, and then solved contradiction between component pressure and other characteristics, not only realized having the superelevation blocking voltage, taken into account simultaneously the dv/dt tolerance, on state characteristic, the hot properties that improve element.Compare with chip manufacturing diffusion technology in the past, can make the semiconductor chip of higher blocking voltage, more excellent device property.
The utility model makes semiconductor chip can bear larger avalanche breakdown voltage and difficult the puncture owing to adopting highfield insulation protection technology in the table top moulding protection at semiconductor chip edge; Highfield insulation protection technology is specially: two-sided table top protection, and adopt organic protective material of multilayer high-purity high-insulativity to carry out surface passivation, improved stability and the reliability of device.The outer two-sided table top protection falope ring of semiconductor chip adopts silicon rubber formed technology to process, and its outward appearance is that annular right-angle is cylindrical, has increased the surface creepage distance, more is conducive to semiconductor chip and bears higher surface breakdown voltage; Simultaneously also be conducive to the two-sided center of semiconductor chip and place upper and lower molybdenum disk, utilize the interior garden of falope ring that upper and lower molybdenum disk is positioned.
The utlity model has and to eliminate deformation and the stress that the chip high-temperature soldering produces, can satisfy the characteristics that voltage 5000V high-voltage semi-conductor device above or that chip diameter 4 inch are above requires.The utility model is mainly used in the high-voltage semi-conductor device in the fields such as high pressure soft starting power supply, high voltage static reactive power compensation power supply, high-voltage pulse power power-supply, high voltage direct current transmission.
Description of drawings
Fig. 1 is that the utility model total head connects encapsulation high voltage semiconductor device structure schematic diagram.
Fig. 2 is the structural representation of the utility model semiconductor chip edge and falope ring.
Fig. 3 is the utility model semiconductor chip edge and with the structural representation of groove falope ring.
Fig. 4 is two PN junction edges of the utility model semiconductor chip table top modeling structure schematic diagram.
Fig. 5 is the utility model semiconductor core wafer interior microscopic vertical structure schematic diagram.
Embodiment
The utility model is described in further detail below in conjunction with Fig. 1 to Fig. 5.
As shown in Figure 1.Total head connects the encapsulation high-voltage semi-conductor device, adopts the encapsulation of colding pressing to form by closure on closure under the shell 1, lower molybdenum disk 2, semiconductor chip 3, upper molybdenum disk 4, gate lead assembly 6, the shell 5.Closure 5 center drillings are installed gate lead assembly 6 on the shell, and gate lead assembly 6 exceeds closure 5 surfaces on the shell, snaps in molybdenum disk 4 central through holes, to upper molybdenum disk location.Part table diameter D is: 23mm≤D≤140mm, shell thickness H is: 23mm≤H≤40mm.Device inside semiconductor chip 3 and upper and lower molybdenum disk 2,4 and the upper and lower closure 1 of shell, 5 between externally realize that total head contacts under the pressure-acting, upper and lower molybdenum disk 2,4 upper and lower surfaces and shell up and down closure 1,5 inside and outside table tops adopt grinding technics processing, and surface planarity and the depth of parallelism require less than 20 μ m.Upper and lower molybdenum disk 2,4 Coating passivating materials prevent the thermal oxidation of molybdenum disk; Semiconductor chip 3 anode and cathode surface-coated thickness are the metal conducting layer of 10 μ m ∽, 50 μ m.Device inside vacuumizes first, filling with inert gas again, and the accurate control by to aeration quantity in the device and air pressure inside makes air pressure inside be lower than external pressure, thereby has both guaranteed that each parts was in contact with one another well, prevents again the chip high voltage sparking.Closure 1 center also can the open-blind hole under lower molybdenum disk 2 and the shell, reference column is installed is positioned.
After adopting total head to connect packaging technology, semiconductor chip 3 and upper and lower molybdenum disk 2,4 direct crimping and without sintering, eliminated the stress that chip produces because of sintering warpage, be more conducive to chip to larger diameter and more high voltage develop.Semiconductor chip 3 produce with original silicon chip preferred＜100〉crystal orientation high resistant silicon chips, with routine＜111〉crystal orientation silicon chips compare, crimp strength is higher.
Such as Fig. 2, shown in Figure 3.The two-sided mesa surfaces protection in semiconductor chip 3 edges adopts organic protective material of multilayer high-purity high-insulativity to carry out surface passivation, makes chip can bear larger avalanche breakdown voltage and difficult the puncture.Inside and outside duoble-layer table top passivation protection has improved stability and the reliability of element.Ground floor table top protective layer, adopt organic protective material of rarer high-purity high-insulativity, utilize homemade special equipment---the two-sided automatic glue application photoresist spinner of silicon chip (utility model patent number: 201120482060.3), wafer 3 is carried out the protection of table top double spread; Two-sided and edge carries out mould injecting glue moulding protection to table top for second layer table top protective layer, the silicon rubber that adopts thicker high-purity high-insulativity, and falope ring 7,8 outward appearances are that annular right-angle is cylindrical; Upper and lower molybdenum disk 4,2 is placed at semiconductor chip 3 two-sided centers, and utilizes the interior garden of protection glue that upper and lower molybdenum disk 4,2 is positioned.Falope ring 8 upper and lower surfaces also can fluted 9 increase creepage distances.
As shown in Figure 4.The two negative angle table top formative technologies in two sides are adopted in the table top moulding at two PN junction edges of semiconductor chip 3, have both reduced surface field intensity, be conducive to the raising of chip puncture voltage, have reduced again the loss of cathode plane, anode surface conductive area; Its table top moulding angle θ size is: 0.5 °≤θ≤35 °.On technique, utilize homemade special equipment-wafer big angle angle lap machine, adopt respectively machinery control, the automatic angle lap of single face to carry out the table top moulding to the wafer two sides, both simple, be easy to again the table top protection.Negative angle can also be two angle θ 1, θ 2.
As shown in Figure 5.Semiconductor chip 3 wafer interior microscopic vertical structures are by P
+P
1N
1P
2N
2Symmetrical structure consists of.P
+P
1N
1P
2N
2Symmetrical structure adopts every kind of impurity source of Al-Al-P-B to deposit respectively, diffusion advances respectively, repeatedly the oxidation photoetching forms.P
1District, P
2The district is by adopting double-deck Al diffusion technique, carry out respectively twice high vacuum Al pre-deposition and twice high temperature Al and advance diffusion, a low concentration that forms is tied Al and secondary high concentration shallow junction Al deeply, and then solved contradiction between component pressure and other characteristics, not only realized having the superelevation blocking voltage, taken into account simultaneously the dv/dt tolerance, on state characteristic, the hot properties that improve element.N
2The district diffuses through and adopts phosphorus pre-deposition and high temperature to advance twice diffusion of oxidation to finish; P
+The district diffuses through and adopts spray B to be coated with the source and high temperature advances diffusion to finish, and is beneficial to conductive layer and forms good ohmic contact.
Long minority carrier life time absorption techniques is adopted in the wafer diffusion.In the wafer diffusion, introduce the phosphorus oxychloride absorption technique original silicon single crystal flake is carried out the processing of n+ layer Impurity Absorption; Simultaneously, in the diffusible oxydation process, mix trichloroethanes oxidation pipe blow-through and absorb impurity, and do p+ diffusion impurity absorption at anode surface spray boron.By adopting repeatedly Impurity Absorption technique, reduced the reduction of the original minority carrier life time of silicon chip, greatly improve minority carrier life time and the parameter uniformity of semiconductor chip, and then guaranteed consistency and the stability of component parameters.
Claims (10)
1. a total head connects the encapsulation high-voltage semi-conductor device, comprise closure (5) on closure under the shell (1), lower molybdenum disk (2), semiconductor chip (3), upper molybdenum disk (4), gate lead assembly (6) and the shell, it is characterized in that: closure on the described shell (5) center is provided with installing hole; Described upper molybdenum disk (4) center is provided with location hole, and gate lead assembly (6) snaps in this location hole; Closure (5) is followed successively by crimping and contacts on closure under the shell (1), lower molybdenum disk (2), semiconductor chip (3), upper molybdenum disk (4), gate lead assembly (6) and the shell.
2. total head according to claim 1 connects the encapsulation high-voltage semi-conductor device, it is characterized in that: form seal chamber on closure under the described shell (1) and the shell in the closure (5), be filled with the inert gas that is lower than external pressure in the sealing cavity.
3. total head according to claim 1 connects the encapsulation high-voltage semi-conductor device, it is characterized in that: the two negative angle table top moulding in two sides are adopted in the edge table top moulding of two PN junctions of described semiconductor chip (3); The two negative angle table top moulding in two sides, the negative angle of each face is the negative angle that the angle of a negative angle or two different angles consists of, negative angle θ size is: 0.5 °≤θ≤35 °.
4. total head according to claim 3 connects the encapsulation high-voltage semi-conductor device, it is characterized in that: the two negative angle table tops in described semiconductor chip (3) two sides, edge are provided with the cylindrical insulation protection falope ring of annular right-angle (7,8).
5. total head according to claim 4 connects the encapsulation high-voltage semi-conductor device, it is characterized in that: described falope ring (8) superficies are provided with groove (9).
6. total head according to claim 1 and 2 connects the encapsulation high-voltage semi-conductor device, it is characterized in that: on the upper and lower surface of described upper molybdenum disk (4), lower molybdenum disk (2) and the shell under closure (5), the shell the inside and outside table top of closure (1) be abradant surface.
7. total head according to claim 1 connects the encapsulation high-voltage semi-conductor device, it is characterized in that: the Coating passivation layer of described upper molybdenum disk (4), lower molybdenum disk (2).
8. total head according to claim 1 connects the encapsulation high-voltage semi-conductor device, it is characterized in that: described semiconductor chip (3) anode and cathode surface-coated thickness is the metal conducting layer of 10 μ m ∽, 50 μ m.
9. total head according to claim 1 and 2 connects the encapsulation high-voltage semi-conductor device, it is characterized in that: described lower molybdenum disk (2) center is provided with location hole; Closure under the described shell (1) center is provided with installing blind; Reference column is installed in the location hole.
10. total head according to claim 1 connects the encapsulation high-voltage semi-conductor device, it is characterized in that: the wafer original material of described semiconductor chip (3) is N-type＜100〉crystal orientation high resistant monocrystalline silicon piece or N-type＜111〉crystal orientation high resistant monocrystalline silicon piece, and adopt phosphorus oxychloride absorption technique technology that original single-chip is carried out pre-absorption and process; Semiconductor chip (3) wafer interior microscopic vertical structure is by P
+P
1N
1P
2N
2Symmetrical structure consists of, wherein, and P
1District, P
2The P that the district diffuses to form for double-deck Al
1District, P
2The district.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220591187 CN202888149U (en) | 2012-11-12 | 2012-11-12 | Full-pressure-welding packaging high-voltage semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220591187 CN202888149U (en) | 2012-11-12 | 2012-11-12 | Full-pressure-welding packaging high-voltage semiconductor device |
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| CN202888149U true CN202888149U (en) | 2013-04-17 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014183432A1 (en) * | 2013-05-17 | 2014-11-20 | 国家电网公司 | Integrated heat-dissipation thyristor |
| CN104167396A (en) * | 2013-05-17 | 2014-11-26 | 国家电网公司 | Novel integrated water cooled thyristor |
| CN104167398A (en) * | 2013-05-17 | 2014-11-26 | 国家电网公司 | Micro-channel heat radiator |
| CN104157582B (en) * | 2014-07-18 | 2017-02-15 | 宁波芯科电力半导体有限公司 | Mold and method for preparing insulating protective layer for table surface of thyristor chip with mold |
| CN103811424B (en) * | 2012-11-12 | 2017-08-29 | 湖北台基半导体股份有限公司 | Total head connects encapsulation high-voltage semi-conductor device |
-
2012
- 2012-11-12 CN CN 201220591187 patent/CN202888149U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811424B (en) * | 2012-11-12 | 2017-08-29 | 湖北台基半导体股份有限公司 | Total head connects encapsulation high-voltage semi-conductor device |
| WO2014183432A1 (en) * | 2013-05-17 | 2014-11-20 | 国家电网公司 | Integrated heat-dissipation thyristor |
| CN104167397A (en) * | 2013-05-17 | 2014-11-26 | 国家电网公司 | Integrated heat dissipation thyristor |
| CN104167396A (en) * | 2013-05-17 | 2014-11-26 | 国家电网公司 | Novel integrated water cooled thyristor |
| CN104167398A (en) * | 2013-05-17 | 2014-11-26 | 国家电网公司 | Micro-channel heat radiator |
| CN104167397B (en) * | 2013-05-17 | 2017-12-05 | 国家电网公司 | A kind of integrated heat dissipation IGCT |
| CN104157582B (en) * | 2014-07-18 | 2017-02-15 | 宁波芯科电力半导体有限公司 | Mold and method for preparing insulating protective layer for table surface of thyristor chip with mold |
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Legal Events
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|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130417 Termination date: 20191112 |