CN103811424B - Total head connects encapsulation high-voltage semi-conductor device - Google Patents
Total head connects encapsulation high-voltage semi-conductor device Download PDFInfo
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- CN103811424B CN103811424B CN201210448143.XA CN201210448143A CN103811424B CN 103811424 B CN103811424 B CN 103811424B CN 201210448143 A CN201210448143 A CN 201210448143A CN 103811424 B CN103811424 B CN 103811424B
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Abstract
The entitled total head of the present invention connects encapsulation high-voltage semi-conductor device, belongs to high-voltage semi-conductor device technical field.It is mainly the existing chip of solution and electrode slice and the problem of tying and there is welding stress and welding cavity is welded by solder high temperature.It is mainly characterized by：Closure is followed successively by crimping contact on closure, lower Mo wafer, semiconductor chip, upper Mo wafer, gate lead component and shell under shell；Closure center is provided with mounting hole on shell；Upper Mo wafer center is provided with positioning hole, and gate lead component is caught in the positioning hole.The present invention has the deformation that can eliminate the generation of chip high-temperature soldering and stress, the characteristics of high-voltage semi-conductor device requirement of more than voltage 5000V or the inch of chip diameter 4 and the above can be met, is mainly used in the high-voltage semi-conductor device in the fields such as high pressure soft starting power supply, high voltage static reactive-load compensation power supply, high voltage pulse power power supply, D.C. high voltage transmission.
Description
Technical field
The present invention relates to high-voltage semi-conductor device, specially total head connects encapsulation high-voltage semi-conductor device, is mainly used in height
Press the fields such as soft start power supply, high voltage static reactive-load compensation power supply, high voltage pulse power power supply, D.C. high voltage transmission.
Background technology
Traditional semiconductor device chip manufacture, welds knot by solder high temperature using chip and electrode slice and forms, there is weldering
Scoop out power and welding cavity, but continuous improvement with semiconductor devices voltage and chip diameter are continued to increase, particularly core
When piece diameter reaches more than 4 inch, voltage reaches more than 5000V, the deformational stress of high-temperature soldering chip makes its reliability can not
The requirement of high-voltage product and high current product is met, is badly in need of using new semiconductor device structure and new semiconductor process technique
To meet new demand.
The content of the invention
In view of the above problems, the present invention provides the semiconductor devices of brand-new internal structure --- and total head connects encapsulation high pressure half
Conductor device, eliminates deformation and the stress of chip high-temperature soldering generation, can meet more than voltage 5000V or the inch of chip diameter 4
High-voltage semi-conductor device requirement above.
The present invention is achieved through the following technical solutions：A kind of total head connects encapsulation high-voltage semi-conductor device, including is sealed under shell
Closure on fitting, lower Mo wafer, semiconductor chip, upper Mo wafer, gate lead component and shell, it is characterized in that：The pipe
Closure center is provided with mounting hole on shell；The upper Mo wafer center is provided with positioning hole, and gate lead component is caught in the positioning hole
It is interior；Closure is followed successively by closure, lower Mo wafer, semiconductor chip, upper Mo wafer, gate lead component and shell under shell
Crimping contact.Above-mentioned part is in element dress pressure outer electrode or during radiator, under shell on closure and shell between closure
Acted on by external pressure and internal part is realized that total head is contacted.
Closure, should with forming seal cavity in closure on shell under shell described in the technology of the present invention solution
Annular seal space is filled with pressure and is less than the inert gas of external pressure, so as to both ensure that each part contacted with each other well, prevents again
Only chip high voltage is struck sparks.
The edge table top moulding of two PN junctions of the semiconductor chip described in the technology of the present invention solution uses two sides
Double negative angle table top moulding；The negative angle in the double each faces of negative angle table top moulding in two sides can be the angle structure of a negative angle or two different angles
Into negative angle, negative angle θ sizes are：0.5°≤θ≤35°.
The double negative angle table tops in semiconductor chip edge two sides described in the technology of the present invention solution are justified provided with annular right-angle
Cylindricality insulation protection falope ring, two-sided surface table top protection carries out table using organic protection materials of multilayer high-purity high-insulativity
Face is passivated.
Falope ring superficies described in the technology of the present invention solution are provided with groove, increase creep age distance.
Closure on upper Mo wafer, the upper and lower surface of lower Mo wafer and shell described in the technology of the present invention solution,
Table top is abradant surface inside and outside closure under shell, and facial plane degree and depth of parallelism requirement are less than 20 μm.
The Coating passivation layer of upper Mo wafer, lower Mo wafer described in the technology of the present invention solution, prevents upper and lower
Mo wafer thermal oxide.
Semiconductor chip anode and cathode surface coating thickness described in the technology of the present invention solution is 10 μm of 50 μm of ∽
Metal conducting layer.
Lower Mo wafer center described in the technology of the present invention solution is provided with Blind locating holes；Under the shell in closure
The heart is provided with installing blind；Locating dowel is installed in installing blind, and coordinated with Blind locating holes.
The chip original material of semiconductor chip described in the technology of the present invention solution is N-type<100>Crystal orientation high resistant
Monocrystalline silicon piece or N-type<111>Crystal orientation high resistant monocrystalline silicon piece, and original single-chip is carried out using POCl3 absorption technique technology
Pre-absorption is handled；The microcosmic vertical structure of semiconductor chip inner wafer is by P+P1N1P2N2Symmetrical structure is constituted, wherein, P1Area, P2
Area is the P that bilayer Al is diffuseed to form1Area, P2Area.
The present invention is due to using closure, lower Mo wafer, semiconductor chip, upper Mo wafer, gate lead group under shell
The total head that closure is constituted on part and shell connects encapsulation high-voltage semi-conductor device, thus semiconductor chip and upper and lower Mo wafer are straight
Connect crimping and weld and tie without high temperature again, the deformation produced and stress thus eliminating the need chip high temperature weldering knot, and then ensure that
The stability and reliability of device property, are conducive to semiconductor devices to develop to larger diameter, higher voltage；Plus semiconductor core
Piece production is preferred with original silicon chip<100>Crystal orientation high resistant silicon chip, with routine<111>Crystal orientation silicon chip is higher compared to crimp strength,
Also ensure that semiconductor chip that there is more preferable compression strength and non-breakable.
The present invention uses the double negative angle table tops in two sides due to using table top moulding at two PN junction edges of semiconductor chip
Formative technology, reduces surface field intensity, is conducive to the raising of semiconductor chip breakdown voltage, and its table top moulding angle, θ is big
It is small to be：0.5°≤θ≤35°；With one side table top moulding compared with, in technique both it is simple and easy to apply it is easy realize, be conducive to platform again
Face surface protection, while reducing cathode plane, the loss of anode surface conductive area, is improved beneficial to chip through-current capability；Double negative angles
Moulding is compared with double positive angle moulding, and breakdown voltage increase is slow, and relative stability is good, is difficult to puncture.
The present invention due in the microcosmic vertical structure of semiconductor chip inner wafer by P+P1N1P2N2Symmetrical structure, and P+
P1N1P2N2Symmetrical structure is deposited, promotes diffusion, multiple oxidation to be lithographically formed respectively respectively using the every kind of impurity sources of AL-AL-P-B,
P1Area, P2Area carries out high vacuum Al pre-depositions twice and twice respectively by using the double-deck Al diffusion techniques of high surfaces concentration
High temperature Al promotes diffusion, forms low concentration knot Al and secondary high concentration shallow junction Al, and then solve component pressure and its deeply
Contradiction between his characteristic, is not only realized with superelevation blocking voltage, while taking into account the dv/dt tolerances for improving element, conducting spy
Property, hot properties.Compared with the conventional chip manufacturing diffusion technique, higher blocking voltage, more excellent device property can be manufactured
Semiconductor chip.
The present invention makes half due to using highfield insulation protection technology in the table top moulding at semiconductor chip edge protection
Conductor chip can undertake larger avalanche breakdown voltage and be difficult to puncture；Highfield insulation protection technology is specially：Two-sided table top
Protection, using multilayer high-purity high-insulativity organic protection materials carry out surface passivation, improve device stability and can
By property.The two-sided table top protection falope ring of semiconductor chip outer layer is processed using silicon rubber formed technology, and its outward appearance is annular
It is right cylindrically shaped, surface creepage distance is added, semiconductor chip is more beneficial for and bears higher surface breakdown voltage；Simultaneously
Be conducive to the two-sided center of semiconductor chip to place upper and lower Mo wafer, upper and lower Mo wafer is positioned using garden in falope ring.
The present invention has the deformation that can eliminate the generation of chip high-temperature soldering and stress, can meet more than voltage 5000V or core
The characteristics of the high-voltage semi-conductor device more than inch of piece diameter 4 is required.Present invention is mainly used for high pressure soft starting power supply, high voltage static
The high-voltage semi-conductor device in the fields such as reactive-load compensation power supply, high voltage pulse power power supply, D.C. high voltage transmission.
Brief description of the drawings
Fig. 1 is that total head of the present invention connects encapsulation high voltage semiconductor device structure schematic diagram.
Fig. 2 is the structural representation of semiconductor chip edge of the present invention and falope ring.
Fig. 3 is semiconductor chip edge of the present invention and the structural representation with groove falope ring.
Fig. 4 is two PN junction edge table top modeling structure schematic diagrames of semiconductor chip of the present invention.
Fig. 5 is the microcosmic vertical structure schematic diagram of semiconductor chip inner wafer of the present invention.
Embodiment
With reference to Fig. 1 to Fig. 5, the invention will be further described.
As shown in Figure 1.Total head connects encapsulation high-voltage semi-conductor device, closure 1, lower Mo wafer 2, semiconductor core under shell
Piece 3, upper Mo wafer 4, gate lead component 6, closure 5 is formed using cold pressing encapsulation on shell.The center of closure 5 is opened on shell
Gate pole lead assemblies 6 are installed in hole, and gate lead component 6 is higher by the surface of closure 5 on shell, is caught in the central through hole of Mo wafer 4,
Upper Mo wafer is positioned.Part table diameter D is：23mm≤D≤140mm, shell thickness H are：23mm≤H≤40mm.Device
Realized entirely under external pressure effect between internal semiconductor chip 3 and the upper and lower closure 1,5 of upper and lower Mo wafer 2,4 and shell
Table top is processed using grinding technics inside and outside closure 1,5 above and below crimping contact, upper and lower Mo wafer 2,4 upper and lower surfaces and shell, table
Facial plane degree and depth of parallelism requirement are less than 20 μm.Upper and lower Mo wafer 2,4 Coating passivating materials, prevent Mo wafer thermal oxide；
The anode and cathode surface coating thickness of semiconductor chip 3 is 10 μm of 50 μm of ∽ metal conducting layer.Device inside is first vacuumized, then fills lazy
Property gas, by the accurate control to aeration quantity in device and air pressure inside, make air pressure inside be less than external pressure, so as to both protect
Demonstrate,prove each part to contact with each other well, prevent chip high voltage from striking sparks again.The center of closure 1 can also be opened under lower Mo wafer 2 and shell
Blind hole, installs locating dowel and is positioned.
Connect using total head after packaging technology, semiconductor chip 3 is directly crimped with upper and lower Mo wafer 2,4 and without sintering, disappeared
Except the stress that chip is produced by sintering warpage, more conducively chip develops to larger diameter and higher voltage.Semiconductor chip 3
Production is preferred with original silicon chip<100>Crystal orientation high resistant silicon chip, with routine<111>Crystal orientation silicon chip is compared, and crimp strength is higher.
As shown in Figure 2 and Figure 3.The two-sided mesa surfaces protection in the edge of semiconductor chip 3, using multilayer high-purity high-insulativity
Organic protection materials carry out surface passivation, chip is undertaken larger avalanche breakdown voltage and is difficult to puncture.Inside and outside bilayer
Mesa passivation is protected, and improves the stability and reliability of element.First layer table top protective layer is high absolutely using diluter high-purity
Organic protection materials of edge, utilize homemade special equipment --- the two-sided automatic glue application photoresist spinner of silicon chip（Utility model patent
Number：201120482060.3）, table top double spread protection is carried out to chip 3；Second layer table top protective layer, using thicker height
The silicon rubber of purity high-insulativity is two-sided to table top and edge carries out the shaping protection of mould injecting glue, and falope ring 7,8 outward appearances are annular
It is right cylindrically shaped；Upper and lower Mo wafer 4,2 is placed at the two-sided center of semiconductor chip 3, and upper and lower molybdenum is justified using garden in Protection glue
Piece 4,2 is positioned.The upper and lower surface of falope ring 8, it is possibility to have groove 9 increases creep age distance.
As shown in Figure 4.The table top moulding at two PN junction edges of semiconductor chip 3, using the double negative angle table top moulding in two sides
Technique, had both reduced surface field intensity, was conducive to the raising of chip breakdown voltage, cathode plane, anode surface was reduced again conductive
The loss of area；Its table top moulding angle, θ size is：0.5°≤θ≤35°.In technique, homemade special equipment-crystalline substance is utilized
Piece big angle angle lap machine, the automatic angle lap of Mechanical course, one side is respectively adopted to chip two sides and carries out table top moulding, both simple and easy to apply,
It is easy to table top protection again.Negative angle can also be two angle θ 1, θ 2.
As shown in Figure 5.The microcosmic vertical structure of the inner wafer of semiconductor chip 3 is by P+P1N1P2N2Symmetrical structure is constituted.P+
P1N1P2N2Symmetrical structure is deposited respectively using the every kind of impurity sources of Al-Al-P-B, diffusion is promoted, multiple oxidation is lithographically formed respectively.
P1Area, P2Area carries out high vacuum Al pre-depositions twice and high temperature Al promotes expansion twice respectively by using double-deck Al diffusion techniques
Dissipate, the low concentration knot Al and secondary high concentration shallow junction Al, and then solve between component pressure and other characteristics deeply of formation
Contradiction, is not only realized with superelevation blocking voltage, while it is special to take into account the dv/dt tolerances for improving element, on state characteristic, high temperature
Property.N2Area is diffused through promotes oxidation diffusion completion twice using phosphorus pre-deposition and high temperature；P+Area is diffused through applies source using spray B
Promote diffusion to complete with high temperature, good Ohmic contact is formed beneficial to conductive layer.
Chip diffusion uses long minority carrier life time absorption techniques.In chip diffusion, POCl3 absorption technique is introduced to original
Beginning silicon single crystal flake carries out n+ layers of Impurity Absorption processing；Meanwhile, trichloroethanes oxidation cleaning pipeline is mixed during diffusible oxydation
Impurity is absorbed, and makees p+ diffusion impurities in anode surface spray boron and is absorbed.By using multiple Impurity Absorption technique, silicon chip is reduced former
The reduction of beginning minority carrier life time, substantially increases the minority carrier life time and parameter uniformity of semiconductor chip, and then ensure that element is joined
Several uniformity and stability.
Claims (4)
1. a kind of total head connects encapsulation high-voltage semi-conductor device, including closure under shell（1）, lower Mo wafer（2）, semiconductor chip
（3）, upper Mo wafer（4）, gate lead component（6）With closure on shell（5）, it is characterized in that：Closure on the shell（5）
Center is provided with mounting hole, and mounting hole installs gate pole lead assemblies 6, and gate lead component 6 is higher by the surface of closure 5 on shell；Institute
State Mo wafer（4）Center is provided with positioning hole, gate lead component（6）It is caught in the positioning hole；Closure under shell（1）, under
Mo wafer（2）, semiconductor chip（3）, upper Mo wafer（4）, gate lead component（6）With closure on shell（5）It is followed successively by pressure
Contact；The semiconductor chip（3）The microcosmic longitudinally asymmetric structure P of inner wafer+P1N1P2N2Middle P1Area, P2Area expands for bilayer Al
Layer is dissipated, high vacuum Al pre-depositions twice are carried out respectively and high temperature Al propulsions twice diffuse to form low concentration knot Al deeply and secondary
High concentration shallow junction Al；The semiconductor chip（3）Two PN junctions edge table top moulding using the double negative angle table top moulding in two sides,
Semiconductor chip（3）Anode and cathode surface coating thickness is 10 μm of 50 μm of ∽ metal conducting layer；Closure under the shell（1）With
Closure on shell（5）Interior formation seal cavity, the annular seal space is filled with the inert gas less than external pressure；Under described
Mo wafer（2）Center is provided with closure under positioning hole, the shell（1）Center, which is provided with to be provided with installing blind, positioning hole, determines
Position post.
2. total head according to claim 1 connects encapsulation high-voltage semi-conductor device, it is characterised in that：The semiconductor chip
（3）Chip original material be the N-type that pre-absorption processing is carried out using POCl3 absorption technique technology<100>Crystal orientation high resistant list
Crystal silicon chip or N-type<111>Crystal orientation high resistant monocrystalline silicon piece；Semiconductor chip（3）The microcosmic vertical structure P of inner wafer+P1N1P2N2
Symmetrical structure is deposited respectively using the every kind of impurity sources of Al-Al-P-B, diffusion is promoted, multiple oxidation is lithographically formed respectively.
3. total head according to claim 1 or 2 connects encapsulation high-voltage semi-conductor device, it is characterised in that：The two sides is double negative
The negative angle in each face at angle is that the angle of two different angles is constituted, negative angle table top moulding, using Mechanical course, the automatic angle lap pair of one side
Chip two sides is carried out respectively.
4. total head according to claim 1 or 2 connects encapsulation high-voltage semi-conductor device, it is characterised in that：The semiconductor core
Piece（3）The double negative angle table tops in edge two sides are provided with the cylindrical insulation protection falope ring of annular right-angle（7、8）, two-sided table top protection silica gel
Ring is processed using silicon rubber formed technology, falope ring（8）Superficies can be provided with groove（9）；Put at the two-sided center of semiconductor chip
Upper and lower Mo wafer is put, upper and lower Mo wafer is positioned using garden in falope ring.
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| CN201210448143.XA CN103811424B (en) | 2012-11-12 | 2012-11-12 | Total head connects encapsulation high-voltage semi-conductor device |
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| CN103811424B true CN103811424B (en) | 2017-08-29 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109686705B (en) * | 2018-12-18 | 2020-06-12 | 董志良 | IGBT device packaging structure |
| CN111081642A (en) * | 2019-11-04 | 2020-04-28 | 全球能源互联网研究院有限公司 | Compression joint type power device packaging structure and packaging method |
| CN111261619A (en) * | 2019-11-22 | 2020-06-09 | 湖北台基半导体股份有限公司 | Suspension crimping power semiconductor module |
| CN113097152A (en) * | 2021-02-26 | 2021-07-09 | 西安中车永电电气有限公司 | Intelligent semiconductor device for 24-pulse rectifier cabinet powered by subway |
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| CN102201434A (en) * | 2010-11-26 | 2011-09-28 | 宜昌市晶石电力电子有限公司 | High-frequency thyristor |
| CN202120918U (en) * | 2011-07-04 | 2012-01-18 | 润奥电子(扬州)制造有限公司 | Crimp-connection IGBT (Insulated Gate Bipolar Transistor) device |
| CN202888149U (en) * | 2012-11-12 | 2013-04-17 | 湖北台基半导体股份有限公司 | Full-pressure-welding packaging high-voltage semiconductor device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1937243A (en) * | 2006-10-19 | 2007-03-28 | 株洲南车时代电气股份有限公司 | Power device explosion-proof method and device |
| CN101615602A (en) * | 2009-07-31 | 2009-12-30 | 株洲南车时代电气股份有限公司 | A kind of semiconductor device and testing mould, method of testing |
| CN102201434A (en) * | 2010-11-26 | 2011-09-28 | 宜昌市晶石电力电子有限公司 | High-frequency thyristor |
| CN202120918U (en) * | 2011-07-04 | 2012-01-18 | 润奥电子(扬州)制造有限公司 | Crimp-connection IGBT (Insulated Gate Bipolar Transistor) device |
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