WO2020220665A1 - Manufacturing process for four-diode integrated chip - Google Patents

Manufacturing process for four-diode integrated chip Download PDF

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WO2020220665A1
WO2020220665A1 PCT/CN2019/121778 CN2019121778W WO2020220665A1 WO 2020220665 A1 WO2020220665 A1 WO 2020220665A1 CN 2019121778 W CN2019121778 W CN 2019121778W WO 2020220665 A1 WO2020220665 A1 WO 2020220665A1
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region
wafer substrate
silicon wafer
film layer
regions
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PCT/CN2019/121778
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French (fr)
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吴念博
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苏州固锝电子股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/298—Semiconductor material, e.g. amorphous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions

Definitions

  • the invention relates to a diode manufacturing process, in particular to a manufacturing process of four diode integrated chips.
  • Diodes are widely used in various circuits. It can be said that there are diodes wherever there is a circuit, using its unidirectional characteristic to convert alternating current into direct current, so that the terminal parts of the circuit can obtain stable direct current input.
  • the existing manufacturing method of the rectifier diode is based on the N-type ⁇ 111> crystal orientation monocrystalline silicon wafer. The upper surface of the silicon wafer is doped with boron once to form a flat P region, and then the lower surface is formed by a phosphorus diffusion. The flat N area is then subjected to photolithography, metallization, alloying and other processes to finally form the PN structure and electrode metal of the diode to make a rectifier diode.
  • the existing diode structure has side wall leakage current, and the device reliability is low;
  • the purpose of the present invention is to provide a manufacturing process of four diode integrated chips.
  • a four-diode integrated chip manufacturing process select a silicon wafer substrate, and then follow the steps below:
  • a first silicon dioxide film layer is formed on both the upper surface and the lower surface of the silicon wafer substrate;
  • the four first spacer regions on the first silicon dioxide film layer on the upper surface and the lower surface of the silicon wafer substrate are respectively masked by photoresist, and the photoresist is used as a mask layer, respectively Etching and removing the exposed first silicon dioxide film layer on the upper surface and the lower surface of the silicon wafer substrate to remove the isolation zone area except the first spacer area;
  • the first doping of the first impurity is performed on the upper surface and the lower surface of the silicon wafer substrate to the isolation zone area, so that all the upper and lower surfaces of the silicon wafer substrate are doped.
  • a first P+ region or a first N+ region is formed in the isolation zone area; the first P+ region on the upper surface is connected to the first P+ region on the lower surface to form the first P+ region through the silicon in the up and down direction
  • the wafer substrate forms an isolation wall, or the first N+ region on the upper surface is connected to the first N+ region on the lower surface to form a first N+ region that penetrates the silicon wafer substrate in the up and down direction to form an isolation wall;
  • the isolation wall isolates four horizontally spaced spacer blocks in the silicon wafer substrate to prepare for the subsequent formation of four diodes;
  • the first silicon dioxide film layer is removed, the upper surface and the lower surface of the silicon wafer substrate are cleaned, and then a second silicon dioxide film layer is formed respectively;
  • the fifth step is to mask the four second spacer regions and the isolation band region on the second silicon dioxide film layer on the upper surface of the silicon wafer substrate by photoresist; the second spacer region and the first spacer region One interval area corresponds to one another, and the area of each second interval area is smaller than that of each first interval area; and the photoresist is used as a mask layer to etch and remove the exposed second silicon dioxide film layer. 4. Peripheral areas outside the second interval area and located in the fourth first interval area;
  • the second impurity doping is performed on the upper surface of the silicon wafer substrate to perform the second impurity doping on the peripheral region, thereby forming an N+ region or P+ region in the peripheral region.
  • the surface of the N+ region The doping concentration of the P+ region is at least 10 21 atm/cm 3 , the diffusion depth is 30-50 ⁇ m, the doping concentration on the surface of the P+ region is at least 10 21 atm/cm 3 , and the diffusion depth is 50-70 ⁇ m;
  • the second silicon dioxide film layer is removed, and the upper and lower surfaces of the silicon wafer substrate are cleaned, and then a third silicon dioxide film layer is formed respectively;
  • the eighth step is to mask the peripheral area and the isolation zone area with photoresist, and use the photoresist as a mask layer to etch and remove the exposed third silicon dioxide film layer.
  • the second spacing area, and the second spacing area is spaced apart from the peripheral area;
  • the ninth step is the second doping of the first impurity, and the first doping is performed on each of the second spacer regions on the upper surface of the silicon wafer substrate, thereby forming a second P+ region or a second spacer region in the second spacer region.
  • Two N+ regions the doping concentration on the surface of the second P+ region is at least 10 21 atm/cm 3 , the diffusion depth is 50-70 ⁇ m, the doping concentration on the surface of the second N+ region is at least 10 21 atm/cm 3 , and the diffusion depth is 30 ⁇ 50 ⁇ m;
  • the tenth step is to open a trench in the edge area of each of the second P+ region or the second N+ region, and the depth of the trench is 20-40um;
  • the third silicon dioxide film layer is removed, and the upper surface of the silicon wafer substrate and the groove are cleaned, and then a polysilicon passivation composite film layer is formed;
  • the twelfth step forming a glass passivation layer on the surface of the polysilicon passivation composite film layer in the trench;
  • the polysilicon passivation composite film layer on the surface of the peripheral region and the second spacer region is removed, and the N+ region or the P+ region, and the second P+ region or the The second N+ zone;
  • a metal layer is deposited on the surfaces of the N+ region or the P+ region and the second P+ region or the second N+ region to form a metal electrode.
  • the silicon wafer substrate has an N-type ⁇ 111> crystal orientation
  • the first impurity doping is boron impurity doping or gallium impurity doping
  • the second impurity doping is phosphorus impurity doping. Impurity or arsenic impurity doping;
  • the first doping of the first impurity on the upper surface and the lower surface of the silicon wafer substrate forms a first P+ region in the isolation zone regions;
  • the second impurity doping on the upper surface of the silicon wafer substrate N+ regions are formed in the peripheral regions of four;
  • the second first impurity doping forms second P+ regions in each of the second spacer regions on the upper surface of the silicon wafer substrate;
  • the trench is opened in the edge area of the second P+ region.
  • the silicon wafer substrate has a P-type ⁇ 111> crystal orientation
  • the first impurity doping is phosphorus impurity doping or arsenic impurity doping
  • the second impurity doping is boron impurity doping. Doped with impurities or gallium impurities;
  • the first doping of the first impurity on the upper surface and the lower surface of the silicon wafer substrate forms a first N+ region in the isolation zone regions;
  • the second impurity doping on the upper surface of the silicon wafer substrate A P+ region is formed in the peripheral region of four;
  • the second first impurity doping forms a second N+ region in each of the second spacer regions on the upper surface of the silicon wafer substrate;
  • the trench is opened in the edge area of the second N+ region.
  • the distance between the second separation area and the peripheral area is 200-300um.
  • the process conditions for forming the first silicon dioxide thin film layer, the second silicon dioxide thin film layer and the third silicon dioxide thin film layer are as follows: 30 ⁇ 5 minutes of oxygen atmosphere, 480 ⁇ 10 minutes of water vapor atmosphere, and finally 30 ⁇ 5 minutes of oxygen atmosphere.
  • the silicon wafer substrate has an N-type ⁇ 111> crystal orientation
  • the process conditions for the phosphorus impurity doping are: first in a furnace tube at 1100°C ⁇ 0.5°C for 2 ⁇ 0.05 hours, atmosphere Phosphorus oxychloride; soak in hydrofluoric acid for 30 ⁇ 5 minutes after being out of the furnace, and then in the furnace tube at 1250 ⁇ 0.5 ° C for 4 ⁇ 0.05 hours, and the atmosphere is N 2 to form the The N+ area.
  • the silicon wafer substrate has an N-type ⁇ 111> crystal orientation
  • the process conditions for the second doping of boron impurities are: firstly, a liquid boron source is coated on the surface of the second spacer region, and In the furnace tube at 1150 ⁇ 0.5°C, the time is 2 ⁇ 0.05 hours, the atmosphere is nitrogen; after the furnace is soaked in hydrofluoric acid for 30 ⁇ 5 minutes, then, in the furnace tube at 1250 ⁇ 0.5°C, the time is 18 ⁇ 0.05 hours, and the atmosphere is nitrogen. Under conditions, the second P+ region is formed by diffusion of boron atoms.
  • step eleven the polysilicon passivation composite thin film layer is deposited and formed by a CVD process, and the process conditions are as follows: firstly, pass silane gas and dioxide at a temperature of 650 ⁇ 1°C Nitrogen gas, the time is 25 ⁇ 1 minutes, wherein the flow rate of the silane gas is 130 ⁇ 5ml per minute, and the flow rate of the nitrous oxide gas is 30 ⁇ 2ml per minute; then, at a temperature of 780 ⁇ 1°C Continue to pass in silane gas and nitrous oxide gas for 15 ⁇ 0.5 minutes, and the flow rates of the two gases are SiH 4 25 ⁇ 5ml per minute and N 2 O 80 ⁇ 5ml per minute; finally a layer containing The polysilicon passivation composite film layer of an oxygen polysilicon passivation film and a silicon dioxide film.
  • step twelve the process conditions for forming the glass passivation layer in the trench are: filling the trench with glass paste with a thickness of 25-35 ⁇ m, and then sintering at high temperature to form a compact
  • the glass passivation layer has a temperature of 830 ⁇ 10°C and a time of 30 ⁇ 5 minutes.
  • the silicon wafer substrate has an N-type ⁇ 111> crystal orientation, the first P+ region is a cross shape, and the silicon wafer substrate is horizontally isolated into four places arranged in a square shape.
  • the silicon wafer substrate has a P-type ⁇ 111> crystal orientation, and the first N+ region is cross-shaped, and the silicon wafer substrate is horizontally separated into four spacer blocks arranged in a square shape.
  • a four-diode integrated chip includes a silicon wafer substrate in which a first P+ region or a first N+ region is formed through the first doping of first impurities, and the first P+ region or the An N+ region penetrates the silicon wafer substrate in the up and down direction to form an isolation wall, and four horizontally spaced spacers are isolated from the silicon wafer substrate;
  • each spacer block is formed with an N+ region or a P+ region by second impurity doping, and a second P+ region or a second N+ region is formed by the second first impurity doping, and the N+ region and the first
  • the P+ zone and the second P+ zone are both arranged at intervals, or the P+ zone is arranged at intervals with the first N+ zone and the second N+ zone;
  • the edge area of the second P+ region or the second N+ region is provided with a trench
  • the upper surface of the silicon wafer substrate is covered with a layer of polysilicon passivation compound on the peripheral area of the N+ zone or the P+ zone, the peripheral area of the second P+ zone or the second N+ zone, and the trench Thin film layer; the groove is also filled with glass glue, and a glass passivation layer is formed by high-temperature sintering;
  • a metal layer is deposited on the surface of the N+ region or P+ region and the second P+ region or the second N+ region to form a metal electrode.
  • the silicon wafer substrate has an N-type ⁇ 111> crystal orientation, and the N+ region surrounds the second P+ region, or the N+ region and the second P+ region are horizontally parallel.
  • the first P+ area is in a cross shape, and the silicon wafer substrate is horizontally separated into four spacer blocks arranged in a square shape.
  • the distance between the N+ zone and the second P+ zone is 200-300um.
  • the groove is opened in the edge area of the second P+ region.
  • the silicon wafer substrate has a P-type ⁇ 111> crystal orientation, and the P+ region surrounds the second N+ region, or the P+ region and the second N+ region are horizontally parallel.
  • the first N+ area is in a cross shape, and the silicon wafer substrate is horizontally separated into four spacer blocks arranged in a square shape.
  • the distance between the P+ zone and the second N+ zone is 200-300um.
  • the groove is opened in the edge area of the second N+ region.
  • the depth of the groove is 20-40um.
  • the thickness of the glass glue is 25-35 ⁇ m.
  • the polysilicon passivation composite thin film layer is deposited and formed by a CVD process.
  • the process conditions are as follows: First, pass silane gas and nitrous oxide gas at a temperature of 650 ⁇ 1°C for a time of 25 ⁇ 1 minute, wherein the flow rate of the silane gas is 130 ⁇ 5ml per minute, and the flow rate of the nitrous oxide gas is 30 ⁇ 2ml per minute; then, continue to pass the silane gas under the temperature condition of 780 ⁇ 1°C And nitrous oxide gas, the time is 15 ⁇ 0.5 minutes, and the flow rates of the two gases are 25 ⁇ 5ml per minute for SiH 4 and 80 ⁇ 5ml per minute for N 2 O; finally a layer of oxygen-containing polysilicon passivation film and The polysilicon passivation composite film layer of the silicon dioxide film.
  • the present invention is a manufacturing process of four diode integrated chips; the steps include: 1. forming a first silicon dioxide film layer on both the upper and lower surfaces of a silicon wafer substrate; 2. etching and removing the upper and lower surfaces The isolation zone area of the silicon oxide film layer; 3. The first doping of the isolation zone area forms the first P+ region or the first N+ region, which penetrates in the up and down direction to form an isolation wall, and isolates four spacers in the silicon wafer substrate 4. Remove the first silicon dioxide film layer, clean and form the second silicon dioxide film layer; 5. Etch and remove the four peripheral areas on the second silicon dioxide film layer; 6. Perform the four peripheral areas The second doping forms the N+ region or the P+ region; 7.
  • the second spacer region is first doped to form a second P+ region or a second N+ region; 10.
  • a trench is opened in the edge region of the second P+ region or the second N+ region; 11.
  • Combine the polysilicon passivation on the surface of the peripheral area and the second spacer area The thin film layer is removed, and the N+ region or P+ region and the second P+ region or the second N+ region are exposed; 14.
  • a metal layer is deposited on the surface of the N+ region or P+ region and the second P+ region or the second N+ region to form a metal electrode.
  • the advantages of the present invention include:
  • the U-shaped PN junction is formed by selective diffusion, which increases the effective area of the PN junction and significantly reduces the power consumption of the diode when it is used in the circuit;
  • the present invention is different from the conventional planar process on the one hand.
  • the conventional planar process can generally only achieve 600V. If it needs to reach 800 or more than 1000V, a complicated process is required, that is, it is realized by multiple voltage divider rings, and a larger chip is required. Area and complex process, the processing cost needs to be at least doubled to complete; on the other hand, it is different from the conventional trench process of 100-140um.
  • the conventional trench process requires more than 3 times the chemical corrosion of the deep trench.
  • the area of the glass passivation method increases the chance of contamination by impurities, resulting in high leakage current.
  • deep trenches can also cause problems such as warpage of the silicon wafer and increased process fragmentation rate.
  • the applicable products of the present invention include ordinary rectifier diodes, fast recovery diodes, TVS protection diodes and voltage regulator tubes.
  • the present invention can greatly simplify the packaging, thereby reducing material costs and labor costs, which is beneficial to reduce the processing cost of large-scale diode semiconductor devices, and realizes that the processing cost can be reduced by up to 30%, and Can improve the production efficiency per unit time. It can also reduce the energy consumption of the client, which is more conducive to reducing the waste of resources (eliminating the consumption of resin, solder, copper leads and other materials), and contributes to environmental protection.
  • Figure 1 is a schematic diagram of the first step of the embodiment of the utility model
  • Figure 2 is a schematic top view of the second step of the embodiment of the utility model
  • Figure 3 is a schematic diagram of the principle of the second step of the embodiment of the utility model
  • Figure 4 is a schematic diagram of the principle of the third step of the embodiment of the utility model
  • Figure 5 is a schematic diagram of the principle of the fourth step of the embodiment of the utility model
  • Figure 6 is a schematic diagram of the principle of the fifth step of the embodiment of the utility model.
  • Figure 7 is a schematic diagram of the principle of the sixth step of the embodiment of the utility model.
  • Fig. 8 is a schematic diagram of the principle of the seventh step of the embodiment of the utility model.
  • Figure 9 is a schematic diagram of the principle of the eighth step of the embodiment of the utility model.
  • Figure 10 is a schematic diagram of the principle of the ninth step of the embodiment of the utility model.
  • Figure 11 is a schematic diagram of the principle of the tenth step of the embodiment of the utility model
  • Figure 12 is a schematic diagram of the principle of the eleventh step of the embodiment of the utility model.
  • Figure 13 is a schematic diagram of the principle of the twelfth step of the embodiment of the utility model
  • Figure 14 is a schematic diagram of the principle of the thirteenth step of the embodiment of the utility model.
  • Figure 15 is a schematic diagram of the principle of the fourteenth step of the embodiment of the utility model
  • Fig. 16 is a schematic structural diagram of an embodiment of the utility model (a top view).
  • Embodiment Refer to Figures 1-16, a manufacturing process of four diode integrated chips; select N-type ⁇ 111> crystal orientation or P-type ⁇ 111> crystal orientation silicon wafer substrate 1, this embodiment uses Take the N-type ⁇ 111> crystal orientation as an example to explain, and then follow the steps below:
  • a first silicon dioxide film layer 2 is formed on both the upper surface and the lower surface of the silicon wafer substrate 1;
  • the four first spacer regions 3 on the first silicon dioxide film layer 2 on the upper and lower surfaces of the silicon wafer substrate are masked by photoresist, and
  • the photoresist is used as a mask layer to etch and remove the exposed first silicon dioxide film layer 2 on the upper and lower surfaces of the silicon wafer substrate 1 respectively, and remove the isolation zone 4 except the first spacer region 3 ;
  • the first doping of the first impurity is performed on the upper surface and the lower surface of the silicon wafer substrate 1 to the isolation zone region 4, and the first impurity doping
  • the impurity is doped with boron impurity (it can also be doped with gallium impurity), and the doping concentration is 1-9*10 19 atm/cm 3 , so that the isolation zone 4 on the upper and lower surfaces of the silicon wafer substrate 1 A first P+ region 5 is formed in both of them, and the first P+ region 5 on the upper surface is connected to the first P+ region 5 on the lower surface, forming the first P+ region 5 to penetrate the silicon wafer substrate 1 in the vertical direction An isolation wall is formed, and four horizontally spaced spacer blocks 6 are isolated from the silicon wafer substrate 1 to prepare for the subsequent formation of four diodes;
  • the first silicon dioxide film layer 2 is removed, and the upper and lower surfaces of the silicon wafer substrate 1 are cleaned, and then a layer of second silicon dioxide is formed respectively. ⁇ 7;
  • the fifth step is to mask the four second spacer regions 8 and the isolation band region 4 on the second silicon dioxide film layer 7 on the upper surface of the silicon wafer substrate 1 with photoresist;
  • the second interval regions 8 correspond to the first interval regions 3 in a one-to-one manner, the area of each second interval region 8 is smaller than that of each first interval region 3, and each second interval region 8 is located in the middle of each first interval region 3
  • the photoresist as a mask layer to etch and remove the exposed second silicon dioxide film layer 7 except for the fourth second spacer region 8 and located in the fourth first spacer
  • the peripheral region 9 is doped with the second impurity.
  • the two impurity doping is phosphorus impurity doping (or arsenic impurity doping), thereby forming an N+ region 10 in the peripheral region 9.
  • the doping concentration on the surface of the N+ region 10 is at least 10 21 atm/cm 3 , which is diffused
  • the depth is 30-50 ⁇ m; the process conditions of phosphorus impurity doping are: first in the furnace tube at 1100°C ⁇ 0.5°C, the time is 2 ⁇ 0.05 hours, the atmosphere is phosphorus oxychloride (POCl 3 ); HF) 30 ⁇ 5 minutes, then, in a furnace tube at 1250 ⁇ 0.5°C for 4 ⁇ 0.05 hours, and the atmosphere is N 2 to form the N+ zone 10 in the peripheral region 9 through the diffusion of phosphorus atoms .
  • the second silicon dioxide film layer 7 is removed, and the upper and lower surfaces of the silicon wafer substrate 1 are cleaned, and then a layer of third silicon dioxide is formed respectively. ⁇ 11;
  • the eighth step is to mask the peripheral area 9 and the isolation zone area 4 with photoresist, and use the photoresist as a mask layer to etch and remove the exposed third Four of the second spacer regions 8 on the silicon dioxide film layer 11, and the second spacer regions 8 and the peripheral regions 9 are spaced apart;
  • the ninth step the second doping with boron impurity (or gallium impurity doping), the upper surface of the silicon wafer substrate 1 is doped with boron on each of the second spacer regions 8 , Thereby forming a second P+ region 12 in the second spacer region 8, the doping concentration of the surface of the second P+ region 12 is at least 10 21 atm/cm 3 , and the diffusion depth is 50-70 ⁇ m;
  • the process conditions for the second doping of boron impurities are as follows: firstly, a liquid boron source is coated on the surface of the second separation area 8 in a furnace tube of 1150 ⁇ 0.5°C for 2 ⁇ 0.05 hours, and the atmosphere is nitrogen (N 2 ); After the furnace is soaked in hydrofluoric acid (HF) for 30 ⁇ 5 minutes, then, in the 1250 ⁇ 0.5 °C furnace tube, the time is 18 ⁇ 0.05 hours, and the atmosphere is nitrogen (N 2 ).
  • the second spacer region 8 forms the second P+ region 12 by diffusion of boron atoms.
  • trenches 13 are formed in the edge regions of each of the second P+ regions 12, thereby exposing the PN junction on the upper surface of the silicon wafer substrate 1, forming a diode device region, and trenches 13
  • the depth is 20 ⁇ 40um
  • the damage layer on the surface of the silicon wafer substrate 1 can be removed and the leakage current of the device can be reduced. Under the protection of the thin film layer 14, the leakage current on the surface of the device is reduced to improve reliability.
  • the third silicon dioxide film layer 11 is removed, and the upper surface of the silicon wafer substrate 1 and the trench 13 are cleaned, and then a layer of polysilicon passivation is formed.
  • the polysilicon passivation composite thin film layer 14 is deposited and formed by a CVD process (chemical vapor deposition process), and the process conditions are as follows: firstly, pass silane (SiH 4 ) gas and two oxides at a temperature of 650 ⁇ 1° C.
  • Nitrogen (N 2 O) gas the time is 25 ⁇ 1 minute, wherein the flow rate of the silane (SiH 4 ) gas is 130 ⁇ 5 ml per minute, and the flow rate of the nitrous oxide (N 2 O) gas is per minute 30 ⁇ 2ml; then, continue to pass silane (SiH 4 ) gas and nitrous oxide (N 2 O) gas under the temperature condition of 780 ⁇ 1°C for 15 ⁇ 0.5 minutes, and the flow rates of the two gases are respectively SiH 4 is 25 ⁇ 5 ml per minute and N 2 O is 80 ⁇ 5 ml per minute; finally, a layer of polysilicon passivation composite film layer 14 containing oxygen-containing polysilicon passivation film and silicon dioxide film is formed.
  • physical parameters such as the film thickness, composition, unit cell size, and refractive index of the polysilicon passivation composite thin film layer 14 that meet the requirements are achieved.
  • a glass passivation layer 15 is formed on the surface of the polysilicon passivation composite film layer 14 in the trench 13;
  • the process conditions for forming the glass passivation layer 15 in the trench 13 are: filling the trench 13 with glass paste with a thickness of 25-35 ⁇ m, and then forming a dense glass passivation layer 15 through high temperature sintering.
  • the temperature is 830 ⁇ 10°C, and the time is 30 ⁇ 5 minutes.
  • the polysilicon passivation composite film layer 14 on the surface of the peripheral region 9 and the second spacer region 8 is removed, and the N+ region 10 and the second P+ are exposed.
  • a metal layer 16 is deposited on the surfaces of the N+ region 10 and the second P+ region 12 to form a metal electrode.
  • the distance d between the second separation area 8 and the peripheral area 9 is 200-300um.
  • the reason for choosing this distance parameter is that the design of the distance between the second P+ region 12 and the N+ region 10 must ensure a certain range. When an electric field is applied, the space charge region of the diode PN junction will expand, and the second P+ region 12 and N+ If the distance of the region 10 is too close, the expansion of the space charge region will be insufficient. The diode will break down in advance and fail to meet the designed voltage requirement. If it is too wide, it will lead to an increase in size and waste of materials.
  • the process conditions for forming the first silicon dioxide thin film layer 2, the second silicon dioxide thin film layer 7 and the third silicon dioxide thin film layer 11 are as follows: in the furnace tube of 1150 ⁇ 0.5° C. ⁇ 5 minutes of oxygen atmosphere, 480 ⁇ 10 minutes of water vapor atmosphere, and finally 30 ⁇ 5 minutes of oxygen atmosphere.
  • a four-diode integrated chip includes a silicon wafer substrate 1, which has an N-type ⁇ 111> crystal orientation; the silicon wafer substrate 1 passes through the first boron Impurity doping forms a first P+ region 5, which penetrates the silicon wafer substrate 1 in the up and down direction to form an isolation wall, and four horizontally spaced spacers 6 are isolated in the silicon wafer substrate 1.
  • the first P+ region 5 is cross-shaped, and isolates the silicon wafer substrate 1 in the horizontal direction from the four spacer blocks 6 arranged in a square shape.
  • each spacer 6 is doped with phosphorus impurities to form an N+ region 10, and through the second boron impurity doping, a second P+ region 12 is formed, and the N+ region 10 is connected to the first P+ region 5 and the second
  • the P+ regions 12 are arranged at intervals; the N+ region 10 surrounds the second P+ region 12, or the N+ region 10 and the second P+ region 12 are horizontally parallel.
  • the distance d between the N+ zone 10 and the second P+ zone 12 is 200-300um.
  • the doping concentration on the surface of the N+ region 10 is at least 10 21 atm/cm 3 , and the diffusion depth is 30-50 ⁇ m; the doping concentration on the surface of the second P+ region 12 is at least 10 21 atm/cm 3 , and the diffusion depth is 50- 70 ⁇ m.
  • a trench 13 is opened in the edge area of the second P+ region 12; the depth of the trench 13 is 20-40um.
  • the upper surface of the silicon wafer substrate 1 is covered with a polysilicon passivation composite film layer 14 on the peripheral area of the N+ region 10, the peripheral area of the second P+ region 12, and the surface of the trench 13;
  • the groove 13 is also filled with glass glue, the thickness of the glass glue is 25-35 ⁇ m, and the glass passivation layer 15 is formed by high-temperature sintering.
  • a metal layer 16 is deposited on the surface of the N+ region 10 and the second P+ region 12 to form a metal electrode.
  • the polysilicon passivation composite thin film layer 14 is deposited and formed by a CVD process (chemical vapor deposition process), and the process conditions are as follows: first, pass silane gas and nitrous oxide gas at a temperature of 650 ⁇ 1°C , The time is 25 ⁇ 1 minutes, wherein the flow rate of the silane gas is 130 ⁇ 5ml per minute, and the flow rate of the nitrous oxide gas is 30 ⁇ 2ml per minute; then, continue under the temperature condition of 780 ⁇ 1°C Inject silane gas and nitrous oxide gas for 15 ⁇ 0.5 minutes, and the flow rates of the two gases are 25 ⁇ 5ml per minute for SiH 4 and 80 ⁇ 5ml per minute for N 2 O; finally a layer of oxygen-containing polysilicon is formed The polysilicon passivation composite film layer 14 of passivation film and silicon dioxide film.
  • CVD process chemical vapor deposition process
  • the metal electrodes corresponding to the N+ region 10 and the second P+ region 12 on different diode particles can be connected through pins to make them full-bridge rectified Product, or a product with a half bridge and two diodes.

Abstract

A manufacturing process for a four-diode integrated chip, comprising steps of: forming first silicon dioxide thin film layers on an upper surface and a lower surface of a silicon substrate; etching and removing isolation strip regions of the first silicon dioxide thin film layers on the upper surface and the lower surface; performing first doping on the isolation strip regions to form a first P+ region, which penetrates through in a vertical direction to form an isolation wall, so as to partition the silicon substrate into four spacer blocks; forming second silicon dioxide thin film layers; etching and removing surrounding regions on the second silicon dioxide thin film layers; performing second doping on the surrounding regions to form N+ regions; forming third silicon dioxide thin film layers; etching and removing four second spacer regions on the third silicon dioxide thin film layers; performing first doping on the second spacer regions to form second P+ regions; forming channels in edge regions of the second P+ regions; forming a poly-silicon passivation composite thin film layer; forming a glass passivation layer in the channel; exposing the N+ regions and the second P+ regions; and depositing metal layers on surfaces of the N+ regions and the second P+ regions to form metal electrodes.

Description

一种四颗二极管集成芯片的制造工艺Manufacturing process of four-diode integrated chip 技术领域Technical field
本发明涉及一种二极管制造工艺，具体涉及一种四颗二极管集成芯片的制造工艺。The invention relates to a diode manufacturing process, in particular to a manufacturing process of four diode integrated chips.
背景技术Background technique
二极管广泛应用在各种电路中，可以说凡有电路处皆有二级管，利用其单向导通的特性把交流电转化为直流电，使电路的终端部件可以获得稳定的直流电输入。现有整流二极管的制造方法是以N型〈111〉晶向单晶硅片为基本材料，在该硅片的上表面进行一次硼掺杂形成平的P区，然后在下表面进行一次磷扩散形成平的N区，然后再进行光刻、金属化、合金等工序，最终形成二极管的PN结构和电极金属，制成整流二极管。Diodes are widely used in various circuits. It can be said that there are diodes wherever there is a circuit, using its unidirectional characteristic to convert alternating current into direct current, so that the terminal parts of the circuit can obtain stable direct current input. The existing manufacturing method of the rectifier diode is based on the N-type <111> crystal orientation monocrystalline silicon wafer. The upper surface of the silicon wafer is doped with boron once to form a flat P region, and then the lower surface is formed by a phosphorus diffusion. The flat N area is then subjected to photolithography, metallization, alloying and other processes to finally form the PN structure and electrode metal of the diode to make a rectifier diode.
现有技术的不足包括：The shortcomings of existing technology include:
一、当需要组成桥式整流电路时，通常需要四个独立的二极管进行电连接，不利于产品的小型化，且工艺流程复杂，制造成本较高；1. When it is necessary to form a bridge rectifier circuit, four independent diodes are usually required for electrical connection, which is not conducive to the miniaturization of the product, and the process flow is complicated and the manufacturing cost is high;
二、现有二极管结构存在侧壁的漏电流，器件可靠性低；2. The existing diode structure has side wall leakage current, and the device reliability is low;
三、上述现有二极管在工作的过程中，反向截止，正向导通，在正向电流导通过程中由于其自身的正向压降存在，二极管会不断发热，P＝U*I(这里U是正向压降，I是代表正常工作的电流)。二极管发热的这部分功耗不但由于持续的发热而影响器件的可靠性和使用寿命，而且消耗大量无谓的能量，这和目前绿色节能的环保要求显得格格不入。3. In the working process of the above-mentioned existing diode, the reverse is cut off and the forward conducts. During the forward current conduction process, due to its own forward voltage drop, the diode will continue to heat up, P=U*I(here U is the forward voltage drop, I is the current that represents normal operation). This part of the power consumption of the diode heating not only affects the reliability and service life of the device due to continuous heating, but also consumes a large amount of unnecessary energy, which is incompatible with the current environmental protection requirements of green energy saving.
因此，如何解决上述现有技术存在的不足，便成为本发明所要研究解决的课题。Therefore, how to solve the above-mentioned shortcomings of the prior art has become the subject of the present invention.
发明内容Summary of the invention
本发明的目的是提供一种四颗二极管集成芯片的制造工艺。The purpose of the present invention is to provide a manufacturing process of four diode integrated chips.
为达到上述目的，本发明采用的技术方案是：In order to achieve the above objective, the technical solution adopted by the present invention is:
一种四颗二极管集成芯片的制造工艺；选择硅片衬底，然后按以下步骤进行操作：A four-diode integrated chip manufacturing process; select a silicon wafer substrate, and then follow the steps below:
第一步，在所述硅片衬底上表面和下表面均形成一层第一二氧化硅薄膜层；In the first step, a first silicon dioxide film layer is formed on both the upper surface and the lower surface of the silicon wafer substrate;
第二步，通过光刻胶分别掩膜硅片衬底上表面及下表面的所述第一二氧化硅薄膜层上的四第一间隔区域，并以此光刻胶作为掩膜层，分别刻蚀并去除硅片衬底上表面及下表面裸露的所述第一二氧化硅薄膜层除去四第一间隔区域之外的隔离带区域；In the second step, the four first spacer regions on the first silicon dioxide film layer on the upper surface and the lower surface of the silicon wafer substrate are respectively masked by photoresist, and the photoresist is used as a mask layer, respectively Etching and removing the exposed first silicon dioxide film layer on the upper surface and the lower surface of the silicon wafer substrate to remove the isolation zone area except the first spacer area;
第三步，第一次第一杂质掺杂，在所述硅片衬底上表面及下表面对所述隔离带区域进行第一掺杂，从而在硅片衬底上表面及下表面的所述隔离带区域中均形成第一P+区或第一N+区；上表面的所述第一P+区与下表面的所述第一P+区连接，构成第一P+区在上下方向贯通所述硅片衬底形成隔离墙，或者，上表面的所述第一N+区与下表面的所述第一N+区连接，构成第一N+区在上下方向贯通所述硅片衬底形成隔离墙；通过所述隔离墙在硅片衬底 中隔离出四个水平间隔布置的间隔块，为后续形成四颗二极管做好前期准备；In the third step, the first doping of the first impurity is performed on the upper surface and the lower surface of the silicon wafer substrate to the isolation zone area, so that all the upper and lower surfaces of the silicon wafer substrate are doped. A first P+ region or a first N+ region is formed in the isolation zone area; the first P+ region on the upper surface is connected to the first P+ region on the lower surface to form the first P+ region through the silicon in the up and down direction The wafer substrate forms an isolation wall, or the first N+ region on the upper surface is connected to the first N+ region on the lower surface to form a first N+ region that penetrates the silicon wafer substrate in the up and down direction to form an isolation wall; The isolation wall isolates four horizontally spaced spacer blocks in the silicon wafer substrate to prepare for the subsequent formation of four diodes;
第四步，将所述第一二氧化硅薄膜层去除，并对所述硅片衬底上表面和下表面进行清洗，然后分别形成一层第二二氧化硅薄膜层；In the fourth step, the first silicon dioxide film layer is removed, the upper surface and the lower surface of the silicon wafer substrate are cleaned, and then a second silicon dioxide film layer is formed respectively;
第五步，通过光刻胶掩膜硅片衬底上表面的所述第二二氧化硅薄膜层上的四第二间隔区域以及所述隔离带区域；所述第二间隔区域与所述第一间隔区域一一对应，各第二间隔区域的面积小于各第一间隔区域；并以所述光刻胶作为掩膜层，刻蚀并去除裸露的所述第二二氧化硅薄膜层上除去四所述第二间隔区域之外的且位于四所述第一间隔区域中的周边区域；The fifth step is to mask the four second spacer regions and the isolation band region on the second silicon dioxide film layer on the upper surface of the silicon wafer substrate by photoresist; the second spacer region and the first spacer region One interval area corresponds to one another, and the area of each second interval area is smaller than that of each first interval area; and the photoresist is used as a mask layer to etch and remove the exposed second silicon dioxide film layer. 4. Peripheral areas outside the second interval area and located in the fourth first interval area;
第六步，第二杂质掺杂，在所述硅片衬底上表面对四所述周边区域进行第二杂质掺杂，从而在所述周边区域中形成N+区或P+区，该N+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm，P+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm； In the sixth step, the second impurity doping is performed on the upper surface of the silicon wafer substrate to perform the second impurity doping on the peripheral region, thereby forming an N+ region or P+ region in the peripheral region. The surface of the N+ region The doping concentration of the P+ region is at least 10 21 atm/cm 3 , the diffusion depth is 30-50 μm, the doping concentration on the surface of the P+ region is at least 10 21 atm/cm 3 , and the diffusion depth is 50-70 μm;
第七步，将所述第二二氧化硅薄膜层去除，并对所述硅片衬底上表面和下表面进行清洗，然后分别形成一层第三二氧化硅薄膜层；In the seventh step, the second silicon dioxide film layer is removed, and the upper and lower surfaces of the silicon wafer substrate are cleaned, and then a third silicon dioxide film layer is formed respectively;
第八步，通过光刻胶掩膜所述周边区域以及所述隔离带区域，并以此光刻胶作为掩膜层，刻蚀并去除裸露的所述第三二氧化硅薄膜层上的四所述第二间隔区域，且第二间隔区域与所述周边区域间隔设置；The eighth step is to mask the peripheral area and the isolation zone area with photoresist, and use the photoresist as a mask layer to etch and remove the exposed third silicon dioxide film layer. The second spacing area, and the second spacing area is spaced apart from the peripheral area;
第九步，第二次第一杂质掺杂，在所述硅片衬底上表面对各所述第二间隔区域进行第一掺杂，从而在第二间隔区域中形成第二P+区或第二N+区，该第二P+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm，第二N+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm； The ninth step is the second doping of the first impurity, and the first doping is performed on each of the second spacer regions on the upper surface of the silicon wafer substrate, thereby forming a second P+ region or a second spacer region in the second spacer region. Two N+ regions, the doping concentration on the surface of the second P+ region is at least 10 21 atm/cm 3 , the diffusion depth is 50-70 μm, the doping concentration on the surface of the second N+ region is at least 10 21 atm/cm 3 , and the diffusion depth is 30 ～50μm;
第十步，在各所述第二P+区或所述第二N+区的边缘区域开沟槽，沟槽的深度为20～40um；The tenth step is to open a trench in the edge area of each of the second P+ region or the second N+ region, and the depth of the trench is 20-40um;
第十一步，将所述第三二氧化硅薄膜层去除，并对所述硅片衬底上表面以及所述沟槽进行清洗，然后形成一层多晶硅钝化复合薄膜层；In the eleventh step, the third silicon dioxide film layer is removed, and the upper surface of the silicon wafer substrate and the groove are cleaned, and then a polysilicon passivation composite film layer is formed;
第十二步，在所述沟槽中的多晶硅钝化复合薄膜层表面形成一层玻璃钝化层；The twelfth step, forming a glass passivation layer on the surface of the polysilicon passivation composite film layer in the trench;
第十三步，将所述周边区域以及所述第二间隔区域表面的多晶硅钝化复合薄膜层去除，并裸露出所述N+区或所述P+区，以及所述第二P+区或所述第二N+区；In the thirteenth step, the polysilicon passivation composite film layer on the surface of the peripheral region and the second spacer region is removed, and the N+ region or the P+ region, and the second P+ region or the The second N+ zone;
第十四步，在所述N+区或所述P+区以及所述第二P+区或所述第二N+区的表面均沉积金属层，形成金属电极。In the fourteenth step, a metal layer is deposited on the surfaces of the N+ region or the P+ region and the second P+ region or the second N+ region to form a metal electrode.
上述技术方案中的有关内容解释如下：The relevant content in the above technical solution is explained as follows:
1.上述方案中，所述硅片衬底为N型〈111〉晶向，所述第一杂质掺杂为硼杂质掺杂或镓杂质掺杂，所述第二杂质掺杂为磷杂质掺杂或砷杂质掺杂；1. In the above solution, the silicon wafer substrate has an N-type <111> crystal orientation, the first impurity doping is boron impurity doping or gallium impurity doping, and the second impurity doping is phosphorus impurity doping. Impurity or arsenic impurity doping;
所述第一次第一杂质掺杂在硅片衬底上表面及下表面的所述隔离带区域中均形成第一P+ 区；所述第二杂质掺杂在所述硅片衬底上表面的四所述周边区域中形成N+区；所述第二次第一杂质掺杂在所述硅片衬底上表面的各所述第二间隔区域中形成第二P+区；The first doping of the first impurity on the upper surface and the lower surface of the silicon wafer substrate forms a first P+ region in the isolation zone regions; the second impurity doping on the upper surface of the silicon wafer substrate N+ regions are formed in the peripheral regions of four; the second first impurity doping forms second P+ regions in each of the second spacer regions on the upper surface of the silicon wafer substrate;
所述沟槽开设于所述第二P+区的边缘区域。The trench is opened in the edge area of the second P+ region.
2.上述方案中，所述硅片衬底为P型〈111〉晶向，所述第一杂质掺杂为磷杂质掺杂或砷杂质掺杂，所述第二杂质掺杂为硼杂质掺杂或镓杂质掺杂；2. In the above solution, the silicon wafer substrate has a P-type <111> crystal orientation, the first impurity doping is phosphorus impurity doping or arsenic impurity doping, and the second impurity doping is boron impurity doping. Doped with impurities or gallium impurities;
所述第一次第一杂质掺杂在硅片衬底上表面及下表面的所述隔离带区域中均形成第一N+区；所述第二杂质掺杂在所述硅片衬底上表面的四所述周边区域中形成P+区；所述第二次第一杂质掺杂在所述硅片衬底上表面的各所述第二间隔区域中形成第二N+区；The first doping of the first impurity on the upper surface and the lower surface of the silicon wafer substrate forms a first N+ region in the isolation zone regions; the second impurity doping on the upper surface of the silicon wafer substrate A P+ region is formed in the peripheral region of four; the second first impurity doping forms a second N+ region in each of the second spacer regions on the upper surface of the silicon wafer substrate;
所述沟槽开设于所述第二N+区的边缘区域。The trench is opened in the edge area of the second N+ region.
3.上述方案中，所述第二间隔区域与所述周边区域之间的距离为200～300um。3. In the above solution, the distance between the second separation area and the peripheral area is 200-300um.
4.上述方案中，所述第一二氧化硅薄膜层、所述第二二氧化硅薄膜层以及所述第三二氧化硅薄膜层形成的工艺条件为：1150±0.5℃炉管内，先经过30±5分钟的氧气气氛，再经过480±10分钟的水汽气氛，最后再经过30±5分钟的氧气气氛。4. In the above scheme, the process conditions for forming the first silicon dioxide thin film layer, the second silicon dioxide thin film layer and the third silicon dioxide thin film layer are as follows: 30±5 minutes of oxygen atmosphere, 480±10 minutes of water vapor atmosphere, and finally 30±5 minutes of oxygen atmosphere.
5.上述方案中，所述硅片衬底为N型〈111〉晶向，所述磷杂质掺杂的工艺条件为：首先在1100℃±0.5℃炉管内，时间为2±0.05小时，气氛为三氯氧磷；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为4±0.05小时，气氛为N 2的条件下进行，从而通过磷原子扩散形成所述N+区。 5. In the above scheme, the silicon wafer substrate has an N-type <111> crystal orientation, and the process conditions for the phosphorus impurity doping are: first in a furnace tube at 1100°C±0.5°C for 2±0.05 hours, atmosphere Phosphorus oxychloride; soak in hydrofluoric acid for 30 ± 5 minutes after being out of the furnace, and then in the furnace tube at 1250 ± 0.5 ° C for 4 ± 0.05 hours, and the atmosphere is N 2 to form the The N+ area.
6.上述方案中，所述硅片衬底为N型〈111〉晶向，所述第二次硼杂质掺杂的工艺条件为：首先在第二间隔区域的表面涂覆液态硼源，在1150±0.5℃炉管内，时间为2±0.05小时，气氛为氮气；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为18±0.05小时，气氛为氮气的条件下进行，从而通过硼原子扩散形成所述第二P+区。6. In the above scheme, the silicon wafer substrate has an N-type <111> crystal orientation, and the process conditions for the second doping of boron impurities are: firstly, a liquid boron source is coated on the surface of the second spacer region, and In the furnace tube at 1150±0.5℃, the time is 2±0.05 hours, the atmosphere is nitrogen; after the furnace is soaked in hydrofluoric acid for 30±5 minutes, then, in the furnace tube at 1250±0.5℃, the time is 18±0.05 hours, and the atmosphere is nitrogen. Under conditions, the second P+ region is formed by diffusion of boron atoms.
7.上述方案中，在步骤十一中，所述多晶硅钝化复合薄膜层采用CVD工艺沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷气体和一氧化二氮气体，时间为25±1分钟，其中所述硅烷气体的流速为每分钟130±5ml，所述一氧化二氮气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷气体和一氧化二氮气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层。 7. In the above scheme, in step eleven, the polysilicon passivation composite thin film layer is deposited and formed by a CVD process, and the process conditions are as follows: firstly, pass silane gas and dioxide at a temperature of 650±1℃ Nitrogen gas, the time is 25±1 minutes, wherein the flow rate of the silane gas is 130±5ml per minute, and the flow rate of the nitrous oxide gas is 30±2ml per minute; then, at a temperature of 780±1°C Continue to pass in silane gas and nitrous oxide gas for 15±0.5 minutes, and the flow rates of the two gases are SiH 4 25±5ml per minute and N 2 O 80±5ml per minute; finally a layer containing The polysilicon passivation composite film layer of an oxygen polysilicon passivation film and a silicon dioxide film.
8.上述方案中，在步骤十二中，在所述沟槽中形成所述玻璃钝化层的工艺条件为：在沟槽内填充玻璃胶，厚度为25～35μm，然后通过高温烧结形成致密的所述玻璃钝化层，温度为830±10℃，时间为30±5分钟。8. In the above scheme, in step twelve, the process conditions for forming the glass passivation layer in the trench are: filling the trench with glass paste with a thickness of 25-35 μm, and then sintering at high temperature to form a compact The glass passivation layer has a temperature of 830±10°C and a time of 30±5 minutes.
9.上述方案中，所述硅片衬底为N型〈111〉晶向，所述第一P+区呈十字形，将所述硅片衬底在水平方向隔离成呈田字形布置的四所述间隔块；9. In the above solution, the silicon wafer substrate has an N-type <111> crystal orientation, the first P+ region is a cross shape, and the silicon wafer substrate is horizontally isolated into four places arranged in a square shape. The interval block;
或者，所述硅片衬底为P型〈111〉晶向，所述第一N+区呈十字形，将所述硅片衬底在水平方向隔离成呈田字形布置的四所述间隔块。Alternatively, the silicon wafer substrate has a P-type <111> crystal orientation, and the first N+ region is cross-shaped, and the silicon wafer substrate is horizontally separated into four spacer blocks arranged in a square shape.
为达到上述目的，本发明采用的另一技术方案是：In order to achieve the above objective, another technical solution adopted by the present invention is:
一种四颗二极管集成芯片，包括一硅片衬底，所述硅片衬底中通过第一次第一杂质掺杂形成有第一P+区或第一N+区，该第一P+区或第一N+区在上下方向贯通所述硅片衬底形成隔离墙，在硅片衬底中隔离出四个水平间隔布置的间隔块；A four-diode integrated chip includes a silicon wafer substrate in which a first P+ region or a first N+ region is formed through the first doping of first impurities, and the first P+ region or the An N+ region penetrates the silicon wafer substrate in the up and down direction to form an isolation wall, and four horizontally spaced spacers are isolated from the silicon wafer substrate;
各所述间隔块的上表面通过第二杂质掺杂形成有N+区或P+区，并通过第二次第一杂质掺杂形成有第二P+区或第二N+区，且N+区与第一P+区、第二P+区均间隔设置，或者P+区与第一N+区、第二N+区均间隔设置；The upper surface of each spacer block is formed with an N+ region or a P+ region by second impurity doping, and a second P+ region or a second N+ region is formed by the second first impurity doping, and the N+ region and the first The P+ zone and the second P+ zone are both arranged at intervals, or the P+ zone is arranged at intervals with the first N+ zone and the second N+ zone;
其中，所述第二P+区或所述第二N+区的边缘区域开有沟槽；Wherein, the edge area of the second P+ region or the second N+ region is provided with a trench;
所述硅片衬底上表面于所述N+区或P+区的周边区域、所述第二P+区或所述第二N+区的周边区域以及所述沟槽的表面覆盖有一层多晶硅钝化复合薄膜层；所述沟槽中还填充有玻璃胶，并通过高温烧结形成玻璃钝化层；The upper surface of the silicon wafer substrate is covered with a layer of polysilicon passivation compound on the peripheral area of the N+ zone or the P+ zone, the peripheral area of the second P+ zone or the second N+ zone, and the trench Thin film layer; the groove is also filled with glass glue, and a glass passivation layer is formed by high-temperature sintering;
所述N+区或P+区以及所述第二P+区或所述第二N+区的表面均沉积有金属层，形成金属电极。A metal layer is deposited on the surface of the N+ region or P+ region and the second P+ region or the second N+ region to form a metal electrode.
上述技术方案中的有关内容解释如下：The relevant content in the above technical solution is explained as follows:
1.上述方案中，所述硅片衬底为N型〈111〉晶向，所述N+区将所述第二P+区包围，或者，所述N+区与所述第二P+区水平并列。所述第一P+区呈十字形，将所述硅片衬底在水平方向隔离成呈田字形布置的四所述间隔块。所述N+区与所述第二P+区的距离为200～300um。所述第二P+区的边缘区域开有所述沟槽。1. In the above solution, the silicon wafer substrate has an N-type <111> crystal orientation, and the N+ region surrounds the second P+ region, or the N+ region and the second P+ region are horizontally parallel. The first P+ area is in a cross shape, and the silicon wafer substrate is horizontally separated into four spacer blocks arranged in a square shape. The distance between the N+ zone and the second P+ zone is 200-300um. The groove is opened in the edge area of the second P+ region.
2.上述方案中，所述硅片衬底为P型〈111〉晶向，所述P+区将所述第二N+区包围，或者，所述P+区与所述第二N+区水平并列。所述第一N+区呈十字形，将所述硅片衬底在水平方向隔离成呈田字形布置的四所述间隔块。所述P+区与所述第二N+区的距离为200～300um。所述第二N+区的边缘区域开有所述沟槽。2. In the above solution, the silicon wafer substrate has a P-type <111> crystal orientation, and the P+ region surrounds the second N+ region, or the P+ region and the second N+ region are horizontally parallel. The first N+ area is in a cross shape, and the silicon wafer substrate is horizontally separated into four spacer blocks arranged in a square shape. The distance between the P+ zone and the second N+ zone is 200-300um. The groove is opened in the edge area of the second N+ region.
3.上述方案中，所述沟槽的深度为20～40um。3. In the above solution, the depth of the groove is 20-40um.
4.上述方案中，所述玻璃胶的厚度为25～35μm。4. In the above solution, the thickness of the glass glue is 25-35 μm.
5.上述方案中，所述多晶硅钝化复合薄膜层采用CVD工艺沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷气体和一氧化二氮气体，时间为25±1分钟，其中所述硅烷气体的流速为每分钟130±5ml，所述一氧化二氮气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷气体和一氧化二氮气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层。 5. In the above scheme, the polysilicon passivation composite thin film layer is deposited and formed by a CVD process. The process conditions are as follows: First, pass silane gas and nitrous oxide gas at a temperature of 650±1°C for a time of 25 ±1 minute, wherein the flow rate of the silane gas is 130±5ml per minute, and the flow rate of the nitrous oxide gas is 30±2ml per minute; then, continue to pass the silane gas under the temperature condition of 780±1℃ And nitrous oxide gas, the time is 15±0.5 minutes, and the flow rates of the two gases are 25±5ml per minute for SiH 4 and 80±5ml per minute for N 2 O; finally a layer of oxygen-containing polysilicon passivation film and The polysilicon passivation composite film layer of the silicon dioxide film.
本发明的工作原理及优点如下：The working principle and advantages of the present invention are as follows:
本发明一种四颗二极管集成芯片的制造工艺；步骤包括：一、在硅片衬底上、下表面均形成第一二氧化硅薄膜层；二、刻蚀并去除上、下表面第一二氧化硅薄膜层的隔离带区域；三、对隔离带区域进行第一掺杂形成第一P+区或第一N+区，在上下方向贯通形成隔离墙，在硅片衬底中隔离出四间隔块；四、将第一二氧化硅薄膜层去除，清洗并形成第二二氧化硅薄膜层；五、刻蚀并去除第二二氧化硅薄膜层上的四周边区域；六、对四周边区域进行第二掺杂形成N+区或P+区；七、将第二二氧化硅薄膜层去除，清洗并形成第三二氧化硅薄膜层；八、刻蚀并去除第三二氧化硅薄膜层上的四第二间隔区域；九、对第二间隔区域进行第一掺杂形成第二P+区或第二N+区；十、在第二P+区或第二N+区的边缘区域开沟槽；十一、将第三二氧化硅薄膜层去除，清洗并形成多晶硅钝化复合薄膜层；十二、在沟槽中形成玻璃钝化层；十三、将周边区域及第二间隔区域表面的多晶硅钝化复合薄膜层去除，裸露出N+区或P+区以及第二P+区或第二N+区；十四、在N+区或P+区以及第二P+区或第二N+区的表面沉积金属层形成金属电极。The present invention is a manufacturing process of four diode integrated chips; the steps include: 1. forming a first silicon dioxide film layer on both the upper and lower surfaces of a silicon wafer substrate; 2. etching and removing the upper and lower surfaces The isolation zone area of the silicon oxide film layer; 3. The first doping of the isolation zone area forms the first P+ region or the first N+ region, which penetrates in the up and down direction to form an isolation wall, and isolates four spacers in the silicon wafer substrate 4. Remove the first silicon dioxide film layer, clean and form the second silicon dioxide film layer; 5. Etch and remove the four peripheral areas on the second silicon dioxide film layer; 6. Perform the four peripheral areas The second doping forms the N+ region or the P+ region; 7. Remove the second silicon dioxide film layer, clean and form the third silicon dioxide film layer; 8. Etch and remove the fourth silicon dioxide film layer on the third silicon dioxide film layer The second spacer region; 9. The second spacer region is first doped to form a second P+ region or a second N+ region; 10. A trench is opened in the edge region of the second P+ region or the second N+ region; 11. Remove the third silicon dioxide film layer, clean and form a polysilicon passivation composite film layer; 12. Form a glass passivation layer in the trench; 13. Combine the polysilicon passivation on the surface of the peripheral area and the second spacer area The thin film layer is removed, and the N+ region or P+ region and the second P+ region or the second N+ region are exposed; 14. A metal layer is deposited on the surface of the N+ region or P+ region and the second P+ region or the second N+ region to form a metal electrode.
相比现有技术而言，本发明的优点包括：Compared with the prior art, the advantages of the present invention include:
一、通过选择性扩散形成U形的PN结，增加了PN结的有效面积，显著降低了二极管在电路中应用时的功耗；1. The U-shaped PN junction is formed by selective diffusion, which increases the effective area of the PN junction and significantly reduces the power consumption of the diode when it is used in the circuit;
二、采用化学汽相淀积钝化和玻璃钝化结合的方法，减少侧壁的漏电流，提高了器件的可靠性；2. The combination of chemical vapor deposition passivation and glass passivation is adopted to reduce the leakage current of the side wall and improve the reliability of the device;
三、工艺流程简单，化学品耗用少，正向功耗低，实现了低制造成本高品质的效果；3. The process flow is simple, the chemical consumption is low, the forward power consumption is low, and the effect of low manufacturing cost and high quality is realized;
四、采用20～40um的浅沟槽，加玻璃的二极管PN结钝化设计，通过将四颗二极管都集成在同一硅片衬底中，且各二极管的电极均设计在芯片的同一侧，提高了集成度，器件的体积可大幅减小。4. Using 20~40um shallow trenches, glass-added diode PN junction passivation design, by integrating four diodes in the same silicon substrate, and the electrodes of each diode are designed on the same side of the chip, improving With the integration degree, the volume of the device can be greatly reduced.
另外，本发明一方面不同于常规平面工艺，常规平面工艺一般只能做到600V，如果需要达到800或1000V以上则需要复杂的工艺，即通过多个分压环来实现，需要更大的芯片面积和复杂的工艺过程，加工成本至少需要加倍才能完成；另一方面也不同于100～140um常规的沟槽工艺，常规的沟槽工艺需要3倍以上的化学品腐蚀深的沟槽，采用大面积的玻璃钝化方法增加了杂质沾污的机会，导致漏电流偏高，同时深的沟槽还会导致硅片翘曲增加过程破片率等问题。In addition, the present invention is different from the conventional planar process on the one hand. The conventional planar process can generally only achieve 600V. If it needs to reach 800 or more than 1000V, a complicated process is required, that is, it is realized by multiple voltage divider rings, and a larger chip is required. Area and complex process, the processing cost needs to be at least doubled to complete; on the other hand, it is different from the conventional trench process of 100-140um. The conventional trench process requires more than 3 times the chemical corrosion of the deep trench. The area of the glass passivation method increases the chance of contamination by impurities, resulting in high leakage current. At the same time, deep trenches can also cause problems such as warpage of the silicon wafer and increased process fragmentation rate.
本发明可应用的产品包括普通的整流二极管、快恢复二极管、TVS保护二极管以及稳压管等。The applicable products of the present invention include ordinary rectifier diodes, fast recovery diodes, TVS protection diodes and voltage regulator tubes.
相较传统二极管芯片结构而言，本发明能够做到大幅简化封装，从而能够降低材料费、人工费，有利于降低大批量二极管半导体器件的加工成本，实现最多可降低30％的加 工成本，并能够提升单位时间的生产效率。还能减少客户端的使用能耗，更有利于减少资源的浪费(免去对树脂、焊锡、铜引线等材料的消耗)，对环保作出贡献。Compared with the traditional diode chip structure, the present invention can greatly simplify the packaging, thereby reducing material costs and labor costs, which is beneficial to reduce the processing cost of large-scale diode semiconductor devices, and realizes that the processing cost can be reduced by up to 30%, and Can improve the production efficiency per unit time. It can also reduce the energy consumption of the client, which is more conducive to reducing the waste of resources (eliminating the consumption of resin, solder, copper leads and other materials), and contributes to environmental protection.
附图说明Description of the drawings
附图1为本实用新型实施例第一步的原理示意图；Figure 1 is a schematic diagram of the first step of the embodiment of the utility model;
附图2为本实用新型实施例第二步的俯视示意图；Figure 2 is a schematic top view of the second step of the embodiment of the utility model;
附图3为本实用新型实施例第二步的原理示意图；Figure 3 is a schematic diagram of the principle of the second step of the embodiment of the utility model;
附图4为本实用新型实施例第三步的原理示意图；Figure 4 is a schematic diagram of the principle of the third step of the embodiment of the utility model;
附图5为本实用新型实施例第四步的原理示意图；Figure 5 is a schematic diagram of the principle of the fourth step of the embodiment of the utility model;
附图6为本实用新型实施例第五步的原理示意图；Figure 6 is a schematic diagram of the principle of the fifth step of the embodiment of the utility model;
附图7为本实用新型实施例第六步的原理示意图；Figure 7 is a schematic diagram of the principle of the sixth step of the embodiment of the utility model;
附图8为本实用新型实施例第七步的原理示意图；Fig. 8 is a schematic diagram of the principle of the seventh step of the embodiment of the utility model;
附图9为本实用新型实施例第八步的原理示意图；Figure 9 is a schematic diagram of the principle of the eighth step of the embodiment of the utility model;
附图10为本实用新型实施例第九步的原理示意图；Figure 10 is a schematic diagram of the principle of the ninth step of the embodiment of the utility model;
附图11为本实用新型实施例第十步的原理示意图；Figure 11 is a schematic diagram of the principle of the tenth step of the embodiment of the utility model;
附图12为本实用新型实施例第十一步的原理示意图；Figure 12 is a schematic diagram of the principle of the eleventh step of the embodiment of the utility model;
附图13为本实用新型实施例第十二步的原理示意图；Figure 13 is a schematic diagram of the principle of the twelfth step of the embodiment of the utility model;
附图14为本实用新型实施例第十三步的原理示意图；Figure 14 is a schematic diagram of the principle of the thirteenth step of the embodiment of the utility model;
附图15为本实用新型实施例第十四步的原理示意图；Figure 15 is a schematic diagram of the principle of the fourteenth step of the embodiment of the utility model;
附图16为本实用新型实施例的结构示意图(俯视视角)。Fig. 16 is a schematic structural diagram of an embodiment of the utility model (a top view).
以上附图中：1.硅片衬底；2.第一二氧化硅薄膜层；3.第一间隔区域；4.隔离带区域；5.第一P+区；6.间隔块；7.第二二氧化硅薄膜层；8.第二间隔区域；9.周边区域；10.N+区；11.第三二氧化硅薄膜层；12.第二P+区；13.沟槽；14.多晶硅钝化复合薄膜层；15.玻璃钝化层；16.金属层；d.距离。In the above drawings: 1. silicon wafer substrate; 2. first silicon dioxide film layer; 3. first spacer region; 4. isolation zone region; 5. first P+ region; 6. spacer block; 7. Two silicon dioxide film layer; 8. Second spacer area; 9. Peripheral area; 10. N+ area; 11. Third silicon dioxide film layer; 12. Second P+ area; 13. Trench; 14. Polysilicon passivation Compound film layer; 15. Glass passivation layer; 16. Metal layer; d. Distance.
具体实施方式Detailed ways
下面结合附图及实施例对本发明作进一步描述：The present invention will be further described below in conjunction with the drawings and embodiments:
实施例：参见附图1～16所示，一种四颗二极管集成芯片的制造工艺；选择N型〈111〉晶向或者P型〈111〉晶向的硅片衬底1，本实施例以N型〈111〉晶向为例进行说明，然后按以下步骤进行操作：Embodiment: Refer to Figures 1-16, a manufacturing process of four diode integrated chips; select N-type <111> crystal orientation or P-type <111> crystal orientation silicon wafer substrate 1, this embodiment uses Take the N-type <111> crystal orientation as an example to explain, and then follow the steps below:
如图1所示，第一步，在所述硅片衬底1上表面和下表面均形成一层第一二氧化硅薄膜层2；As shown in FIG. 1, in the first step, a first silicon dioxide film layer 2 is formed on both the upper surface and the lower surface of the silicon wafer substrate 1;
如图2、3所示，第二步，通过光刻胶分别掩膜硅片衬底上表面及下表面的所述第一二氧化硅薄膜层2上的四第一间隔区域3，并以此光刻胶作为掩膜层，分别刻蚀并去除硅片衬底1上表面及下表面裸露的所述第一二氧化硅薄膜层2除去四第一间隔区域3之外的隔离带区 域4；As shown in Figures 2 and 3, in the second step, the four first spacer regions 3 on the first silicon dioxide film layer 2 on the upper and lower surfaces of the silicon wafer substrate are masked by photoresist, and The photoresist is used as a mask layer to etch and remove the exposed first silicon dioxide film layer 2 on the upper and lower surfaces of the silicon wafer substrate 1 respectively, and remove the isolation zone 4 except the first spacer region 3 ；
如图4所示，第三步，第一次第一杂质掺杂，在所述硅片衬底1上表面及下表面对所述隔离带区域4进行第一掺杂，该第一杂质掺杂为硼杂质掺杂(也可为镓杂质掺杂)，掺杂浓度为1～9*10 19atm/cm 3，从而在硅片衬底1上表面及下表面的所述隔离带区域4中均形成第一P+区5，且上表面的所述第一P+区5与下表面的所述第一P+区5连接，构成第一P+区5在上下方向贯通所述硅片衬底1形成隔离墙，在硅片衬底1中隔离出四个水平间隔布置的间隔块6，为后续形成四颗二极管做好前期准备； As shown in FIG. 4, in the third step, the first doping of the first impurity is performed on the upper surface and the lower surface of the silicon wafer substrate 1 to the isolation zone region 4, and the first impurity doping The impurity is doped with boron impurity (it can also be doped with gallium impurity), and the doping concentration is 1-9*10 19 atm/cm 3 , so that the isolation zone 4 on the upper and lower surfaces of the silicon wafer substrate 1 A first P+ region 5 is formed in both of them, and the first P+ region 5 on the upper surface is connected to the first P+ region 5 on the lower surface, forming the first P+ region 5 to penetrate the silicon wafer substrate 1 in the vertical direction An isolation wall is formed, and four horizontally spaced spacer blocks 6 are isolated from the silicon wafer substrate 1 to prepare for the subsequent formation of four diodes;
如图5所示，第四步，将所述第一二氧化硅薄膜层2去除，并对所述硅片衬底1上表面和下表面进行清洗，然后分别形成一层第二二氧化硅薄膜层7；As shown in FIG. 5, in the fourth step, the first silicon dioxide film layer 2 is removed, and the upper and lower surfaces of the silicon wafer substrate 1 are cleaned, and then a layer of second silicon dioxide is formed respectively.膜层7;
如图6所示，第五步，通过光刻胶掩膜硅片衬底1上表面的所述第二二氧化硅薄膜层7上的四第二间隔区域8以及所述隔离带区域4；所述第二间隔区域8与所述第一间隔区域3一一对应，各第二间隔区域8的面积小于各第一间隔区域3且各第二间隔区域8位于各第一间隔区域3的中部；并以所述光刻胶作为掩膜层，刻蚀并去除裸露的所述第二二氧化硅薄膜层7上除去四所述第二间隔区域8之外的且位于四所述第一间隔区域3中的周边区域9；如图7所示，第六步，第二杂质掺杂，在所述硅片衬底1上表面对四所述周边区域9进行第二杂质掺杂，该第二杂质掺杂为磷杂质掺杂(也可为砷杂质掺杂)，从而在所述周边区域9中形成N+区10，该N+区10表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；磷杂质掺杂的工艺条件为：首先在1100℃±0.5℃炉管内，时间为2±0.05小时，气氛为三氯氧磷(POCl 3)；出炉后泡氢氟酸(HF)30±5分钟，接着，在1250±0.5℃炉管内，时间为4±0.05小时，气氛为N 2的条件下进行，从而在所述周边区域9通过磷原子扩散形成所述N+区10。 As shown in FIG. 6, the fifth step is to mask the four second spacer regions 8 and the isolation band region 4 on the second silicon dioxide film layer 7 on the upper surface of the silicon wafer substrate 1 with photoresist; The second interval regions 8 correspond to the first interval regions 3 in a one-to-one manner, the area of each second interval region 8 is smaller than that of each first interval region 3, and each second interval region 8 is located in the middle of each first interval region 3 And using the photoresist as a mask layer to etch and remove the exposed second silicon dioxide film layer 7 except for the fourth second spacer region 8 and located in the fourth first spacer The peripheral region 9 in the region 3; as shown in FIG. 7, in the sixth step, the second impurity doping is performed on the upper surface of the silicon wafer substrate 1. The peripheral region 9 is doped with the second impurity. The two impurity doping is phosphorus impurity doping (or arsenic impurity doping), thereby forming an N+ region 10 in the peripheral region 9. The doping concentration on the surface of the N+ region 10 is at least 10 21 atm/cm 3 , which is diffused The depth is 30-50μm; the process conditions of phosphorus impurity doping are: first in the furnace tube at 1100℃±0.5℃, the time is 2±0.05 hours, the atmosphere is phosphorus oxychloride (POCl 3 ); HF) 30±5 minutes, then, in a furnace tube at 1250±0.5°C for 4±0.05 hours, and the atmosphere is N 2 to form the N+ zone 10 in the peripheral region 9 through the diffusion of phosphorus atoms .
如图8所示，第七步，将所述第二二氧化硅薄膜层7去除，并对所述硅片衬底1上表面和下表面进行清洗，然后分别形成一层第三二氧化硅薄膜层11；As shown in FIG. 8, in the seventh step, the second silicon dioxide film layer 7 is removed, and the upper and lower surfaces of the silicon wafer substrate 1 are cleaned, and then a layer of third silicon dioxide is formed respectively.膜层11;
如图9所示，第八步，通过光刻胶掩膜所述周边区域9以及所述隔离带区域4，并以此光刻胶作为掩膜层，刻蚀并去除裸露的所述第三二氧化硅薄膜层11上的四所述第二间隔区域8，且第二间隔区域8与所述周边区域9间隔设置；As shown in FIG. 9, the eighth step is to mask the peripheral area 9 and the isolation zone area 4 with photoresist, and use the photoresist as a mask layer to etch and remove the exposed third Four of the second spacer regions 8 on the silicon dioxide film layer 11, and the second spacer regions 8 and the peripheral regions 9 are spaced apart;
如图10所示，第九步，第二次硼杂质掺杂(也可为镓杂质掺杂)，在所述硅片衬底1上表面对各所述第二间隔区域8进行硼掺杂，从而在第二间隔区域8中形成第二P+区12，该第二P+区12表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm； As shown in FIG. 10, the ninth step, the second doping with boron impurity (or gallium impurity doping), the upper surface of the silicon wafer substrate 1 is doped with boron on each of the second spacer regions 8 , Thereby forming a second P+ region 12 in the second spacer region 8, the doping concentration of the surface of the second P+ region 12 is at least 10 21 atm/cm 3 , and the diffusion depth is 50-70 μm;
第二次硼杂质掺杂的工艺条件为：首先在与所述第二间隔区域8的表面涂覆液态硼源，在1150±0.5℃炉管内，时间为2±0.05小时，气氛为氮气(N 2)；出炉后泡氢氟酸(HF)30±5分钟，接着，在1250±0.5℃炉管内，时间为18±0.05小时，气氛为氮气(N 2)的条件 下进行，从而在所述第二间隔区域8通过硼原子扩散形成所述第二P+区12。 The process conditions for the second doping of boron impurities are as follows: firstly, a liquid boron source is coated on the surface of the second separation area 8 in a furnace tube of 1150±0.5°C for 2±0.05 hours, and the atmosphere is nitrogen (N 2 ); After the furnace is soaked in hydrofluoric acid (HF) for 30 ± 5 minutes, then, in the 1250 ± 0.5 ℃ furnace tube, the time is 18 ± 0.05 hours, and the atmosphere is nitrogen (N 2 ). The second spacer region 8 forms the second P+ region 12 by diffusion of boron atoms.
如图11所示，第十步，在各所述第二P+区12的边缘区域开沟槽13，从而在所述硅片衬底1上表面暴露PN结，形成二极管器件区，沟槽13的深度为20～40um；As shown in FIG. 11, in the tenth step, trenches 13 are formed in the edge regions of each of the second P+ regions 12, thereby exposing the PN junction on the upper surface of the silicon wafer substrate 1, forming a diode device region, and trenches 13 The depth is 20～40um;
通过沟槽13的开设，一方面可去除所述硅片衬底1表面的损伤层，减少器件的漏电流，另一方面使暴露在硅片表面的PN结向下凹陷，在多晶硅钝化复合薄膜层14的保护下，减小器件表面的漏电流以提升可靠性。Through the opening of the trench 13, on the one hand, the damage layer on the surface of the silicon wafer substrate 1 can be removed and the leakage current of the device can be reduced. Under the protection of the thin film layer 14, the leakage current on the surface of the device is reduced to improve reliability.
如图12所示，第十一步，将所述第三二氧化硅薄膜层11去除，并对所述硅片衬底1上表面以及所述沟槽13进行清洗，然后形成一层多晶硅钝化复合薄膜层14；As shown in FIG. 12, in the eleventh step, the third silicon dioxide film layer 11 is removed, and the upper surface of the silicon wafer substrate 1 and the trench 13 are cleaned, and then a layer of polysilicon passivation is formed.化 compound film layer 14;
所述多晶硅钝化复合薄膜层14采用CVD工艺(化学气相淀积工艺)沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷(SiH 4)气体和一氧化二氮(N 2O)气体，时间为25±1分钟，其中所述硅烷(SiH 4)气体的流速为每分钟130±5ml，所述一氧化二氮(N 2O)气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷(SiH 4)气体和一氧化二氮(N 2O)气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层14。通过上述各项工艺条件，达到符合要求的多晶硅钝化复合薄膜层14的膜厚、成分、晶胞大小、折射率等物理参数。 The polysilicon passivation composite thin film layer 14 is deposited and formed by a CVD process (chemical vapor deposition process), and the process conditions are as follows: firstly, pass silane (SiH 4 ) gas and two oxides at a temperature of 650±1° C. Nitrogen (N 2 O) gas, the time is 25 ± 1 minute, wherein the flow rate of the silane (SiH 4 ) gas is 130 ± 5 ml per minute, and the flow rate of the nitrous oxide (N 2 O) gas is per minute 30±2ml; then, continue to pass silane (SiH 4 ) gas and nitrous oxide (N 2 O) gas under the temperature condition of 780±1℃ for 15±0.5 minutes, and the flow rates of the two gases are respectively SiH 4 is 25±5 ml per minute and N 2 O is 80±5 ml per minute; finally, a layer of polysilicon passivation composite film layer 14 containing oxygen-containing polysilicon passivation film and silicon dioxide film is formed. Through the above process conditions, physical parameters such as the film thickness, composition, unit cell size, and refractive index of the polysilicon passivation composite thin film layer 14 that meet the requirements are achieved.
如图13所示，第十二步，在所述沟槽13中的多晶硅钝化复合薄膜层14表面形成一层玻璃钝化层15；As shown in FIG. 13, in the twelfth step, a glass passivation layer 15 is formed on the surface of the polysilicon passivation composite film layer 14 in the trench 13;
在所述沟槽13中形成所述玻璃钝化层15的工艺条件为：在沟槽13内填充玻璃胶，厚度为25～35μm，然后通过高温烧结形成致密的所述玻璃钝化层15，温度为830±10℃，时间为30±5分钟。The process conditions for forming the glass passivation layer 15 in the trench 13 are: filling the trench 13 with glass paste with a thickness of 25-35 μm, and then forming a dense glass passivation layer 15 through high temperature sintering. The temperature is 830±10℃, and the time is 30±5 minutes.
如图14所示，第十三步，将所述周边区域9以及所述第二间隔区域8表面的多晶硅钝化复合薄膜层14去除，并裸露出所述N+区10以及所述第二P+区12；As shown in FIG. 14, in the thirteenth step, the polysilicon passivation composite film layer 14 on the surface of the peripheral region 9 and the second spacer region 8 is removed, and the N+ region 10 and the second P+ are exposed. District 12;
如图15、16所示，第十四步，在所述N+区10以及所述第二P+区12的表面均沉积金属层16，形成金属电极。As shown in FIGS. 15 and 16, in the fourteenth step, a metal layer 16 is deposited on the surfaces of the N+ region 10 and the second P+ region 12 to form a metal electrode.
其中，所述第二间隔区域8与所述周边区域9之间的距离d为200～300um。之所以选择该距离参数，是因为第二P+区12和N+区10的距离设计必须保证一定的范围，当外加电场时，二极管PN结的空间电荷区会外扩展，第二P+区12和N+区10的距离太近则导致空间电荷区的展宽不够，二极管会提前击穿而达不到设计的电压要求，如果太宽则导致尺寸的增加和材料的浪费。Wherein, the distance d between the second separation area 8 and the peripheral area 9 is 200-300um. The reason for choosing this distance parameter is that the design of the distance between the second P+ region 12 and the N+ region 10 must ensure a certain range. When an electric field is applied, the space charge region of the diode PN junction will expand, and the second P+ region 12 and N+ If the distance of the region 10 is too close, the expansion of the space charge region will be insufficient. The diode will break down in advance and fail to meet the designed voltage requirement. If it is too wide, it will lead to an increase in size and waste of materials.
其中，所述第一二氧化硅薄膜层2、所述第二二氧化硅薄膜层7以及所述第三二氧化硅薄膜层11形成的工艺条件为：1150±0.5℃炉管内，先经过30±5分钟的氧气气氛，再 经过480±10分钟的水汽气氛，最后再经过30±5分钟的氧气气氛。Wherein, the process conditions for forming the first silicon dioxide thin film layer 2, the second silicon dioxide thin film layer 7 and the third silicon dioxide thin film layer 11 are as follows: in the furnace tube of 1150±0.5° C. ±5 minutes of oxygen atmosphere, 480 ± 10 minutes of water vapor atmosphere, and finally 30 ± 5 minutes of oxygen atmosphere.
综上工艺步骤所述，本案于产品层面可按以下方案实施，该方案仅为举例说明之用，不应以此为限：In summary of the above process steps, this case can be implemented at the product level according to the following scheme, which is only for illustrative purposes and should not be limited to this:
如图16所示，一种四颗二极管集成芯片，包括一硅片衬底1，该硅片衬底1为N型〈111〉晶向；所述硅片衬底1中通过第一次硼杂质掺杂形成有第一P+区5，该第一P+区5在上下方向贯通所述硅片衬底1形成隔离墙，在硅片衬底1中隔离出四个水平间隔布置的间隔块6；所述第一P+区5呈十字形，将所述硅片衬底1在水平方向隔离出呈田字形布置的四所述间隔块6。As shown in FIG. 16, a four-diode integrated chip includes a silicon wafer substrate 1, which has an N-type <111> crystal orientation; the silicon wafer substrate 1 passes through the first boron Impurity doping forms a first P+ region 5, which penetrates the silicon wafer substrate 1 in the up and down direction to form an isolation wall, and four horizontally spaced spacers 6 are isolated in the silicon wafer substrate 1. The first P+ region 5 is cross-shaped, and isolates the silicon wafer substrate 1 in the horizontal direction from the four spacer blocks 6 arranged in a square shape.
各所述间隔块6的上表面通过磷杂质掺杂形成有N+区10，并通过第二次硼杂质掺杂形成有第二P+区12，且N+区10与第一P+区5、第二P+区12均间隔设置；所述N+区10将所述第二P+区12包围，或者，所述N+区10与所述第二P+区12水平并列。所述N+区10与所述第二P+区12的距离d为200～300um。The upper surface of each spacer 6 is doped with phosphorus impurities to form an N+ region 10, and through the second boron impurity doping, a second P+ region 12 is formed, and the N+ region 10 is connected to the first P+ region 5 and the second The P+ regions 12 are arranged at intervals; the N+ region 10 surrounds the second P+ region 12, or the N+ region 10 and the second P+ region 12 are horizontally parallel. The distance d between the N+ zone 10 and the second P+ zone 12 is 200-300um.
所述N+区10表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm；所述第二P+区12表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm。 The doping concentration on the surface of the N+ region 10 is at least 10 21 atm/cm 3 , and the diffusion depth is 30-50 μm; the doping concentration on the surface of the second P+ region 12 is at least 10 21 atm/cm 3 , and the diffusion depth is 50- 70μm.
其中，所述第二P+区12的边缘区域开有沟槽13；所述沟槽13的深度为20～40um。Wherein, a trench 13 is opened in the edge area of the second P+ region 12; the depth of the trench 13 is 20-40um.
所述硅片衬底1上表面于所述N+区10的周边区域、所述第二P+区12的周边区域以及所述沟槽13的表面覆盖有一层多晶硅钝化复合薄膜层14；所述沟槽13中还填充有玻璃胶，所述玻璃胶的厚度为25～35μm，并通过高温烧结形成玻璃钝化层15。The upper surface of the silicon wafer substrate 1 is covered with a polysilicon passivation composite film layer 14 on the peripheral area of the N+ region 10, the peripheral area of the second P+ region 12, and the surface of the trench 13; The groove 13 is also filled with glass glue, the thickness of the glass glue is 25-35 μm, and the glass passivation layer 15 is formed by high-temperature sintering.
所述N+区10以及所述第二P+区12的表面均沉积有金属层16，形成金属电极。A metal layer 16 is deposited on the surface of the N+ region 10 and the second P+ region 12 to form a metal electrode.
其中，所述多晶硅钝化复合薄膜层14采用CVD工艺(化学气相淀积工艺)沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷气体和一氧化二氮气体，时间为25±1分钟，其中所述硅烷气体的流速为每分钟130±5ml，所述一氧化二氮气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷气体和一氧化二氮气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层14。 Wherein, the polysilicon passivation composite thin film layer 14 is deposited and formed by a CVD process (chemical vapor deposition process), and the process conditions are as follows: first, pass silane gas and nitrous oxide gas at a temperature of 650±1°C , The time is 25±1 minutes, wherein the flow rate of the silane gas is 130±5ml per minute, and the flow rate of the nitrous oxide gas is 30±2ml per minute; then, continue under the temperature condition of 780±1℃ Inject silane gas and nitrous oxide gas for 15±0.5 minutes, and the flow rates of the two gases are 25±5ml per minute for SiH 4 and 80±5ml per minute for N 2 O; finally a layer of oxygen-containing polysilicon is formed The polysilicon passivation composite film layer 14 of passivation film and silicon dioxide film.
其中，在后期封装过程中，可通过将不同二极管颗粒(间隔块6)上的所述N+区10及所述第二P+区12对应的金属电极通过引脚连接，使之成为全桥整流的产品，或者成为一个半桥和两个二极管的产品。Among them, in the later packaging process, the metal electrodes corresponding to the N+ region 10 and the second P+ region 12 on different diode particles (spacer block 6) can be connected through pins to make them full-bridge rectified Product, or a product with a half bridge and two diodes.
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。The above-mentioned embodiments are only to illustrate the technical concept and characteristics of the present invention, and their purpose is to enable those familiar with the technology to understand the content of the present invention and implement them accordingly, and cannot limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.

Claims (10)

  1. 一种四颗二极管集成芯片的制造工艺；其特征在于：选择硅片衬底，然后按以下步骤进行操作：A manufacturing process of four diode integrated chips; it is characterized in that: a silicon wafer substrate is selected, and then the following steps are performed:
    第一步，在所述硅片衬底上表面和下表面均形成一层第一二氧化硅薄膜层；In the first step, a first silicon dioxide film layer is formed on both the upper surface and the lower surface of the silicon wafer substrate;
    第二步，通过光刻胶分别掩膜硅片衬底上表面及下表面的所述第一二氧化硅薄膜层上的四第一间隔区域，并以此光刻胶作为掩膜层，分别刻蚀并去除硅片衬底上表面及下表面裸露的所述第一二氧化硅薄膜层除去四第一间隔区域之外的隔离带区域；In the second step, the four first spacer regions on the first silicon dioxide film layer on the upper surface and the lower surface of the silicon wafer substrate are respectively masked by photoresist, and the photoresist is used as a mask layer, respectively Etching and removing the exposed first silicon dioxide film layer on the upper surface and the lower surface of the silicon wafer substrate to remove the isolation zone area except the first spacer area;
    第三步，第一次第一杂质掺杂，在所述硅片衬底上表面及下表面对所述隔离带区域进行第一掺杂，从而在硅片衬底上表面及下表面的所述隔离带区域中均形成第一P+区或第一N+区；上表面的所述第一P+区与下表面的所述第一P+区连接，构成第一P+区在上下方向贯通所述硅片衬底形成隔离墙，或者，上表面的所述第一N+区与下表面的所述第一N+区连接，构成第一N+区在上下方向贯通所述硅片衬底形成隔离墙；通过所述隔离墙在硅片衬底中隔离出四个水平间隔布置的间隔块，为后续形成四颗二极管做好前期准备；In the third step, the first doping of the first impurity is performed on the upper surface and the lower surface of the silicon wafer substrate to the isolation zone area, so that all the upper and lower surfaces of the silicon wafer substrate are doped. A first P+ region or a first N+ region is formed in the isolation zone area; the first P+ region on the upper surface is connected to the first P+ region on the lower surface to form the first P+ region through the silicon in the up and down direction The wafer substrate forms an isolation wall, or the first N+ region on the upper surface is connected to the first N+ region on the lower surface to form a first N+ region that penetrates the silicon wafer substrate in the up and down direction to form an isolation wall; The isolation wall isolates four horizontally spaced spacer blocks in the silicon wafer substrate to prepare for the subsequent formation of four diodes;
    第四步，将所述第一二氧化硅薄膜层去除，并对所述硅片衬底上表面和下表面进行清洗，然后分别形成一层第二二氧化硅薄膜层；In the fourth step, the first silicon dioxide film layer is removed, the upper surface and the lower surface of the silicon wafer substrate are cleaned, and then a second silicon dioxide film layer is formed respectively;
    第五步，通过光刻胶掩膜硅片衬底上表面的所述第二二氧化硅薄膜层上的四第二间隔区域以及所述隔离带区域；所述第二间隔区域与所述第一间隔区域一一对应，各第二间隔区域的面积小于各第一间隔区域；并以所述光刻胶作为掩膜层，刻蚀并去除裸露的所述第二二氧化硅薄膜层上除去四所述第二间隔区域之外的且位于四所述第一间隔区域中的周边区域；The fifth step is to mask the four second spacer regions and the isolation band region on the second silicon dioxide film layer on the upper surface of the silicon wafer substrate by photoresist; the second spacer region and the first spacer region One interval area corresponds to one another, and the area of each second interval area is smaller than that of each first interval area; and the photoresist is used as a mask layer to etch and remove the exposed second silicon dioxide film layer. 4. Peripheral areas outside the second interval area and located in the fourth first interval area;
    第六步，第二杂质掺杂，在所述硅片衬底上表面对四所述周边区域进行第二杂质掺杂，从而在所述周边区域中形成N+区或P+区，该N+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm，P+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm； In the sixth step, the second impurity doping is performed on the upper surface of the silicon wafer substrate to perform the second impurity doping on the peripheral region, thereby forming an N+ region or P+ region in the peripheral region. The surface of the N+ region The doping concentration of the P+ region is at least 10 21 atm/cm 3 , the diffusion depth is 30-50 μm, the doping concentration on the surface of the P+ region is at least 10 21 atm/cm 3 , and the diffusion depth is 50-70 μm;
    第七步，将所述第二二氧化硅薄膜层去除，并对所述硅片衬底上表面和下表面进行清洗，然后分别形成一层第三二氧化硅薄膜层；In the seventh step, the second silicon dioxide film layer is removed, and the upper and lower surfaces of the silicon wafer substrate are cleaned, and then a third silicon dioxide film layer is formed respectively;
    第八步，通过光刻胶掩膜所述周边区域以及所述隔离带区域，并以此光刻胶作为掩膜层，刻蚀并去除裸露的所述第三二氧化硅薄膜层上的四所述第二间隔区域，且第二间隔区域与所述周边区域间隔设置；The eighth step is to mask the peripheral area and the isolation zone area with photoresist, and use the photoresist as a mask layer to etch and remove the exposed third silicon dioxide film layer. The second spacing area, and the second spacing area is spaced apart from the peripheral area;
    第九步，第二次第一杂质掺杂，在所述硅片衬底上表面对各所述第二间隔区域进行第一掺杂，从而在第二间隔区域中形成第二P+区或第二N+区，该第二P+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为50～70μm，第二N+区表面的掺杂浓度至少10 21atm/cm 3，扩散深度为30～50μm； The ninth step is the second doping of the first impurity, and the first doping is performed on each of the second spacer regions on the upper surface of the silicon wafer substrate, thereby forming a second P+ region or a second spacer region in the second spacer region. Two N+ regions, the doping concentration on the surface of the second P+ region is at least 10 21 atm/cm 3 , the diffusion depth is 50-70 μm, the doping concentration on the surface of the second N+ region is at least 10 21 atm/cm 3 , and the diffusion depth is 30 ～50μm;
    第十步，在各所述第二P+区或所述第二N+区的边缘区域开沟槽，沟槽的深度为20～40um；The tenth step is to open a trench in the edge area of each of the second P+ region or the second N+ region, and the depth of the trench is 20-40um;
    第十一步，将所述第三二氧化硅薄膜层去除，并对所述硅片衬底上表面以及所述沟槽进行清洗，然后形成一层多晶硅钝化复合薄膜层；In the eleventh step, the third silicon dioxide film layer is removed, and the upper surface of the silicon wafer substrate and the groove are cleaned, and then a polysilicon passivation composite film layer is formed;
    第十二步，在所述沟槽中的多晶硅钝化复合薄膜层表面形成一层玻璃钝化层；The twelfth step, forming a glass passivation layer on the surface of the polysilicon passivation composite film layer in the trench;
    第十三步，将所述周边区域以及所述第二间隔区域表面的多晶硅钝化复合薄膜层去除，并裸露出所述N+区或所述P+区，以及所述第二P+区或所述第二N+区；In the thirteenth step, the polysilicon passivation composite film layer on the surface of the peripheral region and the second spacer region is removed, and the N+ region or the P+ region, and the second P+ region or the The second N+ zone;
    第十四步，在所述N+区或所述P+区以及所述第二P+区或所述第二N+区的表面均沉积金属层，形成金属电极。In the fourteenth step, a metal layer is deposited on the surfaces of the N+ region or the P+ region and the second P+ region or the second N+ region to form a metal electrode.
  2. 根据权利要求1所述的工艺，其特征在于：所述硅片衬底为N型〈111〉晶向，所述第一杂质掺杂为硼杂质掺杂或镓杂质掺杂，所述第二杂质掺杂为磷杂质掺杂或砷杂质掺杂；The process according to claim 1, wherein the silicon wafer substrate has an N-type <111> crystal orientation, the first impurity doping is doped with boron impurity or gallium impurity, and the second Impurity doping is phosphorus impurity doping or arsenic impurity doping;
    所述第一次第一杂质掺杂在硅片衬底上表面及下表面的所述隔离带区域中均形成第一P+区；所述第二杂质掺杂在所述硅片衬底上表面的四所述周边区域中形成N+区；所述第二次第一杂质掺杂在所述硅片衬底上表面的各所述第二间隔区域中形成第二P+区；The first doping of the first impurity on the upper surface and the lower surface of the silicon wafer substrate forms a first P+ region in the isolation zone regions; the second impurity doping on the upper surface of the silicon wafer substrate N+ regions are formed in the peripheral regions of four; the second first impurity doping forms second P+ regions in each of the second spacer regions on the upper surface of the silicon wafer substrate;
    所述沟槽开设于所述第二P+区的边缘区域。The trench is opened in the edge area of the second P+ region.
  3. 根据权利要求1所述的工艺，其特征在于：所述硅片衬底为P型〈111〉晶向，所述第一杂质掺杂为磷杂质掺杂或砷杂质掺杂，所述第二杂质掺杂为硼杂质掺杂或镓杂质掺杂；所述第一次第一杂质掺杂在硅片衬底上表面及下表面的所述隔离带区域中均形成第一N+区；所述第二杂质掺杂在所述硅片衬底上表面的四所述周边区域中形成P+区；所述第二次第一杂质掺杂在所述硅片衬底上表面的各所述第二间隔区域中形成第二N+区；The process according to claim 1, wherein the silicon wafer substrate has a P-type <111> crystal orientation, the first impurity doping is phosphorus impurity doping or arsenic impurity doping, and the second The impurity doping is boron impurity doping or gallium impurity doping; the first first impurity doping forms a first N+ region in both the isolation zone regions on the upper surface and the lower surface of the silicon wafer substrate; The second impurity doping forms the P+ region in the four peripheral regions on the upper surface of the silicon wafer substrate; the second first impurity doping on the upper surface of the silicon wafer substrate forms a P+ region; Forming a second N+ zone in the spacer region;
    所述沟槽开设于所述第二N+区的边缘区域。The trench is opened in the edge area of the second N+ region.
  4. 根据权利要求1所述的工艺，其特征在于：所述第一二氧化硅薄膜层、所述第二二氧化硅薄膜层以及所述第三二氧化硅薄膜层形成的工艺条件为：1150±0.5℃炉管内，先经过30±5分钟的氧气气氛，再经过480±10分钟的水汽气氛，最后再经过30±5分钟的氧气气氛。The process according to claim 1, wherein the process conditions for forming the first silicon dioxide thin film layer, the second silicon dioxide thin film layer and the third silicon dioxide thin film layer are: 1150± In the 0.5℃ furnace tube, first pass through an oxygen atmosphere for 30±5 minutes, then pass through a water vapor atmosphere for 480±10 minutes, and finally pass an oxygen atmosphere for 30±5 minutes.
  5. 根据权利要求2所述的工艺，其特征在于：所述磷杂质掺杂的工艺条件为：首先在1100℃±0.5℃炉管内，时间为2±0.05小时，气氛为三氯氧磷；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为4±0.05小时，气氛为N 2的条件下进行，从而通过磷原子扩散形成所述N+区。 The process according to claim 2, characterized in that: the process conditions of the phosphorus impurity doping are: firstly in a furnace tube at 1100°C ± 0.5°C for 2 ± 0.05 hours, and the atmosphere is phosphorus oxychloride; Soak in hydrofluoric acid for 30±5 minutes, and then, in a furnace tube at 1250±0.5°C for 4±0.05 hours, and the atmosphere is N 2 to form the N+ zone through the diffusion of phosphorus atoms.
  6. 根据权利要求2所述的工艺，其特征在于：所述第二次硼杂质掺杂的工艺条件为：首先在第二间隔区域的表面涂覆液态硼源，在1150±0.5℃炉管内，时间为2±0.05小时，气氛为氮气；出炉后泡氢氟酸30±5分钟，接着，在1250±0.5℃炉管内，时间为18±0.05小时，气氛为氮气的条件下进行，从而通过硼原子扩散形成所述第二P+区。The process according to claim 2, characterized in that: the process conditions for the second doping with boron impurities are: firstly coating a liquid boron source on the surface of the second interval area, in the furnace tube at 1150±0.5°C for a time 2±0.05 hours, the atmosphere is nitrogen; after the furnace is soaked in hydrofluoric acid for 30±5 minutes, then, in the 1250±0.5℃ furnace tube, the time is 18±0.05 hours, and the atmosphere is nitrogen, so as to pass the boron atom Diffusion forms the second P+ region.
  7. 根据权利要求1所述的工艺，其特征在于：在步骤十一中，所述多晶硅钝化复合薄膜 层采用CVD工艺沉积形成，其工艺条件为：首先，在650±1℃的温度条件下通入硅烷气体和一氧化二氮气体，时间为25±1分钟，其中所述硅烷气体的流速为每分钟130±5ml，所述一氧化二氮气体的流速为每分钟30±2ml；然后，在780±1℃的温度条件下继续通入硅烷气体和一氧化二氮气体，时间为15±0.5分钟，且两种气体的流速分别为SiH 4每分钟25±5ml和N 2O每分钟80±5ml；最终形成一层含氧多晶硅钝化膜和二氧化硅薄膜的所述多晶硅钝化复合薄膜层。 The process according to claim 1, characterized in that: in step eleven, the polysilicon passivation composite film layer is deposited and formed by a CVD process, and the process conditions are as follows: first, pass under a temperature condition of 650±1°C Into the silane gas and nitrous oxide gas, the time is 25±1 minutes, the flow rate of the silane gas is 130±5ml per minute, and the flow rate of the nitrous oxide gas is 30±2ml per minute; Under the temperature condition of 780±1℃, continue to pass silane gas and nitrous oxide gas for 15±0.5 minutes, and the flow rates of the two gases are SiH 4 25±5ml per minute and N 2 O per minute 80± 5ml; finally a layer of the polysilicon passivation composite film layer containing oxygen-containing polysilicon passivation film and silicon dioxide film is formed.
  8. 根据权利要求1所述的工艺，其特征在于：在步骤十二中，在所述沟槽中形成所述玻璃钝化层的工艺条件为：在沟槽内填充玻璃胶，厚度为25～35μm，然后通过高温烧结形成致密的所述玻璃钝化层，温度为830±10℃，时间为30±5分钟。The process according to claim 1, characterized in that: in step 12, the process conditions for forming the glass passivation layer in the trench are: filling the trench with glass paste with a thickness of 25-35 μm , And then form a dense passivation layer of the glass through high-temperature sintering at a temperature of 830±10°C and a time of 30±5 minutes.
  9. 一种四颗二极管集成芯片，其特征在于：包括一硅片衬底，所述硅片衬底中通过第一次第一杂质掺杂形成有第一P+区或第一N+区，该第一P+区或第一N+区在上下方向贯通所述硅片衬底形成隔离墙，在硅片衬底中隔离出四个水平间隔布置的间隔块；A four-diode integrated chip, characterized in that it comprises a silicon wafer substrate in which a first P+ region or a first N+ region is formed through the first doping of the first impurity, the first The P+ region or the first N+ region penetrates the silicon wafer substrate in the up and down direction to form an isolation wall, and four horizontally spaced spacers are isolated in the silicon wafer substrate;
    各所述间隔块的上表面通过第二杂质掺杂形成有N+区或P+区，并通过第二次第一杂质掺杂形成有第二P+区或第二N+区，且N+区与第一P+区、第二P+区均间隔设置，或者P+区与第一N+区、第二N+区均间隔设置；The upper surface of each spacer block is formed with an N+ region or a P+ region by second impurity doping, and a second P+ region or a second N+ region is formed by the second first impurity doping, and the N+ region and the first The P+ zone and the second P+ zone are both arranged at intervals, or the P+ zone is arranged at intervals with the first N+ zone and the second N+ zone;
    其中，所述第二P+区或所述第二N+区的边缘区域开有沟槽；Wherein, the edge area of the second P+ region or the second N+ region is provided with a trench;
    所述硅片衬底上表面于所述N+区或P+区的周边区域、所述第二P+区或所述第二N+区的周边区域以及所述沟槽的表面覆盖有一层多晶硅钝化复合薄膜层；所述沟槽中还填充有玻璃胶，并通过高温烧结形成玻璃钝化层；The upper surface of the silicon wafer substrate is covered with a layer of polysilicon passivation compound on the peripheral area of the N+ zone or the P+ zone, the peripheral area of the second P+ zone or the second N+ zone, and the trench Thin film layer; the groove is also filled with glass glue, and a glass passivation layer is formed by high-temperature sintering;
    所述N+区或P+区以及所述第二P+区或所述第二N+区的表面均沉积有金属层，形成金属电极。A metal layer is deposited on the surface of the N+ region or P+ region and the second P+ region or the second N+ region to form a metal electrode.
  10. 根据权利要求8所述的芯片，其特征在于：所述第一P+区或所述第一N+区呈十字形，将所述硅片衬底在水平方向隔离成呈田字形布置的四所述间隔块。8. The chip according to claim 8, wherein the first P+ region or the first N+ region is cross-shaped, and the silicon wafer substrate is horizontally separated into four squares arranged in a cross shape. Spacer block.
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CN104538417A (en) * 2015-01-08 2015-04-22 电子科技大学 LED open circuit protection integrated chip based on diode chain and manufacturing method thereof
CN109427763A (en) * 2017-08-22 2019-03-05 奇景光电股份有限公司 Electrostatic discharge protective circuit
CN109599332A (en) * 2018-12-27 2019-04-09 朝阳无线电元件有限责任公司 A kind of low volt voltage adjustment diode manufacturing method
CN110060934A (en) * 2019-04-30 2019-07-26 苏州固锝电子股份有限公司 A kind of manufacturing process of four diode integrated chips

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