CN104362182B - A kind of plane binode type Zener diode chip and its production technology - Google Patents
A kind of plane binode type Zener diode chip and its production technology Download PDFInfo
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- CN104362182B CN104362182B CN201410665403.8A CN201410665403A CN104362182B CN 104362182 B CN104362182 B CN 104362182B CN 201410665403 A CN201410665403 A CN 201410665403A CN 104362182 B CN104362182 B CN 104362182B
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- 238000009792 diffusion process Methods 0.000 claims abstract description 145
- 229910052751 metal Inorganic materials 0.000 claims abstract description 43
- 239000002184 metal Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000002161 passivation Methods 0.000 claims abstract description 26
- 238000002513 implantation Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 176
- 239000010703 silicon Substances 0.000 claims description 176
- 229910052710 silicon Inorganic materials 0.000 claims description 176
- 239000000243 solution Substances 0.000 claims description 75
- 229910052796 boron Inorganic materials 0.000 claims description 44
- -1 boron ion Chemical class 0.000 claims description 43
- 238000001259 photo etching Methods 0.000 claims description 30
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- 238000005530 etching Methods 0.000 claims description 18
- 238000001465 metallisation Methods 0.000 claims description 18
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- 239000008367 deionised water Substances 0.000 claims description 12
- 229910021641 deionized water Inorganic materials 0.000 claims description 12
- 238000001035 drying Methods 0.000 claims description 12
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- 238000007654 immersion Methods 0.000 claims description 11
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- 238000005520 cutting process Methods 0.000 claims description 6
- 239000000428 dust Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 230000000717 retained effect Effects 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
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- 230000015556 catabolic process Effects 0.000 abstract description 30
- 239000000463 material Substances 0.000 abstract description 16
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- 238000004140 cleaning Methods 0.000 description 8
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- 230000005684 electric field Effects 0.000 description 5
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- 239000010931 gold Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66128—Planar diodes
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- H01L29/6609—Diodes
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/861—Diodes
- H01L29/866—Zener diodes
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Abstract
The invention discloses a kind of plane binode type Zener diode chip and its production technology, belong to electronic device manufacture field.A kind of plane binode type Zener diode chip, including chip, front metal layer and metal layer on back, chip include substrate layer, epitaxial layer, deep layer doped diffusion region, surface doping diffusion region and passivation layer, and described chip is Zener diode chip;Chip cuts layer and is followed successively by substrate layer, epitaxial layer, deep layer doped diffusion region, surface doping diffusion region and passivation layer from bottom to top.Chip production process can effectively improve the breakdown voltage precision of device using ion implanting and thermal diffusion process twice, reduce because of the device performance difference caused by substrate and epitaxial material performance difference;By adjustment, implantation dosage or diffusion conditionses can be with directly modulation device electric breakdown strengths twice, so as in the case of using single epitaxial material, the making of achievable multi-voltage grade voltage-stabilizing device improve production efficiency, reduce production cost, have stable dynamic electric resistor performance.
Description
Technical field
The present invention relates to electronic device manufacture field, more particularly, it relates to a kind of plane binode type Zener diode core
Piece and its production technology.
Background technology
The substitute products of vacuum tube, voltage stabilizing (Zener) diode were widely used as voltage reference points from the fifties
In all kinds of voltage modulated circuits, the breakdown voltage rank of device is in requisition for from several volts to upper hectovolt.Zener diode it is important
Characteristic is that electric current is blocked under backward voltage, until reversely pressure reaches the threshold values or breakdown voltage of device, when Zener
When load, it is puncturing for this pipe that the zener diode of reverse biased can clamp down on the voltage at load two ends to diodes in parallel
Voltage.Zener diode is often used as voltage reference points or transient voltage suppressor.But it is when being used as voltage reference points, high
The breakdown voltage of precision is very important parameter request for some circuit designs.Generally, Zener diode product can all refer to
Determine the positive and negative percentage ratio of breakdown voltage error, high-precision product can set breakdown voltage error as less than ± 1%, ± 2% or
± 5%.
Existing publication:Zener diode, patent application publication No.:CN85101319, patent application date of publication:1987
It is the substrate Silicon Wafer using all kinds of resistivity to disclose within 10 days 01 month voltage stabilizing Zener diode general at present year, or raw
The epitaxial wafer being longer than on highly doped substrate, and by single adulterate (mode such as solid/gas state source, paper source, and ion implanting) and
Diffusion process preparing, but due to the immanent cause of material fabrication process, common substrate wafer or epitaxial wafer, batch and
Between batch, with batch difference wafer between, or even same wafer zones of different all exist doping or resistivity difference.This
The amplitude of difference can change within the specific limits according to different material preparation methods, even up to higher level.By single
The breakdown voltage of the voltage stabilizing Zener diode prepared by doping and method of diffusion is largely dependent upon the resistance of base material
Rate and device fabrication process also bring along the error of breakdown voltage in itself.Resistivity of material error and device prepare introduced
Device after error superposition can cause to make has larger voltage dispersion (even greater than ± 10% more than ± 5%), affects
To the voltage accuracy and reduction yield rate of device.In addition, using single adulterate and diffusion technique voltage stabilizing Zener diode, for
Different electric pressures, needs the wafer using different resistivity.For certain voltage scope series of products are included, buying is needed
The wafer of multiple resistivity classifications, correspondingly improves production cost.
For plane voltage stabilizing zener diode, problem that another traditional single doping and diffusion technique are brought is, P/N
The physical edge of knot puncture that difference influences whether device puncture behavior.The avalanche breakdown of P/N knots and the electric field point at knot edge
Cloth is closely connected, and the Electric Field Distribution difference for tying adjacent edges can affect prebreakdown and the small electric of device to a great extent
What is flowed down punctures behavior, so, the main junction breakdown tied by P/N and edge breakdown separate or isolation can be such that device itself has surely
Fixed and unified punctures behavior.
The content of the invention
1. technical problem to be solved
For because of the higher device electric breakdown strength error caused by epitaxial material difference, tying edge present in prior art
The instable problem of dynamic electric resistor caused by the prebreakdown of electric field, the invention provides a kind of two pole of plane binode type voltage stabilizing
Die and its production technology.It has the high precision of voltage regulation, the low, compact conformation of electric leakage, has the excellent of good age stability performance
Point, it is possible to achieve the making of multi-voltage grade voltage-stabilizing device, production efficiency is high, low cost.
2. technical scheme
The purpose of the present invention is achieved through the following technical solutions.
A kind of plane binode type Zener diode chip, including chip, front metal layer and metal layer on back, described core
Piece includes substrate layer, epitaxial layer, deep layer doped diffusion region, surface doping diffusion region and passivation layer, and described chip is voltage stabilizing two
Pole pipe chip;Chip cut layer be followed successively by from bottom to top substrate layer, epitaxial layer, deep layer doped diffusion region, surface doping diffusion region and
Passivation layer.
Further, described substrate layer is N+ type substrate layers, and described epitaxial layer is N-type epitaxial layer, corresponding depth
Layer doped diffusion region and surface doping diffusion region are respectively N+ moldeed depth layers doped diffusion region, P+ type surface doping diffusion region.
Further, described substrate layer is P+ type substrate layer, and described epitaxial layer is P-type epitaxial layer, corresponding depth
Layer doped diffusion region and surface doping diffusion region are respectively P+ deep layers doped diffusion region, N+ type surface dopings diffusion region.
Further, described epitaxy layer thickness be 5 μm -30 μm, electrical resistivity of epitaxy in 0.50ohm.cm extremely
10.0ohm.cm。
Further, described passivation layer is silicon dioxide passivation layer.
A kind of plane binode type Zener diode chip production process, its step are as follows:
1) clean:Lot number establishment, mark number are carried out to silicon chip, rear deionized water is rinsed silicon chip surface or existed with machine
Silicon chip surface swabbing, removes the dust fallen in silicon chip surface during mark, then silicon chip is put in baking oven and is dried;
2) initial fields oxidation:Silicon chip after drying is sent in 900~1100 DEG C of oxidation furnace, layer of oxide layer is grown;
3) first time photoetching:Silicon chip after step 2 is aoxidized leaves photoetching through gluing, exposure, development, etching procedure
Figure, and silicon chip is immersed in 10 minutes in SPM solution, photoresist is removed;
4) deep layer doping:Silicon chip surface is injected into phosphorus or boron ion, is doped;
5) deep layer diffusion:Silicon chip after doping is put in diffusion furnace carries out phosphorus or boron diffusion propulsion, phosphorus or boron select with
Step 4 intermediate ion is identical, forms deep layer doped diffusion region, carries out deep layer doping and diffusion formation N+ moldeed depth layers using phosphonium ion and mixes
Miscellaneous diffusion region, carries out deep layer doping and diffusion using boron ion and forms P+ type deep layer doped diffusion region;
6) second photoetching:By the silicon chip obtained in step 5 through operations such as gluing, exposure, development, deoxidations, stay
Litho pattern, and silicon chip is immersed in 10 minutes in SPM solution, photoresist is removed;
7) surface doping:Silicon chip surface is injected into boron or phosphonium ion, is doped, phosphorus or boron select with step 4 from
It is sub different, phosphonium ion injection used in step 4, then this step from boron ion injection, used in step 4, inject, then by boron ion
This step is injected from phosphonium ion;
8) diffusion into the surface:Silicon chip after step 7 is adulterated carries out boron or phosphorus diffusion propulsion, phosphorus or boron choosing in being put into diffusion furnace
Select identical with step 7 intermediate ion, surface doping is carried out using boron ion and diffuse to form P+ type surface doping diffusion region, phosphonium ion
Carry out deep layer doping and diffusion and form N+ moldeed depth layers doped diffusion region;
9) second oxidation:The silicon chip that step 8 is obtained sends into 900~1100 DEG C of oxidation furnace, grows one layer of oxidation
Layer;
10) third time photoetching:Contact hole photoetching, the silicon chip after step 9 is aoxidized is through gluing, exposure, development, etching work
Sequence, leaves litho pattern, and figure is passivation layer shape, after silicon chip is immersed in 10 minutes in SPM solution, photoresist is removed;
11) clean:With machine by silicon chip immerse B-clean solution in, the B-clean solution successively comprising SPM solution,
DHF solution, SC1 solution, SC2 solution, the above-mentioned debris that all deionized water is rinsed on silicon chip after each step solution, enter
Under row, silicon chip is finally put into oven for drying by a kind of solution;
12) front-side metallization:The silicon chip that step 11 is obtained carries out surface evaporation, one layer of titanium of surface evaporation,
Then evaporate one layer of aluminum metal, form front metal layer;
13) four mask:Metal lithographic, by the silicon chip after metallization through gluing, exposure, development, etching procedure, stays
Lower litho pattern, figure are front metal layer shape, and silicon chip is immersed in 10 minutes in SPM solution, and photoresist is removed;
14) thinning back side:The silicon chip that step 13 is obtained carries out back and polishes off, and piece thickness is retained in 200~230um;
15) clean:In the silicon chip immersion ethanol that step 14 is obtained and the mixed solution of fluohydric acid gas, then silicon chip is carried out
Redistilled water is cleaned, and is dried silicon chip using chip drier;
16) back face metalization:The silicon chip that step 15 is obtained carries out back side evaporation, and one layer of titanium is evaporated at the back side,
Then evaporate one layer of nickel metal, one layer of silver metal of final evaporation;Form metal layer on back;
17) chip cutting:The silicon chip that step 16 is obtained is divided into into one single chip with scribing machine.
Further, in step 4 and 7, ion implantation energy is 40KeV~80KeV.
Further, in step 4 and 7, ion implantation dosage is 1.0E12cm-2~2.2E16cm-2, the injection of step 7
Implantation dosage of the dosage more than or equal to step 4.
Further, in step 5 and 8, diffusion furnace temperature when phosphorus and boron spread is 1100~1250 DEG C.
3. beneficial effect
Compared to prior art, it is an advantage of the current invention that:
(1) present invention utilizes secondary injection and diffusion technique so that the breakdown voltage of device is by injecting twice and spread institute
The P/N knots of formation are determined, and can effectively improve the breakdown voltage essence of device without direct correlation with the performance of epitaxial material
Degree, reduces because of the device performance difference caused by substrate and epitaxial material performance difference;
(2) because the breakdown voltage of device prepared by the present invention is determined by the dosage and diffusion conditionses that inject twice, do not changing
In the case of becoming epitaxial nature, can pass through to adjust the mesh of implantation dosage twice or diffusion conditionses to reach modulation breakdown voltage
, so that the present invention in the case of using single epitaxial material, can realize the making of multi-voltage grade voltage-stabilizing device, carry
High production efficiency, such as 6.2V to 40V devices can use the epitaxial wafer of same resistivity, and reduce cost;
(3) there are two P/N tie regions in device prepared by the present invention:1) in zone line and material internal, by twice
The formed deep layer P/N knot of injection and diffusion;2) in outer peripheral areas and material surface, by inject for the second time and spread with extension material
The P/N knots that material is formed.Sheet of the deep layer P/N knot intrinsic breakdown voltage in zone line and material internal region much smaller than outer peripheral areas
Junction breakdown voltage is levied, when device works, under small voltage, zone line P/N knot avalanche breakdowns, while outer peripheral areas P/N knot
In the reverse biased area much smaller than its breakdown voltage, minimum reverse leakage is provided only, the breakdown voltage of device is by mesozone
The uniform Electric Field Distribution in domain determines, it is to avoid the prebreakdown phenomenon of unijunction device junction fringe field, so as to provide surely for device
Fixed dynamic electric resistor performance.
Description of the drawings
Fig. 1 is the schematic cross-section of the chip of the present invention;
Fig. 2 is the schematic cross-section of traditional unijunction type voltage stabilizing Zener diode.
Label declaration in figure:
1st, substrate layer;2nd, epitaxial layer;3rd, deep layer doped diffusion region;4th, surface doping diffusion region;5th, passivation layer;6th, front gold
Category layer;7th, metal layer on back.
Specific embodiment
With reference to Figure of description and specific embodiment, the present invention is described in detail.
Embodiment 1
As shown in figure 1, a kind of plane binode type Zener diode chip, including chip, front metal layer 6 and back metal
Layer 7, chip includes substrate layer 1, epitaxial layer 2, deep layer doped diffusion region 3, surface doping diffusion region 4 and passivation layer 5, and chip is steady
Pressure diode chip for backlight unit;Chip cuts layer and is followed successively by substrate layer 1, epitaxial layer 2, the expansion of deep layer doped diffusion region 3, surface doping from bottom to top
Scattered area 4 and passivation layer 5, passivation layer 5 are silicon dioxide passivation layer.
Substrate layer 1 is N+ type substrate layers, and epitaxial layer 2 is N-type epitaxial layer, and 2 thickness of epitaxial layer is 30 μm, corresponding deep layer
Doped diffusion region 3 and surface doping diffusion region 4 are respectively N+ moldeed depth layers doped diffusion region 3, P+ type surface doping diffusion region 4.
At this moment, due to the PN junction relation between each layer, chip is chip of the top as anode.
As shown in Fig. 2 being the sectional view of traditional Zener diode chip in figure, a P+ type is contains only in chip and is mixed
Miscellaneous area, is single-junction structure.Tie in contrast to deep layer P/N in traditional structure, the present invention, zone line and material internal region, i.e., deeply
Intrinsic junction breakdown voltage of the intrinsic breakdown voltage of layer doped diffusion region 3 much smaller than outer peripheral areas, when device works, in small electric
Pressure, zone line P/N knot avalanche breakdowns, while outer peripheral areas P/N knot is surface doping diffusion region 4 in puncturing much smaller than which
The reverse biased area of voltage, provides only minimum reverse leakage, and the breakdown voltage of device is by the uniform Electric Field Distribution of zone line
Determine, it is to avoid the prebreakdown phenomenon of unijunction device junction fringe field, so as to providing stable dynamic electric resistor performance for device.
According to a kind of above-mentioned production technology of plane binode type Zener diode chip, its step is as follows:
1) clean:Lot number establishment is carried out to silicon chip, silicon chip surface is rinsed in mark number, rear deionized water, removes mark number
When the dust that falls in silicon chip surface, then silicon chip is put in baking oven and is dried;
2) initial fields oxidation:Silicon chip after drying is sent in 900~1100 DEG C of oxidation furnace, layer of oxide layer is grown;
3) first time photoetching:Silicon chip after step 2 is aoxidized leaves photoetching through gluing, exposure, development, etching procedure
Figure, region are deep layer doped diffusion region 3, and silicon chip is immersed in 10 minutes in SPM solution, and photoresist is removed;SPM solution is
Dioxysulfate water mixed liquid, is the cleaning solution of standard configuration;
4) deep layer doping:Silicon chip surface is injected into phosphonium ion, is doped, phosphonium ion Implantation Energy be 50KeV, ion
Implantation dosage is 1.0E15cm-2;
5) deep layer diffusion:Silicon chip after doping is put in diffusion furnace carries out phosphorus diffusion propulsion, and diffusion furnace temperature is 1100
~1250 DEG C, form N+ moldeed depth layers doped diffusion region 3;
6) second photoetching:By the silicon chip obtained in step 5 through operations such as gluing, exposure, development, deoxidations, stay
Litho pattern, region are surface doping diffusion region, and silicon chip is immersed in 10 minutes in SPM solution, and photoresist is removed;
7) surface doping:Silicon chip surface is injected into boron ion, is doped;
8) diffusion into the surface:Silicon chip after step 7 is adulterated carries out boron diffusion propulsion in being put into diffusion furnace, diffusion furnace temperature is
1100~1250 DEG C, surface doping is carried out using boron ion and diffuse to form P+ type surface doping diffusion region, ion implantation energy
For 40KeV, ion implantation dosage is 1.2E16cm-2;
9) second oxidation:The silicon chip that step 8 is obtained sends into 900~1100 DEG C of oxidation furnace, grows one layer of oxidation
Layer;
10) third time photoetching:Contact hole photoetching, the silicon chip after step 9 is aoxidized is through gluing, exposure, development, etching work
Sequence, leaves litho pattern, and figure is 5 shape of passivation layer, after silicon chip is immersed in 10 minutes in SPM solution, photoresist is removed;
11) clean:In the silicon chip immersion B-clean solution that step 10 is obtained, the B-clean solution is included successively
SPM solution, i.e. dioxysulfate water mixed liquid, for the photoresistance on cleaning silicon chip surface, Organic substance;Comprising DHF solution, it is Fluohydric acid.
And hydrogen peroxide mixed solution, it is standard solution, for the natural oxidizing layer on cleaning silicon chip surface;Comprising SC1 solution, by volume ratio
For ammonia:Hydrogenperoxide steam generator:Water=1:1:5-1:2:7 are mixed to get, and described ammonia concn mass concentration is 27%, is used for
The granule foreign on cleaning silicon chip surface;Comprising SC2 solution, by volume ratio hydrogen chloride:Hydrogenperoxide steam generator:Water=1:1:6-1:2:
8 are mixed to get, and it is 30% that described hydrogen chloride mass concentration is 37%, hydrogenperoxide steam generator mass concentration;For cleaning silicon chip
The metal ion on surface, above-mentioned after each step solution, all need deionized water to rinse on silicon chip debris, finally by silicon
Piece is put into oven for drying;
12) front-side metallization:The silicon chip that step 11 is obtained carries out surface evaporation, one layer of titanium of surface evaporation,
Then evaporate one layer of aluminum metal, form front metal layer 6;
13) four mask:Metal lithographic, by the silicon chip after metallization through gluing, exposure, development, etching procedure, stays
Lower litho pattern, figure are 6 shape of front metal layer, and silicon chip is immersed in 10 minutes in SPM solution, and photoresist is removed;
14) thinning back side:The silicon chip that step 13 is obtained carries out back and polishes off, and piece thickness is retained in 210um;
15) clean:In the silicon chip immersion ethanol that step 14 is obtained and the mixed solution of fluohydric acid gas, alcohol concentration is
99.7%, hydrogen fluoride solution mass concentration is 40%, and ratio is volume ratio ethanol:Fluohydric acid gas=1:2.Then two are carried out to silicon chip
Silicon chip is dried by secondary distilled water cleaning using chip drier;
16) back face metalization:The silicon chip that step 15 is obtained carries out back side evaporation, and one layer of titanium is evaporated at the back side,
Then evaporate one layer of nickel metal, one layer of silver metal of final evaporation;Form metal layer on back 7;
17) chip cutting:The silicon chip that step 16 is obtained is divided into into one single chip with scribing machine.
Then chip can be tested;Scribing can not also be carried out, directly full wafer is tested.
Chip parameter is as follows:
Breakdown voltage=16V+/- 5%
Forward voltage (IF=200mA)<1.0V
Reverse leakage current IR@12V<50nA
250 μ A of dynamic electric resistor ZZT@<100ohms.
Chip has breakdown voltage and forward voltage gap big, reverse leakage current is little, it is to avoid unijunction device junction edge electricity
The prebreakdown phenomenon of field, with stable dynamic electric resistor.
Embodiment 2
A kind of plane binode type Zener diode chip, including chip, front metal layer 6 and metal layer on back 7, substrate layer
1st, epitaxial layer 2, deep layer doped diffusion region 3, surface doping diffusion region 4 and passivation layer 5, described chip are Zener diode core
Piece;Chip cuts layer and is followed successively by substrate layer 1, epitaxial layer 2, deep layer doped diffusion region 3, surface doping diffusion region 4 and blunt from bottom to top
Change layer 5, passivation layer 5 is silicon dioxide passivation layer.
Substrate layer 1 is P+ type substrate layer, and epitaxial layer 2 is P-type epitaxial layer, and 2 thickness of epitaxial layer is 5 μm, and corresponding deep layer is mixed
Miscellaneous diffusion region 3 and surface doping diffusion region 4 are respectively P+ type deep layer doped diffusion region 3, N+ type surface dopings diffusion region 4.
At this moment, due to the PN junction relation between each layer, chip of the chip for top cathode.
According to a kind of above-mentioned production technology of plane binode type Zener diode chip, its step is as follows:
1) clean:Lot number establishment is carried out to silicon chip, silicon chip surface is rinsed in mark number, rear deionized water, removes mark number
When the dust that falls in silicon chip surface, then silicon chip is put in baking oven and is dried;
2) initial fields oxidation:Silicon chip after drying is sent in 900~1100 DEG C of oxidation furnace, layer of oxide layer is grown;
3) first time photoetching:Silicon chip after step 2 is aoxidized leaves photoetching through gluing, exposure, development, etching procedure
Figure, region are deep layer doped diffusion region 3, and silicon chip is immersed in 10 minutes in SPM solution, and photoresist is removed;SPM solution is
Dioxysulfate water mixed liquid, is the cleaning solution of standard configuration;
4) deep layer doping:Silicon chip surface is injected into boron ion, is doped, boron ion Implantation Energy be 80KeV, ion
Implantation dosage is 4.0E15cm-2;
5) deep layer diffusion:Silicon chip after doping is put in diffusion furnace carries out boron diffusion propulsion, and diffusion furnace temperature is 1100
~1250 DEG C, form P+ type deep layer doped diffusion region 3;
6) second photoetching:By the silicon chip obtained in step 5 through operations such as gluing, exposure, development, deoxidations, stay
Litho pattern, region are surface doping diffusion region 4, and silicon chip is immersed in 10 minutes in SPM solution, and photoresist is removed;
7) surface doping:Silicon chip surface is injected into phosphonium ion, is doped;
8) diffusion into the surface:Silicon chip after step 7 is adulterated carries out phosphorus diffusion propulsion in being put into diffusion furnace, diffusion furnace temperature is
1100~1250 DEG C, surface doping is carried out using phosphonium ion and diffuse to form N+ type surface dopings diffusion region 4, ion implantation energy
For 80KeV, ion implantation dosage is 1.2E16cm-2;
9) second oxidation:The silicon chip that step 8 is obtained sends into 900~1100 DEG C of oxidation furnace, grows one layer of oxidation
Layer;
10) third time photoetching:Contact hole photoetching, the silicon chip after step 9 is aoxidized is through gluing, exposure, development, etching work
Sequence, leaves litho pattern, and figure is 5 shape of passivation layer, after silicon chip is immersed in 10 minutes in SPM solution, photoresist is removed;
11) clean:In the silicon chip immersion B-clean solution that step 10 is obtained, the B-clean solution is included successively
SPM solution, DHF solution, SC1 solution, SC2 solution, it is above-mentioned after each step solution, all to need deionized water to rinse on silicon chip
Debris, silicon chip is put into into oven for drying finally;
12) front-side metallization:The silicon chip that step 11 is obtained carries out surface evaporation, one layer of titanium of surface evaporation,
Then evaporate one layer of aluminum metal, form front metal layer 6;
13) four mask:Metal lithographic, by the silicon chip after metallization through gluing, exposure, development, etching procedure, stays
Lower litho pattern, figure are 6 shape of front metal layer, and silicon chip is immersed in 10 minutes in SPM solution, and photoresist is removed;
14) thinning back side:The silicon chip that step 13 is obtained carries out back and polishes off, and piece thickness is retained in 200um;
15) clean:In the silicon chip immersion ethanol that step 14 is obtained and the mixed solution of fluohydric acid gas, then silicon chip is carried out
Redistilled water is cleaned, and is dried silicon chip using chip drier;
16) back face metalization:The silicon chip that step 15 is obtained carries out back side evaporation, and one layer of titanium is evaporated at the back side,
Then evaporate one layer of nickel metal, one layer of silver metal of final evaporation;Form metal layer on back 7;
17) chip cutting:The silicon chip that step 16 is obtained is divided into into one single chip with scribing machine.
Then chip can be tested;Scribing can not also be carried out, directly full wafer is tested.
Chip parameter:
Breakdown voltage=9.1V+/- 5%
Forward voltage (IF=200mA)<1.0V
Reverse leakage current IR@7.0V<1.0μA
250 μ A of dynamic electric resistor ZZT@<500ohms.
Embodiment 3
A kind of plane binode type Zener diode chip, including chip, front metal layer 6 and metal layer on back 7, substrate layer
1st, epitaxial layer 2, deep layer doped diffusion region 3, surface doping diffusion region 4 and passivation layer 5, described chip are Zener diode core
Piece;Chip cuts layer and is followed successively by substrate layer 1, epitaxial layer 2, deep layer doped diffusion region 3, surface doping diffusion region 4 and blunt from bottom to top
Change layer 5, passivation layer 5 is silicon dioxide passivation layer.
Substrate layer 1 is P+ type substrate layer, and epitaxial layer 2 is P-type epitaxial layer, and 2 thickness of epitaxial layer is 10 μm, corresponding deep layer
Doped diffusion region 3 and surface doping diffusion region 4 are respectively P+ type deep layer doped diffusion region 3, N+ type surface dopings diffusion region 4.
At this moment, due to the PN junction relation between each layer, chip of the chip for top cathode.
According to a kind of above-mentioned production technology of plane binode type Zener diode chip, its step is as follows:
1) clean:Lot number establishment is carried out to silicon chip, silicon chip surface is rinsed in mark number, rear deionized water, removes mark number
When the dust that falls in silicon chip surface, then silicon chip is put in baking oven and is dried;
2) initial fields oxidation:Silicon chip after drying is sent in 900~1100 DEG C of oxidation furnace, layer of oxide layer is grown;
3) first time photoetching:Silicon chip after step 2 is aoxidized leaves photoetching through gluing, exposure, development, etching procedure
Figure, region are deep layer doped diffusion region 3, and silicon chip is immersed in 10 minutes in SPM solution, and photoresist is removed;SPM solution is
Dioxysulfate water mixed liquid, is the cleaning solution of standard configuration;
4) deep layer doping:Silicon chip surface is injected into boron ion, is doped, boron ion Implantation Energy be 40KeV, ion
Implantation dosage is 1.0E12cm-2;
5) deep layer diffusion:Silicon chip after doping is put in diffusion furnace carries out boron diffusion propulsion, and diffusion furnace temperature is 1100
~1250 DEG C, form P+ type deep layer doped diffusion region;
6) second photoetching:By the silicon chip obtained in step 5 through operations such as gluing, exposure, development, deoxidations, stay
Litho pattern, region are surface doping diffusion region 4, and silicon chip is immersed in 10 minutes in SPM solution, and photoresist is removed;
7) surface doping:Silicon chip surface is injected into phosphonium ion, is doped;
8) diffusion into the surface:Silicon chip after step 7 is adulterated carries out phosphorus diffusion propulsion in being put into diffusion furnace, diffusion furnace temperature is
1100~1250 DEG C, surface doping is carried out using phosphonium ion and diffuse to form N+ type surface dopings diffusion region 4, ion implantation energy
For 80KeV, ion implantation dosage is 2.2E16cm-2;
9) second oxidation:The silicon chip that step 8 is obtained sends into 900~1100 DEG C of oxidation furnace, grows one layer of oxidation
Layer;
10) third time photoetching:Contact hole photoetching, the silicon chip after step 9 is aoxidized is through gluing, exposure, development, etching work
Sequence, leaves litho pattern, and figure is 5 shape of passivation layer, after silicon chip is immersed in 10 minutes in SPM solution, photoresist is removed;
11) clean:In the silicon chip immersion B-clean solution that step 10 is obtained, the B-clean solution is included successively
SPM solution, DHF solution, SC1 solution, SC2 solution, it is above-mentioned after each step solution, all to need deionized water to rinse on silicon chip
Debris, silicon chip is put into into oven for drying finally;
12) front-side metallization:The silicon chip that step 11 is obtained carries out surface evaporation, one layer of titanium of surface evaporation,
Then evaporate one layer of aluminum metal, form front metal layer 6;
13) four mask:Metal lithographic, by the silicon chip after metallization through gluing, exposure, development, etching procedure, stays
Lower litho pattern, figure are 6 shape of front metal layer, and silicon chip is immersed in 10 minutes in SPM solution, and photoresist is removed;
14) thinning back side:The silicon chip that step 13 is obtained carries out back and polishes off, and piece thickness is retained in 230um;
15) clean:In the silicon chip immersion ethanol that step 14 is obtained and the mixed solution of fluohydric acid gas, then silicon chip is carried out
Redistilled water is cleaned, and is dried silicon chip using chip drier;
16) back face metalization:The silicon chip that step 15 is obtained carries out back side evaporation, and one layer of titanium is evaporated at the back side,
Then evaporate one layer of nickel metal, one layer of silver metal of final evaporation;Form metal layer on back 7;
17) chip cutting:The silicon chip that step 16 is obtained is divided into into one single chip with scribing machine.
Then chip can be tested;Scribing can not also be carried out, directly full wafer is tested.
Chip parameter:
Breakdown voltage=12V+/- 5%
Forward voltage (IF=200mA)<1.0V
Reverse leakage current IR@9.0V<1.0μA
250 μ A of dynamic electric resistor ZZT@<550ohms.
Below schematically the invention and embodiments thereof are described, the description does not have restricted, accompanying drawing
Shown in be also the invention one of embodiment, actual structure is not limited thereto.So, if this area
Those of ordinary skill by its enlighten, in the case of without departing from this creations objective, without creativeness design and the technology
The similar frame mode of scheme and embodiment, all should belong to the protection domain of this patent.
Claims (9)
1. a kind of plane binode type Zener diode chip, including chip, front metal layer (6) and metal layer on back (7), which is special
Levy and be:Described chip includes substrate layer (1), epitaxial layer (2), deep layer doped diffusion region (3), surface doping diffusion region (4)
With passivation layer (5), described chip is Zener diode chip;Chip cuts layer and is followed successively by substrate layer (1), epitaxial layer from bottom to top
(2), deep layer doped diffusion region (3), surface doping diffusion region (4) and passivation layer (5);
Chip is obtained using following technique:
1) clean:Lot number establishment, mark number are carried out to silicon chip, rear deionized water rinses silicon chip surface or with machine in silicon chip
Surface swabbing, removes the dust fallen in silicon chip surface during mark, then silicon chip is put in baking oven and is dried;
2) initial fields oxidation:Silicon chip after drying is sent in 900~1100 DEG C of oxidation furnace, layer of oxide layer is grown;
3) first time photoetching:Silicon chip after step 2 is aoxidized leaves litho pattern through gluing, exposure, development, etching procedure,
And silicon chip is immersed in 10 minutes in SPM solution, photoresist is removed;
4) deep layer doping:Silicon chip surface is injected into phosphorus or boron ion, is doped;
5) deep layer diffusion:Silicon chip after doping is put in diffusion furnace carries out phosphorus or boron diffusion propulsion, and phosphorus or boron are selected and step 4
Intermediate ion is identical, forms deep layer doped diffusion region (3), carries out deep layer doping and diffusion using phosphonium ion and forms the doping of N+ moldeed depth layer
Diffusion region, carries out deep layer doping and diffusion using boron ion and forms P+ type deep layer doped diffusion region;
6) second photoetching:By the silicon chip obtained in step 5 through operations such as gluing, exposure, development, deoxidations, photoetching is left
Figure, and silicon chip is immersed in 10 minutes in SPM solution, photoresist is removed;
7) surface doping:Silicon chip surface is injected into boron or phosphonium ion, is doped, phosphorus or boron are selected with step 4 intermediate ion not
Together, phosphonium ion injection used in step 4, then this step from boron ion injection, used in step 4, inject by boron ion, then this step
It is rapid to be injected from phosphonium ion;
8) diffusion into the surface:Silicon chip after step 7 is adulterated carries out boron or phosphorus diffusion propulsion in being put into diffusion furnace, phosphorus or boron select with
Step 7 intermediate ion is identical, carries out surface doping using boron ion and diffuses to form P+ type surface doping diffusion region, and phosphonium ion is carried out
Deep layer doping and diffusion forms N+ moldeed depth layers doped diffusion region;
9) second oxidation:The silicon chip that step 8 is obtained sends into 900~1100 DEG C of oxidation furnace, grows layer of oxide layer;
10) third time photoetching:Contact hole photoetching, the silicon chip after step 9 is aoxidized through gluing, exposure, development, etching procedure,
Leave litho pattern, figure is passivation layer (5) shape, after silicon chip is immersed in 10 minutes in SPM solution, photoresist is removed;
11) clean:In the silicon chip immersion B-clean solution that step 10 is obtained, the B-clean solution is molten comprising SPM successively
Liquid, DHF solution, SC1 solution, SC2 solution, the above-mentioned residual that all deionized water is rinsed on silicon chip after each step solution
Liquid, carries out a kind of lower solution, silicon chip is put into oven for drying finally;
12) front-side metallization:The silicon chip that step 11 is obtained carries out surface evaporation, one layer of titanium of surface evaporationThen
One layer of aluminum metal of evaporationForm front metal layer (6);
13) four mask:Metal lithographic, by the silicon chip after metallization through gluing, exposure, development, etching procedure, leaves light
Needle drawing shape, figure are front metal layer (6) shape, and silicon chip is immersed in 10 minutes in SPM solution, and photoresist is removed;
14) thinning back side:The silicon chip that step 13 is obtained carries out back and polishes off, and piece thickness is retained in 200~230um;
15) clean:In the silicon chip immersion ethanol that step 14 is obtained and the mixed solution of fluohydric acid gas, then silicon chip is carried out secondary
Distilled water is cleaned, and is dried silicon chip using chip drier;
16) back face metalization:The silicon chip that step 15 is obtained carries out back side evaporation, and one layer of titanium is evaporated at the back sideThen
One layer of nickel metal of evaporationOne layer of silver metal of final evaporationForm metal layer on back (7);
17) chip cutting:The silicon chip that step 16 is obtained is divided into into one single chip with scribing machine.
2. a kind of plane binode type Zener diode chip according to claim 1, it is characterised in that:Described substrate layer
(1) it is N+ type substrate layers, described epitaxial layer (2) is N-type epitaxial layer, corresponding deep layer doped diffusion region (3) and surface doping
Diffusion region (4) is respectively N+ moldeed depth layers doped diffusion region (3), P+ type surface doping diffusion region (4).
3. a kind of plane binode type Zener diode chip according to claim 1, it is characterised in that:Described substrate layer
(1) it is P+ type substrate layer, described epitaxial layer (2) is P-type epitaxial layer, corresponding deep layer doped diffusion region (3) and surface doping
Diffusion region (4) is respectively P+ deep layers doped diffusion region (3), N+ type surface dopings diffusion region (4).
4. a kind of plane binode type Zener diode chip according to claim 1 or 2 or 3, it is characterised in that:Described
Epitaxial layer (2) thickness is 5 μm -30 μm.
5. a kind of plane binode type Zener diode chip according to Claims 2 or 3, it is characterised in that:Described is blunt
It is silicon dioxide passivation layer to change layer (5).
6., according to a kind of plane binode type Zener diode chip production process in claim 1, its step is as follows:
1) clean:Lot number establishment, mark number are carried out to silicon chip, rear deionized water rinses silicon chip surface or with machine in silicon chip
Surface swabbing, removes the dust fallen in silicon chip surface during mark, then silicon chip is put in baking oven and is dried;
2) initial fields oxidation:Silicon chip after drying is sent in 900~1100 DEG C of oxidation furnace, layer of oxide layer is grown;
3) first time photoetching:Silicon chip after step 2 is aoxidized leaves litho pattern through gluing, exposure, development, etching procedure,
And silicon chip is immersed in 10 minutes in SPM solution, photoresist is removed;
4) deep layer doping:Silicon chip surface is injected into phosphorus or boron ion, is doped;
5) deep layer diffusion:Silicon chip after doping is put in diffusion furnace carries out phosphorus or boron diffusion propulsion, and phosphorus or boron are selected and step 4
Intermediate ion is identical, forms deep layer doped diffusion region (3), carries out deep layer doping and diffusion using phosphonium ion and forms the doping of N+ moldeed depth layer
Diffusion region, carries out deep layer doping and diffusion using boron ion and forms P+ type deep layer doped diffusion region;
6) second photoetching:By the silicon chip obtained in step 5 through operations such as gluing, exposure, development, deoxidations, photoetching is left
Figure, and silicon chip is immersed in 10 minutes in SPM solution, photoresist is removed;
7) surface doping:Silicon chip surface is injected into boron or phosphonium ion, is doped, phosphorus or boron are selected with step 4 intermediate ion not
Together, phosphonium ion injection used in step 4, then this step from boron ion injection, used in step 4, inject by boron ion, then this step
It is rapid to be injected from phosphonium ion;
8) diffusion into the surface:Silicon chip after step 7 is adulterated carries out boron or phosphorus diffusion propulsion in being put into diffusion furnace, phosphorus or boron select with
Step 7 intermediate ion is identical, carries out surface doping using boron ion and diffuses to form P+ type surface doping diffusion region, and phosphonium ion is carried out
Deep layer doping and diffusion forms N+ moldeed depth layers doped diffusion region;
9) second oxidation:The silicon chip that step 8 is obtained sends into 900~1100 DEG C of oxidation furnace, grows layer of oxide layer;
10) third time photoetching:Contact hole photoetching, the silicon chip after step 9 is aoxidized through gluing, exposure, development, etching procedure,
Leave litho pattern, figure is passivation layer (5) shape, after silicon chip is immersed in 10 minutes in SPM solution, photoresist is removed;
11) clean:In the silicon chip immersion B-clean solution that step 10 is obtained, the B-clean solution is molten comprising SPM successively
Liquid, DHF solution, SC1 solution, SC2 solution, the above-mentioned residual that all deionized water is rinsed on silicon chip after each step solution
Liquid, carries out a kind of lower solution, silicon chip is put into oven for drying finally;
12) front-side metallization:The silicon chip that step 11 is obtained carries out surface evaporation, one layer of titanium of surface evaporationThen
One layer of aluminum metal of evaporationForm front metal layer (6);
13) four mask:Metal lithographic, by the silicon chip after metallization through gluing, exposure, development, etching procedure, leaves light
Needle drawing shape, figure are front metal layer (6) shape, and silicon chip is immersed in 10 minutes in SPM solution, and photoresist is removed;
14) thinning back side:The silicon chip that step 13 is obtained carries out back and polishes off, and piece thickness is retained in 200~230um;
15) clean:In the silicon chip immersion ethanol that step 14 is obtained and the mixed solution of fluohydric acid gas, then silicon chip is carried out secondary
Distilled water is cleaned, and is dried silicon chip using chip drier;
16) back face metalization:The silicon chip that step 15 is obtained carries out back side evaporation, and one layer of titanium is evaporated at the back sideThen
One layer of nickel metal of evaporationOne layer of silver metal of final evaporationForm metal layer on back (7);
17) chip cutting:The silicon chip that step 16 is obtained is divided into into one single chip with scribing machine.
7. a kind of plane binode type Zener diode chip production process according to claim 6, it is characterised in that:Step
In 4 and 7, ion implantation energy is 40KeV~80KeV.
8. a kind of plane binode type Zener diode chip production process according to claim 7, it is characterised in that:Step
In 4 and 7, ion implantation dosage is 1.0E12cm-2~2.2E16cm-2, the note of the implantation dosage of step 7 more than or equal to step 4
Enter dosage.
9. a kind of plane binode type Zener diode chip production process according to claim 6 or 8, it is characterised in that:
In step 5 and 8, diffusion furnace temperature when phosphorus and boron spread is 1100~1250 DEG C.
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4419681A (en) * | 1979-10-18 | 1983-12-06 | U.S. Philips Corporation | Zener diode |
CN102412268A (en) * | 2011-12-06 | 2012-04-11 | 绍兴旭昌科技企业有限公司 | Flat-type one-way trigger diode chip and manufacturing method thereof |
CN204155940U (en) * | 2014-11-19 | 2015-02-11 | 桑德斯微电子器件(南京)有限公司 | A kind of plane binode type voltage stabilizing didoe chip |
-
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4419681A (en) * | 1979-10-18 | 1983-12-06 | U.S. Philips Corporation | Zener diode |
CN102412268A (en) * | 2011-12-06 | 2012-04-11 | 绍兴旭昌科技企业有限公司 | Flat-type one-way trigger diode chip and manufacturing method thereof |
CN204155940U (en) * | 2014-11-19 | 2015-02-11 | 桑德斯微电子器件(南京)有限公司 | A kind of plane binode type voltage stabilizing didoe chip |
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