CN102412268A - Flat-type one-way trigger diode chip and manufacturing method thereof - Google Patents

Flat-type one-way trigger diode chip and manufacturing method thereof Download PDF

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Publication number
CN102412268A
CN102412268A CN2011104001067A CN201110400106A CN102412268A CN 102412268 A CN102412268 A CN 102412268A CN 2011104001067 A CN2011104001067 A CN 2011104001067A CN 201110400106 A CN201110400106 A CN 201110400106A CN 102412268 A CN102412268 A CN 102412268A
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junction
diffusion layer
silicon chip
chip
concentration
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CN102412268B (en
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邓爱民
吴金姿
徐泓
保爱林
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ZHEJIANG MINGDE MICROELECTRONIC CO., LTD.
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SHAOXING RISING-SUN TECHNOLOGY Co Ltd
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Abstract

The invention discloses a flat-type one-way trigger diode chip and a manufacturing method thereof. The trigger diode chip comprises a silicon chip, wherein the polished surface of the silicon chip is provided with a first PN junction and a first diffusion layer, and a second PN junction and a second diffusion layer are arranged on the first diffusion layer; three layers of structures with gradually changed concentrate, namely a lowest-concentration silicon chip, the first diffusion layer the concentration of which is higher than that of a silicon chip, and the second diffusion layer the concentration of which is higher than that of the first diffusion layer, are formed in the thickness direction of the chip; and the first PN junction and the second PN junction which are exposed on the polished surface of the silicon chip are covered by passivation layers, and metal conducting layer are deposited on the upper surface of the second diffusion layer and the back of the silicon chip. The trigger diode chip provided by the invention has the characteristics of simple manufacture procedure process,high reliability, capability of being alternatively applied to the two-way trigger diode in a half-bridge inverter start circuit, and the like.

Description

Planar mono is to diac chip and manufacturing approach thereof
Technical field
The present invention relates to a kind of semiconductor device, particularly a kind of planar mono is to diac chip and manufacturing approach thereof.
Background technology
Bidirectional trigger diode is a kind of bilateral device, has symmetrical negative resistance charactertistic at I, III quadrant, is widely used in the half bridge oscillator of electricity-saving lamp.Traditional bidirectional trigger diode chip is to form two special-shaped series connection to the directional diffusion of silicon chip and PN junctions symmetry constitute by impurity, through two-sided corrosion formation table top.This technology is strict to the thickness requirement of silicon chip, and its thickness must be less than 150 μ m, because of characteristic needs, two PN junction spacings very narrow (about 40 μ m), in two mesa etch processes the processing procedure loss higher, bring great difficulty to production.
In fact in the electricity-saving lamp start-up circuit, only use the unijunction trigger characteristic.And only need have the much lower reverse blocking voltage of a puncture voltage to get final product to other direction.This application conditions reminds us to accomplish the symmetrical electrical characteristics that same triggering function may not need I, III quadrant.Therefore, the invention discloses a kind of planar mono to diac chip and manufacturing approach thereof.Be different from bidirectional trigger diode chip, planar mono is made up of two asymmetric PN junctions to diac, and its electrical characteristics and bidirectional trigger diode in the I quadrant is identical, then is the emitter junction characteristic of triode at the III quadrant.
Summary of the invention
The purpose of this invention is to provide that a kind of making technology is simple, reliability is high, the replaceable planar mono that is applied to bidirectional trigger diode in the energy-conservation lamp half-bridge inverter start-up circuit is to diac chip and manufacturing approach thereof.
For achieving the above object, the present invention realizes through following technical scheme: planar mono comprises silicon chip to the diac chip; On the burnishing surface of silicon chip, be provided with first PN junction and first diffusion layer, on first diffusion layer, be provided with second PN junction and second diffusion layer, and first PN junction and second PN junction are the curved surface knot; This chip has formed the three-decker of concentration gradient at thickness direction; Be respectively the minimum silicon chip of concentration, its concentration C 1 is 9.5E15~5E16, and concentration is higher than first diffusion layer of silicon chip; Its maximum concentration C2 is 1.5E17~8E17; Concentration is higher than second diffusion layer of first diffusion layer, and its maximum concentration C3 is 1E20~2E21, and the distance between first PN junction and second PN junction is 0.5~10 micron; Be exposed at first PN junction and second PN junction on the polished surface of silicon chip and be coated with passivation layer, at the upper surface and the silicon chip backside deposition metal conducting layer of second diffusion layer.
Described planar mono is to the diac chip, and its passivation layer can be that hot growing silicon oxide, the silica with LPCVD method deposition, hot growing silicon oxide are with the layer compound passivation of the silicon nitride that deposits with the LPCVD method, with the silica of LPCVD method deposition and the layer compound passivation of silicon nitride.
A kind of planar mono of making to the method for diac chip is: a. grew as the silicon oxide film of masking layer through 1050~1200 ℃ of following wet-oxygen oxidations on the silicon chip burnishing surface in 0.5~2 hour; Photoetching forms once spreads window; B. the good silicon chip of photoetching was placed 800~1050 ℃ of following pre-depositions 30~200 minutes; Make its surface deposition concentration be higher than the concentration C 1 and the conduction type impurity in contrast of silicon chip; Form first PN junction and first diffusion layer, the silicon chip that c. will form first PN junction and first diffusion layer places the diffusion 2~5 hours that distributes again under 1100~1200 ℃ the aerobic environment, makes the maximum concentration C2 of first diffusion layer reach 1.5E17~8E17; Meanwhile deposit masking layer as the secondary diffusion; And carry out secondary light and carve to form secondary diffusion window, the silicon chip that d. is good with the secondary photoetching placed 800~1100 ℃ of following pre-depositions 20~80 minutes, made its surface deposition concentration be higher than the maximum concentration C2 of first diffusion layer and the impurity of conductivity type opposite with it; Form second PN junction and second diffusion layer; The silicon chip that e. will form second PN junction and second diffusion layer places the diffusion 30~90 minutes that distributes again under 800~1000 ℃ the aerobic environment, and making the distance between first PN junction and second PN junction is 0.5~10 micron, and the maximum concentration C3 of second diffusion layer reaches 1E20~2E21.F. be exposed to deposit passivation layer on the polished surface of silicon chip at two PN junctions, first PN junction and second PN junction that are exposed to the silicon chip surface are implemented to cover, g. accomplishes metallization at the upper surface and the silicon chip backside deposition metal conducting layer of second diffusion layer.
Described manufacturing planar mono is to the method for diac chip, and its silicon chip is chemical polishing sheet or mechanically-polished slice.
Described manufacturing planar mono is to the method for diac chip, and its diffusion way is for sheltering diffusion.
The present invention is owing to adopted technique scheme; Have the following advantages with existing device and compared with techniques: (one) has solved problem strict to silicon wafer thickness and that the processing procedure loss is big: for bidirectional trigger diode chip; For satisfying the binode characteristic; Silicon wafer thickness must be less than 150 microns, and the silicon slice corrosion separation is narrower after two-sided corrosion forms two table tops, the big and operating difficulties of processing procedure loss.Only need spacing and the concentration of diffusion layer through regulating two PN junctions to make first PN junction satisfy desirable characteristics for the present invention, silicon wafer thickness is not had any requirement, be convenient to operation; (2) solved the problem that two mesa bidirectional trigger diode chips are surveyed in can't be automatically: for two mesa bidirectional trigger diode chips, need test respectively on the branch two sides during underway survey, therefore can't realize the full-automatic probe test of wafer.First PN junction of electrical parameter only need test to(for) the present invention gets final product, and has saved the half the testing time, can realize full-automatic middle survey of wafer; (3) can realize full-automatic operation: two mesa bidirectional trigger diode chip test time-division faces are tested, are got ready; When manipulator is got material; The figure of getting ready that is positioned at the crystal grain back side can't be by machine recognition, and therefore two mesa bidirectional trigger diodes can't be realized full-automatic operation., test, get ready all and can accomplish owing to only need test wherein simultaneously electrically for the present invention, therefore can realize full-automatic operation in one side; (4) planar mono can be made in the same one side of silicon chip thereby can adopt the planar technique manufacturing to the PN junctions of diac chip owing to its two special-shaped series connection; Single face photoetching and single face diffusion; Avoid the trouble of two-sided manufacture craft, saved technologies such as mesa etch and etching tank glassivation.
Description of drawings
Fig. 1 is existing bidirectional trigger diode characteristic curve sketch map.
Fig. 2 is that planar mono of the present invention is to diac characteristic curve sketch map.
Fig. 3 is NP of the present invention +N ++The type planar mono is to diac chip structure sketch map.
Fig. 4 is that planar mono of the present invention is to diac chip concentration profile.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are described in further detail.
Embodiment 1: like Fig. 3, shown in Figure 4, planar mono comprises silicon chip 1 to the diac chip; On the burnishing surface of silicon chip 1, be provided with first PN junction 2 and first diffusion layer 3; On first diffusion layer 3, be provided with second PN junction 4 and second diffusion layer 5, and first PN junction 2 and second PN junction 4 be the curved surface knot, this chip has formed the three-decker of concentration gradient at thickness direction; Be respectively the minimum silicon chip of concentration 1; Its concentration C 1 is 9.5E15~5E16, and concentration is higher than first diffusion layer 3 of silicon chip 1, and its maximum concentration C2 is 1.5E17~8E17; Concentration is higher than second diffusion layer 5 of first diffusion layer 3; Its maximum concentration C3 is 1E20~2E21, and the distance 6 between first PN junction 2 and second PN junction 4 is 0.5~10 micron, is exposed at first PN junction 2 and second PN junction 4 on the polished surface 7 of silicon chip 1 to be coated with passivation layer 8; At the upper surface and the silicon chip 1 backside deposition metal conducting layer 9 of second diffusion layer 5, passivation layer 8 can be that hot growing silicon oxide, the silica with LPCVD method deposition, hot growing silicon oxide are with the layer compound passivation of the silicon nitride that deposits with the LPCVD method, with the silica of LPCVD method deposition and the layer compound passivation of silicon nitride.
Embodiment 2: as shown in Figure 4; Choose concentration C 1 and be the N type silicon chip 1 of 3.7E16; On the chemical polished surface of silicon chip 1, once spread window as the silicon oxide film and the photoetching formation of masking layer through 1 hour deposition of 1150 degrees centigrade of following wet-oxygen oxidations; The silicon chip 1 that a photoetching is good places 875 degrees centigrade of following pre-deposition concentration to be higher than the p type impurity 50 minutes of silicon chip 1, forms first PN junction 2 and first diffusion layer 3; And distributed again in the oxygen atmosphere 3 hours 1100 degrees centigrade have, make first diffusion layer, 3 maximum concentration C2 reach 2.5E+17; Meanwhile deposit masking layer, and carry out secondary light and carve formation secondary diffusion window as the secondary diffusion; Be higher than the N type impurity 25 minutes of the maximum concentration C2 of first diffusion layer 3 then 970 degrees centigrade of following pre-deposition concentration, form second PN junction 4 and second diffusion layer 5; The silicon chip that forms second PN junction 4 and second diffusion layer 5 places the aerobic environment under 850 degrees centigrade to distribute 80 minutes again, and making first PN junction and the 2nd PN spacing 6 is 1.5 microns, and the maximum concentration C3 of second diffusion layer 5 reaches 2E20; Be exposed on the polished surface 7 of silicon chip deposition at two PN junctions and first PN junction 2 that is exposed on the silicon chip polished surface 7 implemented coverings with second PN junction 4 as the silicon oxide film 8 of passivation layer; Adopt chemical nickel plating at the upper surface of second diffusion layer 5 and the backside deposition nickel dam 9 of silicon chip 1, and, accomplish metallization in 420 degrees centigrade of following alloys 30 minutes.
Embodiment 3: as shown in Figure 4; Choose concentration C 1 and be the N type silicon chip 1 of 3.7E16; On the mechanical polishing face of silicon chip 1, once spread window as the silicon oxide film and the photoetching formation of masking layer through 1.5 hours depositions of 1100 degrees centigrade of following wet-oxygen oxidations; The silicon chip 1 that a photoetching is good places 1000 degrees centigrade of following pre-deposition concentration to be higher than the p type impurity 150 minutes of silicon chip 1, forms first PN junction 2 and first diffusion layer 3; And distributed again in the oxygen atmosphere 5 hours 1150 degrees centigrade have, make first diffusion layer, 3 maximum concentration C2 reach 8.0E+17; Meanwhile deposit masking layer, and carry out secondary light and carve formation secondary diffusion window as the secondary diffusion; Be higher than the N type impurity 30 minutes of the maximum concentration C2 of first diffusion layer 3 then 850 degrees centigrade of following pre-deposition concentration, form second PN junction 4 and second diffusion layer 5; And distributed again in the aerobic environment under 950 degrees centigrade 45 minutes, making first PN junction and the 2nd PN spacing 6 is 6.5 microns, the maximum concentration C3 of second diffusion layer 5 reaches 4E20; Be exposed on the polished surface 7 of silicon chip deposition at two PN junctions and first PN junction 2 that is exposed on the silicon chip polished surface 7 implemented coverings with second PN junction 4 as the silicon oxide film 8 of passivation layer; Adopt chemical nickel plating at the upper surface of second diffusion layer 5 and the backside deposition nickel dam 9 of silicon chip 1, and, accomplish metallization in 420 degrees centigrade of following alloys 30 minutes.
More than the present invention has been done detailed description, can not think that protection scope of the present invention only is confined to above-mentioned execution mode.If do not have to produce difference in essence, the deduction or replace of above-mentioned execution mode still are regarded as within protection scope of the present invention with the technical scheme of claim of the present invention.

Claims (5)

1. a planar mono is to the diac chip; Comprise silicon chip (1); It is characterized in that: on the burnishing surface of silicon chip (1), be provided with first PN junction (2) and first diffusion layer (3), on first diffusion layer (3), be provided with second PN junction (4) and second diffusion layer (5), and first PN junction (2) and second PN junction (4) are the curved surface knot; This chip has formed the three-decker of concentration gradient at thickness direction; Be respectively the minimum silicon chip of concentration (1), its concentration (C1) is 9.5E15~5E16, and concentration is higher than first diffusion layer (3) of silicon chip (1); Its maximum concentration (C2) is 1.5E17~8E17; Concentration is higher than second diffusion layer (5) of first diffusion layer (3), and its maximum concentration (C3) is 1E20~2E21, and the distance (6) between first PN junction (2) and second PN junction (4) is 0.5~10 micron; Be exposed at first PN junction (2) and second PN junction (4) on the polished surface (7) of silicon chip (1) and be coated with passivation layer (8), at the upper surface and silicon chip (1) the backside deposition metal conducting layer (9) of second diffusion layer (5).
2. planar mono according to claim 1 is characterized in that to the diac chip: passivation layer (8) can be that hot growing silicon oxide, the silica with LPCVD method deposition, hot growing silicon oxide are with the layer compound passivation of the silicon nitride that deposits with the LPCVD method, with the silica of LPCVD method deposition and the layer compound passivation of silicon nitride.
3. method from planar mono to the diac chip that make, its manufacturing approach is:
A. on silicon chip (1) burnishing surface, grew in 0.5~2 hour as the silicon oxide film of masking layer through 1050~1200 ℃ of following wet-oxygen oxidations, photoetching forms once spreads window,
B. a photoetching is good silicon chip (1) placed 800~1050 ℃ of following pre-depositions 30~200 minutes; Make its surface deposition concentration be higher than the concentration (C1) and the conduction type impurity in contrast of silicon chip (1); Form first PN junction (2) and first diffusion layer (3)
The silicon chip (1) that c. will form first PN junction (2) and first diffusion layer (3) places the diffusion 2~5 hours that distributes again under 1100~1200 ℃ the aerobic environment; Make the maximum concentration (C2) of first diffusion layer (3) reach 1.5E17~8E17; Meanwhile deposit masking layer as the secondary diffusion; And carry out secondary light and carve formation secondary diffusion window
D. the secondary photoetching is good silicon chip (1) placed 800~1100 ℃ of following pre-depositions 20~80 minutes; Make its surface deposition concentration be higher than the maximum concentration (C2) of first diffusion layer (3) and the impurity of conductivity type opposite with it; Form second PN junction (4) and second diffusion layer (5)
The silicon chip (1) that e. will form second PN junction (4) and second diffusion layer (5) places the diffusion 30~90 minutes that distributes again under 800~1000 ℃ the aerobic environment; Making the distance (6) between first PN junction (2) and second PN junction (4) is 0.5~10 micron; The maximum concentration (C3) of second diffusion layer (5) reaches 1E20~2E21
F. be exposed to the last deposit passivation layer (8) of polished surface (7) of silicon chip (1) at two PN junctions, first PN junction (2) and second PN junction (4) that are exposed to silicon chip (1) surface implemented to cover,
G. at the upper surface and silicon chip (1) the backside deposition metal conducting layer (9) of second diffusion layer (5), accomplish metallization.
4. manufacturing planar mono according to claim 3 is characterized in that to the method for diac chip: described silicon chip (1) is chemical polishing sheet or mechanically-polished slice.
5. manufacturing planar mono according to claim 3 is characterized in that to the method for diac chip: described diffusion way is for sheltering diffusion.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104347731A (en) * 2013-08-08 2015-02-11 无锡华润华晶微电子有限公司 Diode structure
CN104362182A (en) * 2014-11-19 2015-02-18 桑德斯微电子器件(南京)有限公司 Planar double-knot type voltage stabilizing diode chip and producing process thereof
CN106653869A (en) * 2016-12-14 2017-05-10 丽晶美能(北京)电子技术有限公司 Power diode
CN117219677A (en) * 2023-10-11 2023-12-12 杭州致善微电子科技有限公司 Limiting diode with anode concentration gradient linear distribution and preparation method thereof
CN118213372A (en) * 2024-05-21 2024-06-18 天水天光半导体有限责任公司 16-Bit transparent latch

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CN101399201A (en) * 2008-11-13 2009-04-01 杭州杭鑫电子工业有限公司 Method for manufacturing silicon bidirectional trigger diode
CN101651102A (en) * 2009-08-25 2010-02-17 南通明芯微电子有限公司 Bidirectional trigger diode chip production method
CN101719507A (en) * 2009-09-28 2010-06-02 绍兴科盛电子有限公司 Single table surface series plane PN junction chip and manufacturing method thereof

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Publication number Priority date Publication date Assignee Title
EP1198838A1 (en) * 1999-08-04 2002-04-24 Infineon Technologies AG Protective structure against electrostatic discharges
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CN101399201A (en) * 2008-11-13 2009-04-01 杭州杭鑫电子工业有限公司 Method for manufacturing silicon bidirectional trigger diode
CN101651102A (en) * 2009-08-25 2010-02-17 南通明芯微电子有限公司 Bidirectional trigger diode chip production method
CN101719507A (en) * 2009-09-28 2010-06-02 绍兴科盛电子有限公司 Single table surface series plane PN junction chip and manufacturing method thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104347731A (en) * 2013-08-08 2015-02-11 无锡华润华晶微电子有限公司 Diode structure
CN104362182A (en) * 2014-11-19 2015-02-18 桑德斯微电子器件(南京)有限公司 Planar double-knot type voltage stabilizing diode chip and producing process thereof
CN104362182B (en) * 2014-11-19 2017-04-05 桑德斯微电子器件(南京)有限公司 A kind of plane binode type Zener diode chip and its production technology
CN106653869A (en) * 2016-12-14 2017-05-10 丽晶美能(北京)电子技术有限公司 Power diode
CN117219677A (en) * 2023-10-11 2023-12-12 杭州致善微电子科技有限公司 Limiting diode with anode concentration gradient linear distribution and preparation method thereof
CN117219677B (en) * 2023-10-11 2024-02-23 杭州致善微电子科技有限公司 Limiting diode with anode concentration gradient linear distribution and preparation method thereof
CN118213372A (en) * 2024-05-21 2024-06-18 天水天光半导体有限责任公司 16-Bit transparent latch
CN118213372B (en) * 2024-05-21 2024-08-23 天水天光半导体有限责任公司 16-Bit transparent latch

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