CN101719507A - Single table surface series plane PN junction chip and manufacturing method thereof - Google Patents
Single table surface series plane PN junction chip and manufacturing method thereof Download PDFInfo
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- CN101719507A CN101719507A CN200910153023A CN200910153023A CN101719507A CN 101719507 A CN101719507 A CN 101719507A CN 200910153023 A CN200910153023 A CN 200910153023A CN 200910153023 A CN200910153023 A CN 200910153023A CN 101719507 A CN101719507 A CN 101719507A
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Abstract
The invention discloses a single table surface series plane PN junction chip and a manufacturing method thereof. The PN junction chip comprises a silicon substrate and series plane PN junctions, wherein the series plane PN junctions are directly or indirectly manufactured on the silicon substrate, a single table surface is arranged on the edges of the two PN junctions, and glass or CVD deposited films or other passivating materials are also covered on the side walls of the table surface. The manufacturing method comprises the following steps of: forming the series plane PN junctions on the silicon substrate; forming the single table surface, so that the series plane PN junctions are exposed on the side walls of the single table surface; respectively forming a passivating layer on the side walls of the single table surface, so that the PN junctions are isolated from the outside; and finishing surface metalation.
Description
Technical field
The present invention relates to a kind of manufacturing method of semiconductor device, especially relevant with mesa series plane PN junction chip and manufacture method thereof.
Background technology
The PN junction of making two incorgruous series connection on same chip has significance to forming needed device property.For example transistor is made of curved surface knot or+one planar junction of a curved surface knot of two series connection of process particular design, generally adopts planar technique or plane+mesa technique to realize; Then constitute for for example two-way transient voltage inhibition diode of some device and two-way trigger tube, generally realize passivation by each statement of account solely being done a table top by the planar junction of two series connection.Also there are some in encapsulation process, to realize surface passivation by the chip that the series plane structure becomes.But such chip can not be realized undersized surface-adhered type encapsulation, when the plane PN junction distance of two series connection is very near, each statement of account is solely done a table top realize that passivation will become very difficult and even may not.Yet such requirement is necessary for the electrical characteristics and the encapsulation characteristic that obtain chip exactly.On the other hand, the problem that the existing pair of table top wafer surveyed in also existing and being difficult to carry out automatically: for two table top wafers, need test respectively on the branch two sides during underway survey, therefore can't realize the full-automatic probe test of wafer.For solving the problem of passivation of biplane knot series connection chip, the invention provides the single table surface series plane PN junction chip manufacture method that relates to diffusion technology and passivation technology.
Summary of the invention
The purpose of this invention is to provide a kind of problem of passivation that solves plane series connection chip, and the single table surface series plane PN junction chip of surveying in can conveniently carrying out automatically.
Second purpose of the present invention provides a kind of manufacture method of above-mentioned single table surface series plane PN junction chip.
For reaching above-mentioned first purpose, the present invention is achieved by the following technical solutions:
A kind of single table surface series plane PN junction chip, comprise silicon chip, this silicon chip be one have first first type surface and with the substrate of this first first type surface opposite second major surface, on silicon chip, directly or indirectly be formed with first PN junction and second PN junction of series plane type.Wherein, first PN junction and the second PN junction edge are provided with single table surface, and these two PN junctions are exposed to same single table surface sidewall, are formed with passivation layer on the single table surface sidewall, and this passivation layer is implemented to seal completely to aforementioned first PN junction and second PN junction.
As the further setting to technique scheme, passivation layer is glass passivation layer or CVD deposited film.
Above-mentioned first PN junction and second PN junction are according to different positive-negative-positive or the NPN types of forming of the conduction type of silicon chip.
For reaching above-mentioned second purpose, the invention provides a kind of method of making single table surface series plane PN junction chip, may further comprise the steps:
A. mix second conductive-type impurity simultaneously on silicon chip first first type surface and the second first type surface two sides of first conduction type, this process realizes by the method for diffusion, this process forms second conductive type layer at silicon chip first first type surface and the second first type surface two sides, promptly forms the series connection PN junction;
B. silicon chip first first type surface is ground, make the distance on the surface after first PN junction grinds to silicon chip meet desired depth;
C. photoetching, corrosion are carried out in the surface after silicon chip grinds, and form single table surface, make two PN junctions all be exposed to the single table surface sidewall;
D. do one deck glass or CVD deposited film or other passivation layers at the single table surface sidewall, PN junction is isolated from the outside;
E. adopt the mode of nickel plating or evaporation to finish surface metalation.
In adopting the final series plane PN junction that forms of said method, in adopting the final series plane PN junction that forms of said method, surface after grinding apart from silicon chip is first PN junction far away relatively, itself and grind distance between the rear surface be less than its with silicon chip second first type surface between distance, second PN junction is between the surface after first PN junction and the grinding.
Perhaps, the another kind of method as making single table surface series plane PN junction chip may further comprise the steps:
A. in first first type surface extension one deck, second conductive type layer of the first conduction type silicon chip, form first PN junction;
B. the made epitaxial loayer that mixes high concentration in the epitaxial loayer extension aspect far away apart from silicon chip first first type surface becomes the impurity of the first lower conductive type layer of resistivity again, and this process realizes by the method for diffusion, forms second PN junction this moment;
C. carry out photoetching, corrosion in distance silicon chip first first type surface extension aspect far away, form single table surface, make two PN junctions all be exposed to the single table surface sidewall;
D. do one deck glass or CVD deposited film or other passivation layers at the single table surface sidewall, PN junction is isolated from the outside;
E. adopt the mode of nickel plating or evaporation to finish surface metalation.
In adopting the final series plane PN junction that forms of said method, apart from relative first PN junction far away of the extension aspect of silicon chip, distance between itself and the extension aspect is less than the distance between itself and silicon chip second first type surface, and second PN junction is between the extension aspect of first PN junction and silicon chip.
The present invention is owing to adopted technique scheme, compared with prior art have the following advantages: (one) has solved two table top wafers problem of middle survey automatically: for two table top wafers, need test respectively on the branch two sides during underway survey, therefore can't realize the full-automatic probe test of wafer., at wafer polar switching and testing time only need be set in automatically during survey and can finish wafer sort under the situation at turn-over not owing to adopted the single table surface Modeling Technology for the present invention; (2) can realize full-automatic operation: test, get ready for two table top wafer sort time-division faces, when manipulator was got material, the figure of getting ready that is positioned at the crystal grain back side can't be by machine recognition, and therefore two table top wafers can't be realized full-automatic operation., test, get ready all and can finish owing to have only single table surface for the present invention, therefore can realize full-automatic operation in one side; Adopt single face photoetching, corroding method during (three) for two series plane PN junction close together, it is simple to operate, and mesa technique realizes that easily rate of finished products is higher.
Description of drawings
Fig. 1 is the two table top series plane PN junction chip side-looking structural representations of existing NPN type;
Fig. 2 a is that NPN type series plane PN junction of the present invention adopts diffusion way forming process schematic diagram;
Fig. 2 b is that NPN type series plane PN junction of the present invention adopts extension+diffusion way forming process schematic diagram;
Fig. 3 is NPN type single table surface series plane PN junction chip table top of the present invention and passivation forming process schematic diagram.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are described in further detail.
Embodiment 1: as Fig. 2 a and shown in Figure 3, a kind of method of making single table surface series plane PN junction chip comprises: a. mixes second conductive-type impurity simultaneously on silicon chip 1 first first type surface 101 and second first type surface, 102 two sides of first conduction type, this process can realize by the method for diffusion, this process forms second conductive type layer at silicon chip 1 first first type surface 101 and second first type surface, 102 two sides, promptly form series plane PN junction 2 and 3, b. silicon chip 1 first first type surface 101 is ground, make the distance on the surface 103 after PN junction 2 grinds to silicon chip 1 meet desired depth, c. photoetching is carried out on the surface 103 after silicon chip 1 grinds, corrosion, form single table surface 4, make PN junction 2 and 3 all be exposed to single table surface 4 sidewalls, d. do one deck glass or CVD deposited film or other passivation layers 5 at single table surface 4 sidewalls, PN junction 2 and 3 is isolated from the outside, and e. adopts the mode of nickel plating or evaporation to finish surface metalation.
Embodiment 2: as Fig. 2 b and shown in Figure 3, a kind of method of making single table surface series plane PN junction chip comprises: a. is in first first type surface, 101 extension one decks, second conductive type layer 201 of the first conduction type silicon chip 1, form single plane PN junction 2, b. the made epitaxial loayer 201 that mixes high concentration apart from silicon chip 1 first first type surface 101 extension aspects 202 far away at epitaxial loayer 201 becomes the impurity of the first lower conductive type layer of resistivity again, this process can realize by the method for diffusion, form another plane PN junction 3 this moment, c. carry out photoetching in distance silicon chip 1 first first type surface 101 extension aspects 202 far away, corrosion, form single table surface 4, make PN junction 2 and 3 all be exposed to single table surface 4 sidewalls, d. do one deck glass or CVD deposited film or other passivation layers 5 at single table surface 4 sidewalls, PN junction 2 and 3 is isolated from the outside, and e. adopts the mode of nickel plating or evaporation to finish surface metalation.
More than two kinds of methods can finish single table surface series plane PN junction chip of the present invention, as shown in Figures 2 and 3, adopt the method for embodiment 1, in the final series plane PN junction that forms, surface (103) after grinding apart from silicon chip (1) is first PN junction (2) far away relatively, itself and grind distance between the rear surface (103) be less than its with silicon chip (1) second first type surface (102) between distance, second PN junction (3) is positioned between the surface (103) after first PN junction (2) and the grinding.
Adopt the method for embodiment 2, in the final series plane PN junction that forms, apart from relative first PN junction (2) far away of the extension aspect (202) of silicon chip (1), distance between itself and the extension aspect (202) is less than the distance between itself and silicon chip (1) second first type surface (102), and second PN junction (3) is positioned between the extension aspect (202) of first PN junction (2) and silicon chip (1).
More than the present invention has been done detailed description, can not think that protection scope of the present invention only is confined to above-mentioned execution mode.If do not have to produce in essence difference, the deduction or replace of above-mentioned execution mode still are regarded as within protection scope of the present invention with the technical scheme of claim of the present invention.
Claims (7)
1. single table surface series plane PN junction chip, comprise silicon chip (1), described silicon chip (1), be one have first first type surface (101) and with the substrate of described first first type surface (101) opposite second major surface (102), on described silicon chip (1), directly or indirectly be formed with first PN junction (2) and second PN junction (3) of series plane type, it is characterized in that described first PN junction (2) and second PN junction (3) edge are provided with single table surface (4), first PN junction (2) and second PN junction (3) all are exposed to same single table surface (4) sidewall, be formed with passivation layer (5) on single table surface (4) sidewall, this passivation layer is implemented to seal completely to aforementioned two PN junctions.
2. according to the described single table surface series plane PN junction chip of claim 1, it is characterized in that: described passivation layer is glass passivation layer or CVD deposited film.
3. according to claim 1 or 2 described single table surface series plane PN junction chips, it is characterized in that: described first PN junction (2) and second PN junction (3) are according to different positive-negative-positive or the NPN types of forming of the conduction type of silicon chip (1).
4. method of making single table surface series plane PN junction chip is characterized in that may further comprise the steps:
A. mix second conductive-type impurity simultaneously on silicon chip (1) first first type surface (101) and second first type surface (102) two sides of first conduction type, this process realizes by the method for diffusion, this process forms second conductive type layer at silicon chip (1) first first type surface (101) and second first type surface (102) two sides, promptly forms series connection PN junction (2) and (3);
B. silicon chip (1) first first type surface (101) face is ground, make the distance on the surface (103) after first PN junction (2) grinds to silicon chip (1) meet desired depth;
C. photoetching, corrosion are carried out in the surface (103) after silicon chip (1) grinds, and form single table surface (4), make PN junction (2) and (3) all be exposed to single table surface (4) sidewall;
D. do one deck glass or CVD deposited film or other passivation layers (5) at single table surface (4) sidewall, PN junction (2) and (3) are isolated from the outside;
E. adopt the mode of nickel plating or evaporation to finish surface metalation.
5. according to the method for the described making single table surface series plane PN junction chip of claim 4, it is characterized in that: in the final series plane PN junction that forms, surface (103) after grinding apart from silicon chip (1) is first PN junction (2) far away relatively, itself and grind distance between the rear surface (103) be less than its with silicon chip (1) second first type surface (102) between distance, second PN junction (3) is positioned between the surface (103) after first PN junction (2) and the grinding.
6. method of making single table surface series plane PN junction chip is characterized in that may further comprise the steps:
A. in first first type surface (101) face extension one deck second conductive type layer (201) of the first conduction type silicon chip (1), form first PN junction (2);
B. the made epitaxial loayer (201) that mixes high concentration apart from silicon chip (1) first first type surface (101) extension aspect (202) far away at epitaxial loayer (201) becomes the impurity of the first lower conductive type layer of resistivity again, this process realizes by the method for diffusion, forms second PN junction (3) this moment;
C. carry out photoetching, corrosion in distance silicon chip (1) first first type surface (101) extension aspect (202) far away, form single table surface (4), make PN junction (2) and (3) all be exposed to single table surface (4) sidewall;
D. do one deck glass or CVD deposited film or other passivation layers (5) at single table surface (4) sidewall, PN junction (2) and (3) are isolated from the outside;
E. adopt the mode of nickel plating or evaporation to finish surface metalation.
7. according to the method for the described making single table surface series plane PN junction chip of claim 6, it is characterized in that: in the final series plane PN junction that forms, apart from relative first PN junction (2) far away of the extension aspect (202) of silicon chip (1), distance between itself and the extension aspect (202) is less than the distance between itself and silicon chip (1) second first type surface (102), and second PN junction (3) is positioned between the extension aspect (202) of first PN junction (2) and silicon chip (1).
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102412268A (en) * | 2011-12-06 | 2012-04-11 | 绍兴旭昌科技企业有限公司 | Flat-type one-way trigger diode chip and manufacturing method thereof |
| CN102437199A (en) * | 2011-12-06 | 2012-05-02 | 绍兴旭昌科技企业有限公司 | Table-board type unidirectional negative resistance diode chip and manufacturing method thereof |
| CN102760774A (en) * | 2012-07-04 | 2012-10-31 | 王萌 | High-voltage trigger tube and triggering circuit for both stove oven and metal halogen lamp |
| CN103887167A (en) * | 2014-04-16 | 2014-06-25 | 株洲南车时代电气股份有限公司 | Method for passivating mesa of semiconductor chip |
| CN111256858A (en) * | 2020-04-01 | 2020-06-09 | 北京工业大学 | High-precision contact type temperature measuring method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1298029C (en) * | 2003-03-26 | 2007-01-31 | 中国电子科技集团公司第五十五研究所 | RF desk-top silicon diode electrophoretic depositional glass conformal passivation film manufacture |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412268A (en) * | 2011-12-06 | 2012-04-11 | 绍兴旭昌科技企业有限公司 | Flat-type one-way trigger diode chip and manufacturing method thereof |
| CN102437199A (en) * | 2011-12-06 | 2012-05-02 | 绍兴旭昌科技企业有限公司 | Table-board type unidirectional negative resistance diode chip and manufacturing method thereof |
| CN102760774A (en) * | 2012-07-04 | 2012-10-31 | 王萌 | High-voltage trigger tube and triggering circuit for both stove oven and metal halogen lamp |
| CN102760774B (en) * | 2012-07-04 | 2014-11-26 | 王萌 | High-voltage trigger tube and triggering circuit for both stove oven and metal halogen lamp |
| CN103887167A (en) * | 2014-04-16 | 2014-06-25 | 株洲南车时代电气股份有限公司 | Method for passivating mesa of semiconductor chip |
| CN111256858A (en) * | 2020-04-01 | 2020-06-09 | 北京工业大学 | High-precision contact type temperature measuring method |
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Effective date of registration: 20181023 Address after: 312300 Longshan Software Park, Shaoxing Economic Development Zone, Yuecheng District, Shaoxing, Zhejiang Patentee after: ZHEJIANG MINGDE MICROELECTRONIC CO., LTD. Address before: 312000 Zhejiang science and technology building, 683 Shun Jiang Road, Shaoxing, China (2301-2306) Patentee before: Shaoxing Kesheng Electronic Co., Ltd. |
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