CN103887167A - Method for passivating mesa of semiconductor chip - Google Patents
Method for passivating mesa of semiconductor chip Download PDFInfo
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- CN103887167A CN103887167A CN201410153442.XA CN201410153442A CN103887167A CN 103887167 A CN103887167 A CN 103887167A CN 201410153442 A CN201410153442 A CN 201410153442A CN 103887167 A CN103887167 A CN 103887167A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 154
- 238000000034 method Methods 0.000 title claims abstract description 56
- 239000000376 reactant Substances 0.000 claims abstract description 30
- 238000000465 moulding Methods 0.000 claims description 69
- 239000007789 gas Substances 0.000 claims description 38
- 238000002161 passivation Methods 0.000 claims description 31
- 229910003460 diamond Inorganic materials 0.000 claims description 30
- 239000010432 diamond Substances 0.000 claims description 30
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 27
- 229910052799 carbon Inorganic materials 0.000 claims description 26
- 238000001020 plasma etching Methods 0.000 claims description 26
- 230000000694 effects Effects 0.000 claims description 14
- 239000011261 inert gas Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 32
- 239000000463 material Substances 0.000 description 11
- 238000000151 deposition Methods 0.000 description 10
- 230000008021 deposition Effects 0.000 description 7
- 239000000126 substance Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000007774 longterm Effects 0.000 description 4
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- RLLPVAHGXHCWKJ-IEBWSBKVSA-N (3-phenoxyphenyl)methyl (1s,3s)-3-(2,2-dichloroethenyl)-2,2-dimethylcyclopropane-1-carboxylate Chemical compound CC1(C)[C@H](C=C(Cl)Cl)[C@@H]1C(=O)OCC1=CC=CC(OC=2C=CC=CC=2)=C1 RLLPVAHGXHCWKJ-IEBWSBKVSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001721 carbon Chemical group 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920003055 poly(ester-imide) Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
The invention provides a method for passivating a mesa of a semiconductor chip. The method comprises the steps that the semiconductor chip with a preset mesa model is placed into a reaction chamber for etching a reactive plasma, and the non-mesa area of the semiconductor chip is covered so that only the mesa area of the semiconductor chip can be exposed; reactant gas CH4 is fed into the reaction chamber, and carries out glow discharge under the action of the power of a radio frequency source to generate the plasma; the plasma deposits a diamond-like film on the mesa of the semiconductor chip so that a passivating layer can be formed. The method for passivating the mesa of the semiconductor chip has the advantages of being high in efficiency, good in uniformity, high in repeatability, high in flexibility and low in labor cost.
Description
Technical field
The present invention relates to field of semiconductor devices, relate in particular to a kind of passivating method of semiconductor chip table top.
Background technology
In high-voltage power semiconductor device, determine that this device voltage height also depends on surface treatment except its internal structure parameter, reduce surface field, raising surface withstand voltage, make it higher than body withstand voltage be a very important job.
In order to improve PN junction surface breakdown voltage, reduce surface field intensity, tube core need to carry out moulding, makes surface have a rational shape.In the moulding of high voltage junction terminal, what employing was the widest at present is table top (inclined-plane) Modeling Technology.Common table top moulding has positive negative bevel moulding, two-sided negative bevel moulding, two-sided orthogonal rake moulding.
Because the table top after tube core moulding is exposed to outside, so its surface is easy to adsorb one deck ion, and is easy to be polluted by objectionable impurities, thereby cause tracking current to strengthen.Because there is very large relation on adion and surface with external condition; the tube core performance that surface does not add protection is unsettled; particularly in alive situation; under the effect of electric field; impurity in surrounding environment is more easily adsorbed in die surfaces and causes leakage current sharply to strengthen, and blocking voltage reduces.So, in order to improve the reliability and stability of element, need to carry out Passivation Treatment to moulding surface, make it all present a kind of stable state to chemistry and electrical property aspect.
And in passivation technology for these table top moulding, adopting the widest passivating method is at present soft passivating method.The passivating material that soft passivating method adopts is generally liquid polyester-imide (SU) or polyimides (PI).This passivating method conventionally needs artificial use writing brush dipping or with syringe coating, then at not higher than 300 DEG C of temperature, is cured.
Because this method is to operate manually the stability that is difficult to ensure mesa passivation layer quality.The passivating material that simultaneously soft passivating method adopts has extremely strong penetrating odor, contaminated environment, and larger to harm.
And the passivating material that this passivating method adopts is very easily introduced bubble in coating procedure, after hot setting, the air release in bubble, makes passivating material occur contracting glue phenomenon like this.This processing of just need to doing over again, has reduced operating efficiency.And the very easily moisture absorption of this passivating material, and easily aging, thus cause leakage current to increase, cause the long-term reliability problems of device.
Summary of the invention
In view of this, the problem of bringing in order to solve above-mentioned soft passivating method, the invention provides a kind of passivating method of semiconductor chip table top.
In order to solve the problems of the technologies described above, the present invention has adopted following technical scheme:
A passivating method for semiconductor chip table top, comprises,
The semiconductor chip that is provided with predetermined table top moulding is inserted in the reative cell of reactive plasma etching, and block the non-mesa region of described semiconductor chip, only to make outside the mesa region of described semiconductor chip is exposed to;
In described reative cell, pass into reactant gas CH
4, described reactant gas CH
4under the effect of radio frequency source power, glow discharge produces plasma;
Described plasma is deposit one deck diamond like carbon film on the table top of described semiconductor chip, to form passivation layer.
Preferably, in described reative cell of the semiconductor chip that is provided with predetermined table top moulding being inserted to reactive plasma etching after, describedly in described reative cell, pass into reactant gas CH
4, also comprise before,
In described reative cell, pass into inert gas, to clean the mesa region of described semiconductor chip.
Preferably, in described reative cell of the semiconductor chip that is provided with predetermined table top moulding being inserted to reactive plasma etching before, also comprise,
Adopt oxygen plasma to clean described reative cell.
Preferably, described reactant gas also comprises H
2.
Preferably, in described reative cell of the semiconductor chip that is provided with predetermined table top moulding being inserted to reactive plasma etching before, also comprise,
Described semiconductor chip is placed in the frock matching with described predetermined table top moulding, described in match after described semiconductor chip is placed in described frock, described frock can hide the non-mesa region of described semiconductor chip;
In described reative cell of the semiconductor chip that is provided with predetermined table top moulding being inserted to reactive plasma etching, be specially,
The semiconductor chip that is provided with predetermined table top moulding is inserted in the reative cell of reactive plasma etching together with described frock.
Preferably, it is unsettled that the frock that described and described predetermined table top moulding matches can make to be placed on described semiconductor chip in described frock.
Preferably, described frock comprises bearing, and described bearing is rounding bench-type bearing.
Preferably, described predetermined table top is shaped to two-sided negative bevel moulding, and described two-sided negative bevel moulding comprises the first table top and the second table top,
In described reative cell of the semiconductor chip that is provided with predetermined table top moulding being inserted to reactive plasma etching, be specially, the semiconductor chip that is provided with predetermined table top moulding inserted in the reative cell of reactive plasma etching, described First is faced up;
Described plasma is deposit one deck diamond like carbon film on the table top of described semiconductor chip, is specially, and described plasma is deposit one deck diamond like carbon film on the first table top of described semiconductor chip;
Described plasma after deposit one deck diamond like carbon film, also comprises on the first table top of described semiconductor chip,
Described semiconductor chip is taken out in the reative cell of described reactive plasma etching;
Change the placing direction of described semiconductor chip, again described semiconductor chip is placed in described reative cell according to the placing direction after changing, make described the second table top upward;
In described reative cell, again pass into reactant gas CH
4, described reactant gas CH
4under the effect of radio frequency source power, glow discharge produces plasma;
Described plasma is deposited diamond film on the second table top of described semiconductor chip.
Preferably, described reactant gas CH
4gas flow be 250sccm.
Preferably, the chamber pressure in described reative cell is 150mTorr.
The present invention has following beneficial effect:
The passivating method of semiconductor chip table top provided by the invention, based on reactive plasma etching (RIE, reactive ion etch) principle, by the reactant gas methane CH passing in reative cell
4under the effect of radio frequency source power, glow discharge produces plasma, and the plasma of generation is in mesa region deposit one deck diamond like carbon film of semiconductor chip.The passivating method of this semiconductor chip table top completing by reactive plasma equipment, the technological parameter while deposition by control is consistent, just can ensure the stability of the passivation layer quality of deposit.And the diamond like carbon film forming by passivating method provided by the invention is rigid passivating material, can realize free of pinholes and the agranular requirement of passivation layer, reduce rework rate, thereby improved operating efficiency.
Simultaneously, the diamond like carbon film forming by passivating method provided by the invention has that hardness is high, coefficient of friction is low, resistivity is high, electrical insulating property and the high performance of thermal conductivity, there is good chemical stability and corrosion resistance simultaneously, therefore, can greatly improve the long-term reliability of semiconductor chip and device.
In addition, the diamond like carbon film forming by passivating method provided by the invention does not have smell, can not work the mischief to environment and human body.
Brief description of the drawings
In order to be expressly understood the specific embodiment of the present invention, the accompanying drawing that need to use during below to description embodiment is briefly described.Apparently, these accompanying drawings are only a part of accompanying drawings of the embodiment of the present invention, and those of ordinary skill in the art, not paying under the prerequisite of creative work, can also obtain other accompanying drawing.
Fig. 1 is the principle schematic of plasma etching;
Fig. 2 is the passivating method schematic flow sheet of the semiconductor chip table top that provides of the embodiment of the present invention;
Fig. 3 (1) to Fig. 3 (3) be the cross-sectional view of semiconductor chip table top moulding;
Fig. 4 (1) to Fig. 4 (3) be the chip of varying mesa moulding and the placement location schematic diagram of frock;
Fig. 5 (1) to Fig. 5 (3) be the chip of the varying mesa moulding position view in reative cell;
Fig. 6 is the cross-sectional view of the semiconductor chip table top moulding of carrying out twice deposit that provides of the embodiment of the present invention.
Embodiment
In order to be expressly understood the embodiment of passivating method of semiconductor chip table top provided by the invention, be elaborated below in conjunction with accompanying drawing.
First introduce the formation principle of plasma in conjunction with Fig. 1.Reactive plasma etching system comprises reative cell, comprises upper and lower pair of electrodes in reative cell.While carrying out plasma etching, substrate to be etched is placed on bottom electrode, etching gas is injected into reative cell by the air inlet of the spray hair style of top electrode, under the effect of RF radio frequency source, in reative cell, form uniform plasma, plasma moves to substrate surface substrate is carried out to etching.
The above-mentioned etching gas passing into is replaced with to reactant gas, and the glow discharge under the effect of radio frequency source power of this reactant gas produces reactive plasma, and this reactive plasma can be deposited on the surface of substrate, thereby deposit forms thin film.
The passivating method of semiconductor chip table top provided by the invention adopts above-mentioned principle to complete exactly.
Fig. 2 shows the schematic flow sheet of the passivating method of semiconductor chip table top provided by the invention.As shown in Figure 3, the passivating method of semiconductor chip table top provided by the invention comprises the following steps:
S201, the semiconductor chip that is provided with predetermined table top moulding is inserted in the reative cell of reactive plasma etching, and block the non-mesa region of described semiconductor chip, only to make outside the mesa region of described semiconductor chip is exposed to:
The semiconductor chip that is provided with predetermined table top moulding is inserted on the carrier in the reative cell of reactive plasma etching, and the non-mesa region of blocking described semiconductor chip with catch, only to make outside the mesa region of semiconductor chip is exposed to.It should be noted that, described carrier is positioned on bottom electrode.
It should be noted that, semiconductor chip surface region comprises mesa region and non-mesa region.In order to keep the reliability and stability of semiconductor chip, only need to carry out Passivation Treatment in the mesa region of semiconductor chip.So, in order to prevent passivation layer in non-mesa region deposit, before carrying out deposit, the non-mesa region of semiconductor chip need to be covered up, only make outside the mesa region of semiconductor chip is exposed to.
S202, off-response chamber upper cover, extract the gas in reative cell, makes it become vacuum state:
It should be noted that, extract after gas, the pressure in described reative cell is preferably 150mTorr.
S203, open RF radio frequency source, in reative cell, pass into reactant gas CH
4, described reactant gas CH
4under the effect of radio frequency source power, glow discharge produces plasma:
In reative cell, pass into reactant gas CH by the spray hair style air inlet on top electrode
4, described reactant gas CH
4under the effect of radio frequency source power, glow discharge produces plasma.Thereby in reative cell, form plasma atmosphere.
Wherein, reactant gas CH
4gas flow be preferably 250sccm.In addition, described reactant gas is except methane CH
4in addition, can also comprise H
2, reactant gas is CH
4and H
2.When reactant gas comprises H
2time, the content of the hydrogen in the diamond like carbon film of generation can increase, and hydrogen content is higher, and the resistivity of film is higher, and therefore the passivation effect of film is better.
It should be noted that, during due to reactant gas glow discharge, can produce heat, temperature in reative cell can raise gradually, thereby, for ensure deposition film carry out smoothly and in order to ensure the quality of deposition film, in deposition process, in order to reduce the temperature in reative cell, be conducive to the deposition of plasma, can realize by the method for cooling bottom electrode.
S204, described plasma be deposit one deck diamond like carbon film on the table top of described semiconductor chip, to form passivation layer.
Because semiconductor chip is placed on the carrier in reative cell, the plasma producing is moved in the effect of electric field on the surface of the semiconductor chip on carrier, thereby the mesa region of the semiconductor chip outside being exposed to is deposited as one deck diamond like carbon film, thereby form passivation layer in the mesa region of semiconductor chip.
Described diamond like carbon film is a kind of with sp
3and sp
2the form of key, in conjunction with the metastable material generating, has had the good characteristic of diamond and graphite concurrently, and has had high rigidity, high resistivity, favorable optical performance and outstanding tribological property.
The diamond like carbon film DLC film that is conventionally otherwise known as, is the abbreviation of english vocabulary Diamond Like Carbon, and it does not have strict definition, can comprise the amorphous carbon of very wide property ranges, has therefore had the good characteristic of diamond and graphite concurrently; So the DLC film being come by diamond like carbon is the unordered non-crystalline material of a kind of metastable state long-range equally, the bonding mode between carbon atom is covalent bond, mainly comprises sp
2and sp
3two kinds of hybrid bonds, and in hydrogeneous DLC film, also there is the c h bond of some.
Due to the good characteristic of diamond like carbon film, as high in hardness, coefficient of friction is low, resistivity is high, electrical insulating property and thermal conductivity high, there is good chemical stability and corrosion resistance simultaneously, therefore can greatly improve the long-term reliability of semiconductor device.
Meanwhile, because the hydrogenation surface of this diamond like carbon film is by negatron compatibility and chemical inertness, relatively low effective work function and energy gap.Meanwhile, the electron emission of diamond like carbon film has advantages of that threshold field is low, emission current stable, does not pollute other components and parts.
Be more than the passivating method embodiment of semiconductor chip table top provided by the invention.The passivating method of semiconductor chip table top provided by the invention is based on RIE principle, by reactant gas CH
4under the effect of radio frequency source, be dissociated into plasma, be then deposited on the mesa region of semiconductor chip, thereby formed passivation layer in the mesa region of semiconductor chip.Compared to the passivating method by artificial coating table top in prior art, passivating method provided by the invention has been saved manpower.And can realize the stability of multiple batches of passivation layer quality by controlling technological parameter, thereby compared to prior art, passivating method provided by the invention also can ensure the stability of the passivation layer quality of semiconductor chip mesa region.
In addition, because plasma forms approximate uniform plasma atmosphere in reative cell, the uniformity of passivation layer that is therefore deposited on semiconductor chip mesa region is also higher.And due to the diffusivity of plasma, so the passivation layer forming by passivating method provided by the invention can cover whole mesa region, thereby ensure that passivation layer covers the integrality of mesa region.
In addition, the material of passivation layer that the present invention forms is diamond like carbon film, and it is hard material, thereby has overcome soft passivating material and easily produce the defect of bubble, thereby has also just reduced rework rate.
In addition, by passivating method provided by the invention, multiple semiconductor chips can be placed into simultaneously in reative cell, carry out mesa passivation, in other words, passivating method provided by the invention can be realized the once batch passivation to multiple chips, thereby passivating method provided by the invention has improved operating efficiency.
In addition, the diamond like carbon film that the present invention forms is that one does not have material odorous, and environmental and human health impacts is safe from harm.
Test shows, the efficiency of the deposition film of the passivating method described in the embodiment of the present invention is high, the thickness of its deposition film per minute can be greater than 45nm, and the uniformity of deposition film is better, the thickness difference of the passivation layer of its zones of different is less than ± and 5%, and the repeatability of this passivating method is high, the performance error of the film of different batches passivation is less than ± and 3%.
As another embodiment of the present invention, pollution-free in order to ensure the mesa region of semiconductor chip, after above-mentioned steps S202, before step S203, can also comprise step, in reative cell, pass into inert gas.Thereby the mesa region of semiconductor chip is carried out to backwash cleaning, and then ensure the definitely pollution-free of mesa region, thereby improve the long-term reliability of device.Described inert gas can be argon gas.
In addition, if reative cell had been utilized before, reative cell is not brand-new, may be stained with some accessory substances so on the inwall of reactor chamber, and these accessory substances are in use procedure before, on the inwall of the cavity of reative cell, adheres to.In order to remove these accessory substances, ensure the clean of semiconductor chip mesa region, before semiconductor chip is inserted to reative cell,, before step S201, can also comprise the step that adopts oxygen plasma to clean reative cell.The accessory substance sticking on cavity inner wall can be etched away by this step.
It should be noted that, above-described embodiment is directly placed on semiconductor chip on the carrier in reative cell, in fact, also can in advance semiconductor chip be placed in frock, then semiconductor chip be placed in reative cell according to original modes of emplacement together with frock.It should be noted that, described frock will match with the table top moulding of semiconductor chip.What is called matches, and exactly after semiconductor chip is placed in frock, described frock can hide the non-mesa region of semiconductor chip.Frock described in the present embodiment can comprise bearing and catch two parts.Described bearing and catch can cover up all non-mesa region of chip.
Under normal circumstances, semiconductor chip comprises front, the back side and side, and described mesa region can be positioned at front, the back side and/or side.The table top moulding of junction of semiconductor device terminal at present has three kinds: positive negative bevel moulding (as shown in Fig. 3 (1)), two-sided negative bevel moulding are (as Fig. 3 (2), two-sided orthogonal rake moulding (as Fig. 3 (3)).Wherein, positive negative bevel banker face is positioned on the front of semiconductor chip or a surface at the back side, and two-sided negative bevel moulding table top is positioned on two surfaces of front and back of semiconductor chip, and two-sided orthogonal rake moulding table top is positioned at the side of semiconductor chip.
In the time that table top is shaped to positive negative bevel moulding, if when mesa region is positioned at front, surface configuration and the consistent size at the surface configuration of bearing and size and the semiconductor chip back side.Like this, after semiconductor chip is placed in frock, the back side can be hidden by bearing, is positioned at positive non-mesa region and is blocked by catch.If when mesa region is positioned at the back side, surface configuration and the consistent size in the surface configuration of bearing and size and semiconductor chip front.Like this, after semiconductor chip is placed in frock, front can be hidden by bearing, and the non-mesa region that is positioned at the back side is blocked by catch, thereby only makes outside mesa region is exposed to.
In the time that table top is shaped to positive negative bevel moulding, bearing can be a flat board or platform, after the semiconductor chip that table top is shaped to positive negative bevel moulding is placed on bearing, the chip surface that is not provided with mesa region contacts with bearing, and the surface that is provided with mesa region upward, and non-mesa region covers with catch, only have outside mesa region is exposed to, the position relationship of its placement is as shown in Fig. 4 (1).It should be noted that, in the time semiconductor chip being inserted together with frock in reative cell, semiconductor chip and placement location relation in frock with do not insert before placement location relation identical, the chip that table top is shaped to positive negative bevel moulding at the schematic diagram in reactor chamber as shown in Fig. 5 (1).That is to say, be placed to semiconductor chip in reative cell and the position relationship of frock and be: semiconductor chip is placed on bearing, and its semiconductor chip non-mesa region upward hides with catch to only have outside mesa region is exposed to.
In the time that table top is shaped to two-sided negative bevel moulding, shape and the consistent size of a surperficial non-mesa region in the surface configuration of bearing and size and semiconductor chip front, the back side.Like this, after semiconductor chip is placed in frock, the non-mesa region on one of them surface can be hidden by bearing, and the lip-deep non-mesa region of another one is blocked by catch, and outside mesa region is exposed to.
In the time that table top is shaped to two-sided orthogonal rake moulding, shape and the consistent size at the surface configuration of bearing and size and semiconductor chip front or the back side.Like this, after semiconductor chip is placed in frock, one of them surface is hidden by bearing, and another one surface is blocked by catch, outside the mesa region that is positioned at side is exposed to.
Outside this mesa region of only having semiconductor chip is exposed to, but not the modes of emplacement of the chip that mesa region is hidden by bearing and frock, in follow-up passivating process, only passivation layer in the mesa region deposit of semiconductor chip, and on non-mesa region is not deposited passivation layer.
It should be noted that, in the time that table top is shaped to two-sided negative bevel moulding, mesa region comprises two parts, its be positioned at semiconductor chip just, the back of the body two surfaces on, in the time that table top is shaped to two-sided orthogonal rake moulding, mesa region is positioned at the side of semiconductor chip.In the time that table top is shaped to this two kinds of moulding, if realize depositing technics to the object of passivation layer uniformly in two of table top moulding equal deposits of face, except requiring frock can hide all non-mesa region of chip, described bearing can also make the semiconductor chip that is placed on it unsettled, thereby can be basically identical in the concentration of the diverse location of mesa region at deposition process applying plasma, thereby can on two of a table top moulding face, can form uniform passivation layer.It should be noted that, unsettled described in the embodiment of the present invention be semiconductor chip all mesa region not with any object contact, only contact with a lip-deep non-mesa region of semiconductor chip for the bearing that supports described semiconductor chip.And preferably, described bearing has certain height, semiconductor chip can be placed into bearing time, can reach a certain height, thereby when semiconductor chip and bearing are in a certain atmosphere, the mesa region that can make semiconductor chip gas concentration is around even.
In order to realize this object, described bearing is preferably rounding bench-type bearing, and the shape and size of the maximized surface of this round platform are identical with the shape and size of the non-mesa region of the semiconductor chip contacting with bearing being placed on it.After semiconductor chip is placed on bearing like this, non-mesa region can be blocked, and can make the chip can be unsettled, in passivating process, the passivation layer forming on two table tops can be more even like this.
In the time that bearing is rounding bench-type bearing, after the semiconductor chip that table top is shaped to two-sided negative bevel moulding is placed on bearing, bearing blocks one of semiconductor chip lip-deep non-mesa region, the lip-deep non-mesa region of chip another one is blocked with catch, outside remaining mesa region is exposed to, the position relationship of its placement is as shown in Fig. 4 (2).Chip with the just table top moulding of negative bevel moulding is identical, placement relation in the time that the semiconductor chip of two-sided negative bevel moulding is placed in reative cell together with frock keeps original placement location relation constant, the semiconductor chip that table top is shaped to two-sided negative bevel moulding at the schematic diagram in reactor chamber as shown in Fig. 5 (2).
In the time that bearing is rounding bench-type bearing, after the semiconductor chip that table top is shaped to two-sided orthogonal rake moulding is placed on bearing, bearing blocks a surface of semiconductor chip, block with catch on chip another one surface, outside its mesa region that is positioned at side is exposed to, the position relationship of its placement is as shown in Fig. 4 (3).Chip with the just table top moulding of negative bevel moulding is identical, placement relation in the time that the semiconductor chip of two-sided orthogonal rake moulding is placed in reative cell together with frock keeps original placement location relation constant, the semiconductor chip that table top is shaped to two-sided orthogonal rake moulding at the schematic diagram in reactor chamber as shown in Fig. 5 (3).
Except rounding bench-type bearing, described bearing can be also the supporting surface being supported by elongated stanchions, and the shape and size of this supporting surface are identical with the shape and size of the non-mesa region of semiconductor chip.
It should be noted that, in a frock, can comprise multiple bearings, thereby semiconductor chip one by one can be placed on different bearings, and then the non-mesa region of semiconductor chip is one by one blocked with catch one by one, then together frock and semiconductor chip are placed in reative cell, thereby can realize once, the mesa region of multiple chips are carried out to the object of deposit in batches.
In addition, when table top is shaped to two-sided negative bevel moulding, also can not adopt and can make the unsettled bearing of chip complete the deposit to upper and lower two mesa region, replace, adopt twice depositing technics to carry out passivation to mesa region.Detailed process is as follows:
For convenience of description, the mesa region that is shaped to two-sided negative bevel moulding is divided into two parts: the first table top and the second table top.Described the first table top and the second table top lay respectively at upper and lower two surfaces of semiconductor chip.
Definition executes above-mentioned steps S201 to step S204, has completed deposit and passivation to the first mesa region.As shown in Figure 6, after step S204,
Further comprising the steps of:
S605, described semiconductor chip is taken out in reative cell.
The placing direction of S606, change semiconductor chip, is placed on semiconductor chip on the carrier of reative cell again according to the placing direction after changing, and makes the second table top upward.
S607, in reative cell, again pass into reactant gas CH
4, described reactant gas CH
4under the effect of radio frequency source power, glow discharge produces plasma.
It should be noted that, in order to ensure that the first table top is identical with the thickness of the diamond like carbon film of deposit on the second table top, the process conditions of step S607 are identical with the process conditions of step S203.
S608, described plasma deposited diamond film on the second table top of semiconductor chip.
By above-mentioned twice depositing technics, can realize the passivation on two table tops of two-sided negative bevel.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (10)
1. a passivating method for semiconductor chip table top, is characterized in that, comprise,
The semiconductor chip that is provided with predetermined table top moulding is inserted in the reative cell of reactive plasma etching, and block the non-mesa region of described semiconductor chip, only to make outside the mesa region of described semiconductor chip is exposed to;
In described reative cell, pass into reactant gas CH
4, described reactant gas CH
4under the effect of radio frequency source power, glow discharge produces plasma;
Described plasma is deposit one deck diamond like carbon film on the table top of described semiconductor chip, to form passivation layer.
2. passivating method according to claim 1, is characterized in that, in described reative cell of the semiconductor chip that is provided with predetermined table top moulding being inserted to reactive plasma etching after, describedly in described reative cell, pass into reactant gas CH
4, also comprise before,
In described reative cell, pass into inert gas, to clean the mesa region of described semiconductor chip.
3. passivating method according to claim 1, is characterized in that, in described reative cell of the semiconductor chip that is provided with predetermined table top moulding being inserted to reactive plasma etching before, also comprise,
Adopt oxygen plasma to clean described reative cell.
4. passivating method according to claim 1, is characterized in that, described reactant gas also comprises H
2.
5. according to the passivating method described in claim 1-4 any one, it is characterized in that, in described reative cell of the semiconductor chip that is provided with predetermined table top moulding being inserted to reactive plasma etching before, also comprise,
Described semiconductor chip is placed in the frock matching with described predetermined table top moulding, described in match after described semiconductor chip is placed in described frock, described frock can hide the non-mesa region of described semiconductor chip;
In described reative cell of the semiconductor chip that is provided with predetermined table top moulding being inserted to reactive plasma etching, be specially,
The semiconductor chip that is provided with predetermined table top moulding is inserted in the reative cell of reactive plasma etching together with described frock.
6. passivating method according to claim 5, is characterized in that, it is unsettled that the frock that described and described predetermined table top moulding matches can make to be placed on described semiconductor chip in described frock.
7. passivating method according to claim 6, is characterized in that, described frock comprises bearing, and described bearing is rounding bench-type bearing.
8. according to the passivating method described in claim 1-4 any one, it is characterized in that, described predetermined table top is shaped to two-sided negative bevel moulding, and described two-sided negative bevel moulding comprises the first table top and the second table top,
In described reative cell of the semiconductor chip that is provided with predetermined table top moulding being inserted to reactive plasma etching, be specially, the semiconductor chip that is provided with predetermined table top moulding inserted in the reative cell of reactive plasma etching, described First is faced up;
Described plasma is deposit one deck diamond like carbon film on the table top of described semiconductor chip, is specially, and described plasma is deposit one deck diamond like carbon film on the first table top of described semiconductor chip;
Described plasma after deposit one deck diamond like carbon film, also comprises on the first table top of described semiconductor chip,
Described semiconductor chip is taken out in the reative cell of described reactive plasma etching;
Change the placing direction of described semiconductor chip, again described semiconductor chip is placed in described reative cell according to the placing direction after changing, make described the second table top upward;
In described reative cell, again pass into reactant gas CH
4, described reactant gas CH
4under the effect of radio frequency source power, glow discharge produces plasma;
Described plasma is deposited diamond film on the second table top of described semiconductor chip.
9. according to the passivating method described in claim 1-4 any one, it is characterized in that described reactant gas CH
4gas flow be 250sccm.
10. according to the passivating method described in claim 1-4 any one, it is characterized in that, the chamber pressure in described reative cell is 150mTorr.
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