CN102437199B - Table-board type unidirectional negative resistance diode chip and manufacturing method thereof - Google Patents
Table-board type unidirectional negative resistance diode chip and manufacturing method thereof Download PDFInfo
- Publication number
- CN102437199B CN102437199B CN 201110400117 CN201110400117A CN102437199B CN 102437199 B CN102437199 B CN 102437199B CN 201110400117 CN201110400117 CN 201110400117 CN 201110400117 A CN201110400117 A CN 201110400117A CN 102437199 B CN102437199 B CN 102437199B
- Authority
- CN
- China
- Prior art keywords
- junction
- diffusion layer
- silicon chip
- impurity concentration
- boss
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a table-board type unidirectional negative resistance diode chip and a manufacturing method thereof. A first diffusion layer and a first PN junction are formed by doping an impurity of which the conductive type is opposite to that of a silicon substrate into one surface of the silicon substrate; an impurity of which the conductive type is the same as that of the silicon substrate and the concentration is higher than that of the impurity in the first diffusion layer is doped into the surface of the first diffusion layer, so that a second diffusion layer and a second PN junction are formed; a distance between the first PN junction and the second PN junction is 2 to 15 microns; passivation layers are arranged on the outer sides of two ends of the first PN junction andthe second PN junction which are exposed on the side walls of a boss; and metal layers are arranged on the top surface of the boss and the bottom surface of the silicon substrate. The table-board type unidirectional negative resistance diode chip has the characteristics that: the manufacturing cost is lower, the manufacturing method is simple, a full-automatic working mode can be realized, and the like.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, especially relevant with the unidirectional negative resistance diode chip of mesa and manufacture method thereof.
Background technology
Generally use bidirectional trigger diode in the electricity-saving lamp half-bridge inverter start-up circuit, this device can be considered open base, the NPN transistor of emitter and collector symmetry.Because the needs of characteristic, the width of bidirectional trigger diode base is about about 40um.Present manufacturing process mainly is divided into two-sided synchronous diffusion or adopts the planar technique manufacturing, and the former manufacturing technology difficulty when two-sided etching is bigger, and the fragmentation loss is higher; Latter's manufacturing technology equipment input cost is higher.Consider that bidirectional trigger diode only is applied to the characteristic of one of them PN junction in electricity-saving lamp half-bridge inverter start-up circuit, research and development manufacturing cost novel semi-conductor device lower, that manufacture method is simple, replaceable bidirectional trigger diode is used in electricity-saving lamp half-bridge inverter start-up circuit is main thought of the present invention.
Summary of the invention
The purpose of this invention is to provide a kind of low cost of manufacture, simple, the replaceable unidirectional negative resistance diode chip of mesa and the manufacture method thereof that is applied to bidirectional trigger diode in the energy-conservation lamp half-bridge inverter start-up circuit of manufacture method.
For achieving the above object, the present invention is achieved by the following technical solutions: the unidirectional negative resistance diode chip of mesa, comprise silicon chip, silicon chip wherein the impurity that mixes with the silicon chip conductivity type opposite of one side form first diffusion layer and first PN junction, identical with the silicon chip conduction type at the first diffusion layer surface doping, but impurity concentration is higher than the impurity of the high impurity concentration C2 of first diffusion layer, form second diffusion layer and second PN junction, wherein, the high impurity concentration C2 of first diffusion layer is 10～100 times of silicon chip impurity concentration C1, the high impurity concentration C3 of second diffusion layer is 10～1000 times of the high impurity concentration C2 of first diffusion layer, the spacing of first PN junction and second PN junction is 2～15 microns, be exposed to that the two ends outside of first PN junction and second PN junction is provided with passivation layer on the sidewall of boss, be provided with metal level at the table top of boss and the bottom surface of silicon chip.
The unidirectional negative resistance diode chip of described mesa, its passivation layer are glass passivation layer or CVD deposited film, and silicon chip is abrasive sheet.
A kind of method of making the unidirectional negative resistance diode chip of mesa is: a. chooses the silicon chip that impurity concentration C1 is 7.7E+16-7.7E+17, impurity in any pre-deposition of silicon chip and silicon chip conductivity type opposite, the control temperature is at 900-1150 ℃, 0.5-5 hours pre-deposition time, form first diffusion layer and first PN junction, b. the impurity in first diffusion layer was distributed 5-30 hours under 1200-1265 ℃ of temperature again, make high impurity concentration C2 in first diffusion layer be reduced to 10～100 times of impurity concentration C1 in the silicon chip, c. in that the first diffusion layer surface doping is identical with impurity conduction type in the silicon chip but impurity concentration is higher than the impurity of high impurity concentration C2 in first diffusion layer, under 1000-1265 ℃ of temperature, spread 0.5-8 hours, form second diffusion layer and second PN junction, making first PN junction and the second PN junction spacing is 2～15 microns, d. carry out photoetching on the second diffusion layer surface, corrosion, form boss, two ends of first PN junction and second PN junction all are exposed on the sidewall of boss, e. do one deck passivation layer at the sidewall of boss, first PN junction and second PN junction are sealed fully, be isolated from the outside, f. does the layer of metal layer at the table top of boss and the bottom surface of silicon chip.
The another kind of method of making the unidirectional negative resistance diode chip of mesa is: a. chooses the silicon chip that impurity concentration C1 is 7.7E+16-7.7E+17, at the impurity of any one side diffusion of silicon chip with the silicon chip conductivity type opposite, under 1200-1265 ℃ of temperature, spread 15-50 hours, form first diffusion layer and first PN junction, b. first diffusion layer is removed 20-30 microns with chemistry or blast attenuate mode, make behind the attenuate high impurity concentration C2 in first diffusion layer be reduced to 10～100 times of impurity concentration C1 in the silicon chip, c. the first diffusion layer surface doping but impurity concentration identical with impurity conduction type in the silicon chip is higher than behind the attenuate impurity of high impurity concentration C2 in first diffusion layer behind attenuate, under 1000-1265 ℃ of temperature, spread 0.5-8 hours, form second diffusion layer and second PN junction, making first PN junction and the second PN junction spacing is 2～15 microns, d. carry out photoetching on the second diffusion layer surface, corrosion, form boss, two ends of first PN junction and second PN junction all are exposed on the sidewall of boss, e. do one deck passivation layer at the sidewall of boss, first PN junction and second PN junction are sealed fully, be isolated from the outside, f. does the layer of metal layer at the table top of boss and the bottom surface of silicon chip.
The present invention is owing to adopted technique scheme, compared with prior art have the following advantages: (one) has solved two table top wafers middle problem of surveying automatically: for two table top wafers, need test respectively on the branch two sides during underway survey, therefore can't realize the full-automatic probe test of wafer.First PN junction of electrical parameter only need test to(for) the present invention gets final product, and has saved the testing time of half, can realize full-automatic middle survey of wafer; (2) can realize full-automatic operation: test, get ready for two table top wafer sort time-division faces, when manipulator is got material, the figure of getting ready that is positioned at the crystal grain back side can't be by machine recognition, therefore two table top wafers can't be realized full-automatic operation, wherein one side is electrical owing to only needing test for the present invention, test, get ready all and can finish in one side, therefore can realize full-automatic operation; Adopt single face photoetching, corroding method during (three) for two plane PN junction close together, it is simple to operate, and mesa technique realizes that easily rate of finished products is higher; (4) the unidirectional negative resistance diode chip of mesa, its first PN junction and second PN junction are according to different positive-negative-positive or the NPN types of forming of the conduction type of silicon chip; (5) the unidirectional negative resistance diode chip of mesa that adopts technique scheme to make when using in electricity-saving lamp half-bridge inverter start-up circuit, only needs the first PN junction reverse bias, and the second PN junction forward bias can satisfy instructions for use.
Description of drawings
Fig. 1 is existing bidirectional trigger diode characteristic curve schematic diagram.
Fig. 2 is the unidirectional negative resistance diode characteristic curve of mesa of the present invention schematic diagram.
Fig. 3 is the two table top bidirectional trigger diode chip structural representations of existing NPN type.
Fig. 4 is the unidirectional negative resistance diode chip structure of NPN type mesa of the present invention schematic diagram.
Fig. 5 is each conductive layer Impurity Distribution schematic diagram of the unidirectional negative resistance diode chip of mesa of the present invention.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are described in further detail.
Embodiment 1: as shown in Figure 4 and Figure 5, the unidirectional negative resistance diode chip of mesa, comprise silicon chip 1, silicon chip 1 wherein the impurity that mixes with silicon chip 1 conductivity type opposite of one side form first diffusion layer 2 and first PN junction 4, identical with silicon chip 1 conduction type at first diffusion layer, 2 surface dopings, but impurity concentration is higher than the impurity of first diffusion layer, 2 high impurity concentration C2, form second diffusion layer 3 and second PN junction 5, wherein, the high impurity concentration C2 of first diffusion layer 2 is 30 times of silicon chip 1 impurity concentration C1, the high impurity concentration C3 of second diffusion layer 3 is 100 times of first diffusion layer, 2 high impurity concentration C2, the spacing 6 of first PN junction 4 and second PN junction 5 is 5 microns, be exposed to that the two ends outside of first PN junction 4 and second PN junction 5 is provided with passivation layer 9 on the sidewall 8 of boss 7, be provided with metal level 12 at the table top 10 of boss 7 and the bottom surface 11 of silicon chip 1, passivation layer 9 is glass passivation layer or CVD deposited film, and silicon chip 1 is abrasive sheet.
Embodiment 2: as shown in Figure 4 and Figure 5, choosing impurity concentration C1 is the N-type silicon chip 1 of 7.7E+16, in silicon chip 1 any one side spin coating P type diffuse source, pre-deposition is 2 hours under 1000 ℃ of temperature, form diffusion layer 2 and first PN junction 4, under 1240 ℃ of temperature, distributed again 8 hours, make the high impurity concentration C2 of first diffusion layer 2 reduce to 6.0E+18, mix the N-type impurity that concentration is 7.0E+20 on first diffusion layer, 2 surfaces then, diffusion is 1 hour under 1200 ℃ of temperature, form second diffusion layer 3 and second PN junction 5, the high impurity concentration C3 of diffusion layer 3 this moment second is 7.0E+20, first PN junction 4 and second PN junction, 5 spacings are 3.9 microns, carry out photoetching on second diffusion layer, 3 surfaces at last, corrosion, form boss 7, first PN junction 4 and second PN junction 5 all are exposed on the sidewall 8 of boss 7, do one deck glass or CVD deposited film 9 at the sidewall 8 of boss 7, PN junction is isolated from the outside, adopts the mode of nickel plating or evaporation to finish surface metalation.
Embodiment 3: as shown in Figure 4 and Figure 5, choosing impurity concentration C1 is the N-type silicon chip 1 of 7.5E+17, in silicon chip 1 any one side spin coating P type diffuse source, diffusion is 18 hours under 1260 ℃ of temperature, form first diffusion layer 2 and first PN junction 4, with the chemical reduction mode first diffusion layer 2 is deducted 25 microns, make that diffusion layer 2 high impurity concentration C2 are 1.0E+19 behind the attenuate, the N-type impurity that impurity concentration is 7.0E+21 is mixed on first diffusion layer, 2 surfaces behind attenuate, diffusion is 1.5 hours under 1240 ℃ of temperature, form second diffusion layer 3 and second PN junction 5, the high impurity concentration C3 of diffusion layer 3 this moment second is 7.0E+21, first PN junction 4 and second PN junction, 5 spacings are 7.2 microns, carry out photoetching on diffusion layer 3 surfaces at last, corrosion, form boss 7, first PN junction 4 and second PN junction 4 all are exposed on the sidewall 8 of boss 7, do one deck glass or CVD deposited film 9 at the sidewall 8 of boss 7, PN junction is isolated from the outside, adopts the mode of nickel plating or evaporation to finish surface metalation.
More than the present invention has been done detailed description, can not think that protection scope of the present invention only is confined to above-mentioned execution mode.If do not have to produce in essence difference with the technical scheme of claim of the present invention, the deduction or replace of above-mentioned execution mode still are regarded as within protection scope of the present invention.
Claims (4)
1. unidirectional negative resistance diode chip of mesa, comprise silicon chip (1), it is characterized in that: silicon chip (1) wherein the impurity that mixes with silicon chip (1) conductivity type opposite of one side form first diffusion layer (2) and first PN junction (4), identical with silicon chip (1) conduction type at first diffusion layer (2) surface doping, but impurity concentration is higher than the impurity of the high impurity concentration (C2) of first diffusion layer (2), form second diffusion layer (3) and second PN junction (5), wherein, the high impurity concentration (C2) of first diffusion layer (2) is 10～100 times of silicon chip (1) impurity concentration (C1), the high impurity concentration (C3) of second diffusion layer (3) is 10～1000 times of the high impurity concentration (C2) of first diffusion layer (2), the spacing (6) of first PN junction (4) and second PN junction (5) is 2～15 microns, be exposed to last first PN junction of sidewall (8) (4) of boss (7) and the two ends outside of second PN junction (5) and be provided with passivation layer (9), be provided with metal level (12) at the table top (10) of boss (7) and the bottom surface (11) of silicon chip (1).
2. the unidirectional negative resistance diode chip of mesa according to claim 1, it is characterized in that: passivation layer (9) is glass passivation layer or CVD deposited film, and silicon chip (1) is abrasive sheet.
3. method of making the unidirectional negative resistance diode chip of mesa is characterized in that its manufacture method is:
A. choose impurity concentration (C1) and be the silicon chip of 7.7E+16-7.7E+17 (1), impurity in any pre-deposition of silicon chip (1) and silicon chip (1) conductivity type opposite, the control temperature is at 900-1150 ℃, 0.5-5 hours pre-deposition time, form first diffusion layer (2) and first PN junction (4)
B. the impurity in first diffusion layer (2) was distributed 5-30 hours under 1200-1265 ℃ of temperature again, makes in first diffusion layer (2) high impurity concentration (C2) be reduced to 10～100 times of impurity concentration (C1) in the silicon chip (1),
C. in that first diffusion layer (2) surface doping is identical with impurity conduction type in the silicon chip (1) but impurity concentration is higher than the impurity of high impurity concentration (C2) in first diffusion layer (2), under 1000-1265 ℃ of temperature, spread 0.5-8 hours, form second diffusion layer (3) and second PN junction (5), making first PN junction (4) and second PN junction (5) spacing (6) is 2～15 microns
D. carry out photoetching, corrosion on second diffusion layer (3) surface, form boss (7), two ends of first PN junction (4) and second PN junction (5) all are exposed on the sidewall (8) of boss (7),
E. do one deck passivation layer (9) at the sidewall (8) of boss (7), first PN junction (4) and second PN junction (5) sealed fully, be isolated from the outside,
F. do layer of metal layer (12) at the table top (10) of boss (7) and the bottom surface (11) of silicon chip (1).
4. method of making the unidirectional negative resistance diode chip of mesa is characterized in that its manufacture method is:
A. choose impurity concentration (C1) and be the silicon chip of 7.7E+16-7.7E+17 (1), at the impurity of any one side diffusion of silicon chip (1) with silicon chip (1) conductivity type opposite, under 1200-1265 ℃ of temperature, spread 15-50 hours, form first diffusion layer (2) and first PN junction (4)
B. first diffusion layer (2) is removed 20-30 microns with chemistry or blast attenuate mode, makes behind the attenuate in first diffusion layer (2) high impurity concentration (C2) be reduced to 10～100 times of impurity concentration (C1) in the silicon chip (1),
C. first diffusion layer (2) surface doping but impurity concentration identical with impurity conduction type in the silicon chip (1) is higher than behind the attenuate impurity of high impurity concentration (C2) in first diffusion layer (2) behind attenuate, under 1000-1265 ℃ of temperature, spread 0.5-8 hours, form second diffusion layer (3) and second PN junction (5), making first PN junction (4) and second PN junction (5) spacing (6) is 2～15 microns
D. carry out photoetching, corrosion on second diffusion layer (3) surface, form boss (7), two ends of first PN junction (4) and second PN junction (5) all are exposed on the sidewall (8) of boss (7),
E. do one deck passivation layer (9) at the sidewall (8) of boss (7), first PN junction (4) and second PN junction (5) sealed fully, be isolated from the outside,
F. do layer of metal layer (12) at the table top (10) of boss (7) and the bottom surface (11) of silicon chip (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110400117 CN102437199B (en) | 2011-12-06 | 2011-12-06 | Table-board type unidirectional negative resistance diode chip and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110400117 CN102437199B (en) | 2011-12-06 | 2011-12-06 | Table-board type unidirectional negative resistance diode chip and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102437199A CN102437199A (en) | 2012-05-02 |
| CN102437199B true CN102437199B (en) | 2013-09-04 |
Family
ID=45985176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110400117 Active CN102437199B (en) | 2011-12-06 | 2011-12-06 | Table-board type unidirectional negative resistance diode chip and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102437199B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103871875A (en) * | 2012-12-17 | 2014-06-18 | 中国振华集团永光电子有限公司 | Manufacturing method and structure of low-temperature-coefficient silicon voltage reference diode |
| CN106252349B (en) * | 2016-09-30 | 2019-10-29 | 富芯微电子有限公司 | A kind of low Capacitance Power TVS device and its manufacturing method |
| CN108110063A (en) * | 2018-01-08 | 2018-06-01 | 浙江明德微电子股份有限公司 | A kind of unidirectional TVS chips |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19936636A1 (en) * | 1999-08-04 | 2001-02-15 | Siemens Ag | Protective structure for an integrated semiconductor circuit to protect against electrostatic discharge |
| US20030025175A1 (en) * | 2001-07-27 | 2003-02-06 | Sanyo Electric Company, Ltd. | Schottky barrier diode |
| CN101719507B (en) * | 2009-09-28 | 2012-04-25 | 绍兴科盛电子有限公司 | Single table surface series plane PN junction chip and manufacturing method thereof |
| CN202534653U (en) * | 2011-12-06 | 2012-11-14 | 绍兴旭昌科技企业有限公司 | Mesa-type unidirectional negative resistance diode chip |
-
2011
- 2011-12-06 CN CN 201110400117 patent/CN102437199B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN102437199A (en) | 2012-05-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101720512B (en) | Formation of high quality back contact with screen-printed local back surface field | |
| CN1331235C (en) | N-type semiconductor diamond producing method and semiconductor diamond | |
| CN101399200B (en) | Method for manufacturing silicon diode PN junction by same diffusion process of P and N paper sources | |
| CN102437199B (en) | Table-board type unidirectional negative resistance diode chip and manufacturing method thereof | |
| CN103035746B (en) | Current regulative diode and manufacturing method thereof | |
| EP4250338A3 (en) | Solar cell preparation method | |
| CN105810769B (en) | A kind of laser slotting structure of back passivation solar battery | |
| US2757323A (en) | Full wave asymmetrical semi-conductor devices | |
| CN102412268B (en) | Flat-type one-way trigger diode chip and manufacturing method thereof | |
| CN101719507B (en) | Single table surface series plane PN junction chip and manufacturing method thereof | |
| CN103187250B (en) | Repeatedly epitaxial growth method | |
| CN111370341A (en) | Method for testing interface recombination rate of crystalline silicon cell | |
| CN103378211B (en) | Solar cell unit and manufacturing method thereof | |
| CN202534653U (en) | Mesa-type unidirectional negative resistance diode chip | |
| CN106981544A (en) | The preparation method and battery and its component, system of full back contact solar cell | |
| CN101976657B (en) | Substrate structure for semiconductor device fabrication and method for fabricating same | |
| CN111129110A (en) | Power chip terminal structure, and manufacturing method and device of power chip terminal structure | |
| CN103633149B (en) | Current regulator diode and manufacture method thereof | |
| JP5201659B2 (en) | Method for manufacturing bypass diode for solar cell | |
| CN103762279A (en) | Method for manufacturing selective back field of N type silicon solar cell, N type silicon solar cell and method for manufacturing N type silicon solar cell | |
| CN109390233A (en) | A kind of manufacturing method of channel schottky | |
| CN103943471B (en) | Epitaxial layer forming method and semiconductor structure | |
| CN209571422U (en) | A kind of two-sided crystal silicon solar batteries | |
| CN112599431A (en) | Wafer bonding structure and bonding method | |
| CN202363465U (en) | Bidirectional trigger diode chip with single table surface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: ZHEJIANG MINGDE MICROELECTRONICS CO., LTD. Free format text: FORMER NAME: SHAOXING RISING-SUN TECHNOLOGY CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: 312000 Longshan Software Park, Shaoxing Economic Development Zone, Shaoxing, Zhejiang Patentee after: ZHEJIANG MINGDE MICROELECTRONIC CO., LTD. Address before: 312000 Longshan science and Technology Park, East Mountain Road, Shaoxing Economic Development Zone, Shaoxing, Zhejiang Patentee before: Shaoxing Rising-sun Technology Co., Ltd. |