CN109390233A - A kind of manufacturing method of channel schottky - Google Patents
A kind of manufacturing method of channel schottky Download PDFInfo
- Publication number
- CN109390233A CN109390233A CN201710669356.8A CN201710669356A CN109390233A CN 109390233 A CN109390233 A CN 109390233A CN 201710669356 A CN201710669356 A CN 201710669356A CN 109390233 A CN109390233 A CN 109390233A
- Authority
- CN
- China
- Prior art keywords
- layer
- gently
- resistivity
- manufacturing
- extension
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 12
- 230000004888 barrier function Effects 0.000 abstract description 8
- 239000000463 material Substances 0.000 abstract description 5
- 238000000407 epitaxy Methods 0.000 abstract description 3
- 238000005457 optimization Methods 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 102
- 238000005530 etching Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
Abstract
The invention discloses a kind of manufacturing methods of channel schottky, and this method comprises the following steps: a. one layer of buffer layer of first extension on the heavily doped substrate of N+；B. n-layer is successively grown on the buffer layer gently mix layer.The relatively higher buffer layer of one layer of doping concentration of elder generation's extension of the present invention, for further reducing the forward conduction voltage drop of device under the premise of guaranteeing that device is pressure-resistant, reduce the resistance of drift region, what one or more layers doping concentration of extension gradually decreased again, which gently mixes layer, is gradually increased each layer resistivity, it can be effectively reduced the reverse leakage of device, realize the pressure resistance optimization between barrier region and groove, realize the adjustment to electrical resistivity of epitaxy, electric leakage and the conduction voltage drop for effectively reducing trench schottky product, further promote device performance；Substrate material promotes the performance of device by the way of multilayer epitaxial, does not need the special technique of additional increase, completely compatible with prior art, reduces processing cost.
Description
Technical field
The present invention relates to the manufacturing process of Schottky more particularly to a kind of manufacturing methods of channel schottky.
Background technique
Schottky barrier diode has used many decades in power supply application field as rectifying device.Relative to PN junction
For diode, Schottky barrier diode has the advantages that positive cut-in voltage is low and switching speed is fast, this keeps it very suitable
It closes and is applied to Switching Power Supply and high frequency occasion.Schottky barrier diode is the gold formed using metal and semiconductor contact
Category-semiconductor junction principle manufacture.Channel schottky generates the principle of depletion layer pinch off conductive channel using groove structure,
Its high frequency characteristics and electrical performance are substantially better than planar Schottky.
It is well known that the silicon materials that Schottky diode chip uses are usually single layer silicon epitaxial wafer, single layer silicon epitaxial wafer
It is made of silicon chip substrate (N+) and epitaxial layer (N-) two parts.Conventional groove type Schottky diode structure is as shown in Figure 1, be
Be conducive to illustrate, each thickness degree is not drawn to scale in figure, and the metal layer at the back side is not drawn into, plough groove type Xiao Te
Based diode structure includes silicon substrate 101, epitaxial layer 102, is spaced the multiple groove structures being formed in the epitaxial layer, is located at
Gate oxide 103 in the groove, the conductive polycrystalline silicon 104 being embedded in the gate oxide, and it is made in above structure
The front metal electrode 105 on surface.The shortcomings that prior art is that the resistivity of N- epitaxial layer determines the electric leakage and conducting of device
Pressure drop, the resistivity of epitaxial layer thinks further to reduce electric leakage after determining and conduction voltage drop is highly difficult.
Summary of the invention
In order to solve the above technical problems, the present invention provides a kind of manufacturing method of channel schottky.
The present invention provides a kind of manufacturing methods of channel schottky, include the following steps:
A. one layer of buffer layer of first extension on the heavily doped substrate of N+；B. n-layer is successively grown on the buffer layer gently mix layer.
Above technical scheme, it is preferred that the n-layer, which gently mixes layer and is at least one layer, gently mixes layer, is at most four layers and gently mixes layer.
Above technical scheme, it is preferred that the n-layer gently mixes layer to be made by the way of gradually reducing doping concentration from the bottom to top
Every layer of resistivity becomes larger.
Above technical scheme, it is preferred that the resistivity of the buffer layer is 0.1~20 Ω .cm, with a thickness of 1~20um.
Above technical scheme, it is preferred that the resistivity for gently mixing every layer of layer is respectively 0.3~30 Ω .cm, thickness difference
For 1~20um.
Above technical scheme, it is preferred that step a, b carries out under conditions of temperature is 800~1150 DEG C.
Above technical scheme, it is preferred that layer is gently mixed by chemical vapor deposition process epitaxial buffer layer and growth.
The advantages and positive effects of the present invention are: the buffering that one layer of doping concentration of elder generation's extension of the present invention is relatively higher
Layer, for reducing the resistance of drift region in the forward conduction voltage drop for guaranteeing further to reduce device under the premise of device pressure resistance,
What one or more layers doping concentration of extension gradually decreased again, which gently mixes layer, is gradually increased each layer resistivity, can be effectively reduced device
Reverse leakage, realize the pressure resistance optimization between barrier region and groove, realize the adjustment to electrical resistivity of epitaxy, effectively reduce ditch
The electric leakage of slot schottky products and conduction voltage drop, further promote device performance；Substrate material by the way of multilayer epitaxial come
The performance for promoting device does not need the special technique of additional increase, completely compatible with prior art, reduces processing cost.
Detailed description of the invention
Fig. 1 shows a kind of structural schematic diagrams of groove type Schottky diode structure in the prior art
Fig. 2 indicates the structural schematic diagram of channel schottky made from the embodiment of the present invention one
Fig. 3 indicates the structural schematic diagram of channel schottky made from the embodiment of the present invention two
Fig. 4 indicates the structural schematic diagram of channel schottky made from the embodiment of the present invention three
Specific embodiment
In order to which technical problems, technical solutions and advantages to be solved are more clearly understood, tie below
Conjunction attached drawing, which makes embodiments of the present invention, to be illustrated.
The manufacturing method of channel schottky of the invention includes the following steps: a. first one layer of extension on the heavily doped substrate of N+
Buffer layer；B. successively growth n-layer gently mixes layer on the buffer layer.
Preferably, the resistivity of buffer layer gently mixes the resistivity of every layer of layer for 0.1~20 Ω .cm with a thickness of 1~20um
Respectively 0.3~30 Ω .cm, thickness are respectively 1~20um.
Preferably, n-layer, which gently mixes layer and is at least one layer, gently mixes layer, is at most four layers and gently mixes layer, n-layer is gently mixed layer and adopted from the bottom to top
Every layer of resistivity is become larger with the mode for gradually reducing doping concentration.Preferably, step a, b temperature be 800~
It is carried out under conditions of 1150 DEG C, it is preferred that layer is gently mixed by chemical vapor deposition process epitaxial buffer layer and growth.
Embodiment 1
Step 1: one layer of buffer layer of first extension on the heavily doped silicon substrate of N+, N: 0.1~20 Ω .cm of resistivity, thickness 1~
20um, what this layer of extension N was primarily served is the forward conduction pressure that device is further reduced under the premise of guaranteeing that device is pressure-resistant
Drop, reduces the purpose of the resistance of drift region；
Step 2: one layer of extension gently mixes layer on the buffer layer, and compared to upper layer buffer layer, its doping concentration decreases, N-:
0.3~30 Ω .cm of resistivity, 1~20um of thickness, extension N- are mainly the reverse leakage that can be effectively reduced device, by excellent
Change the layer resistivity and realizes that the pressure resistance between barrier region and groove optimizes.Step 1: two be 800~1150 DEG C of condition in temperature
Lower progress gently mixes layer by chemical vapor deposition process epitaxial buffer layer and growth, using above-mentioned technique epitaxial buffer layer and life
Long gently mixing layer belongs to means customary in the art, and which is not described herein again.
Only have one layer of N- epitaxial layer in prior art, the resistivity of the epitaxial layer determines the electric leakage and conducting pressure of device
It drops, thinks further to reduce electric leakage after the resistivity of the epitaxial layer determines and conduction voltage drop is highly difficult, this method is in heavily-doped Si
One layer of buffer layer of extension reduces the resistance of drift region on substrate, reduces the forward conduction voltage drop of device, then outer on it
Prolong one layer of N- and mix layer gently to reduce the reverse leakage of device, makes to further decrease electric leakage and conduction voltage drop is controllable.
Step 3: subsequent machining technology is identical as prior art after selected epitaxial material, and it is special not need additional increase
Technique, successively carry out the processing of disk front, the back side processing etc., the specific steps are as follows:
Hard mask layer is first manufactured in a manner of chemical meteorology deposition or oxidation in the front for completing the substrate material of extension,
Then by making figure by lithography, mask layer is etched using dry etch process, is then removed photoresist, then is carried out by silicon etching equipment
Etching groove, trench depth 1-5um, determines according to device voltage；Gate oxide is grown, then deposit polycrystalline silicon, thicknesses of layers
Specifically determined by design；Then carry out polycrystal etching, be etched to crystal column surface polycrystalline be etched until；Complete polycrystal etching
Metallization medium layer afterwards；Aperture layer etching is carried out by way of photoetching；Barrier metal deposition and potential barrier are carried out after the completion of aperture layer etching
Alloy arranges front metal deposition after the completion；Front metal photoetching, etching；Conventional backside of wafer processing technology, pad pasting subtract
Thin, burn into takes off film, cleaning, back metal.
Embodiment 2
According to the difference of device pressure resistance, the quantity that extension N- gently mixes layer in step 2 is not limited to one layer, can be multilayer
Structure incrementally increases each epilayer resistance rate generally using gradually reducing doping concentration by the way of, i.e., it is each it is light mix layer by down toward
Upper doping concentration gradually decreases, and resistivity is gradually increased therewith, naturally it is also possible to targetedly be optimized for individual layers.
One layer of extension in 1 step 2 of embodiment is gently mixed layer and is changed to two layers of extension by embodiment 2 gently mixes layer, and a layer ratio is gently mixed on upper layer
It is big that layer resistivity is gently mixed by lower layer, but each layer resistivity and thickness is still in prescribed requirement, and N-: 0.3~30 Ω .cm of resistivity, it is thick
Spend 1~20um.Other steps are the same as embodiment 1.
Embodiment 3
One layer of extension in 1 step 2 of embodiment is gently mixed layer and is changed to four layers of extension by embodiment 3 gently mixes layer, this four layers light to mix layer
Resistivity is gradually increased from the bottom to top, but each layer resistivity and thickness is still in prescribed requirement, and N-: 0.3~30 Ω of resistivity
.cm, 1~20um of thickness.Other steps are the same as embodiment 1.
The relatively higher buffer layer of one layer of doping concentration of elder generation's extension of the present invention, under the premise of guaranteeing that device is pressure-resistant
The further forward conduction voltage drop for reducing device, reduces the resistance of drift region, then extension one or more layers doping concentration is gradually
What is reduced gently mixes layer and is gradually increased each layer resistivity, can be effectively reduced the reverse leakage of device, realizes barrier region and groove
Between pressure resistance optimization, realize the adjustment to electrical resistivity of epitaxy, effectively reduce trench schottky product electric leakage and conducting pressure
Drop, further promotes device performance；Substrate material promotes the performance of device by the way of multilayer epitaxial, does not need additional
Increase special technique, it is completely compatible with prior art, reduce processing cost.
One embodiment of the invention is described in detail above, but the content is only preferable implementation of the invention
Example, should not be considered as limiting the scope of the invention.It is all according to all the changes and improvements made by the present patent application range
Deng should still be within the scope of the patent of the present invention.
Claims (7)
1. a kind of manufacturing method of channel schottky, which comprises the steps of:
A. one layer of buffer layer of first extension on the heavily doped substrate of N+；
B. n-layer is successively grown on the buffer layer gently mix layer.
2. the manufacturing method of channel schottky according to claim 1, it is characterised in that: the n-layer gently mixes layer at least
Layer gently is mixed for one layer, is at most four layers and gently mixes layer.
3. the manufacturing method of channel schottky according to claim 1 or 2, it is characterised in that: the n-layer gently mix layer by
Under the supreme resistivity for making every layer by the way of gradually reducing doping concentration become larger.
4. the manufacturing method of channel schottky according to claim 1, it is characterised in that: the resistivity of the buffer layer
For 0.1~20 Ω .cm, with a thickness of 1~20um.
5. the manufacturing method of channel schottky according to claim 1 or 4, it is characterised in that: described gently to mix every layer of layer
Resistivity be respectively 0.3~30 Ω .cm, thickness is respectively 1~20um.
6. the manufacturing method of channel schottky according to claim 1, it is characterised in that: step a, b is in temperature
Degree carries out under conditions of being 800~1150 DEG C.
7. the manufacturing method of channel schottky according to claim 1, it is characterised in that: pass through chemical vapor deposition work
Layer is gently mixed in skill epitaxial buffer layer and growth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710669356.8A CN109390233A (en) | 2017-08-08 | 2017-08-08 | A kind of manufacturing method of channel schottky |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710669356.8A CN109390233A (en) | 2017-08-08 | 2017-08-08 | A kind of manufacturing method of channel schottky |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109390233A true CN109390233A (en) | 2019-02-26 |
Family
ID=65412687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710669356.8A Pending CN109390233A (en) | 2017-08-08 | 2017-08-08 | A kind of manufacturing method of channel schottky |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109390233A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113066856A (en) * | 2021-04-27 | 2021-07-02 | 厦门吉顺芯微电子有限公司 | Trench MOS Schottky rectifier device with double-layer epitaxial structure and manufacturing method |
| CN113299539A (en) * | 2021-05-24 | 2021-08-24 | 深圳市联冀电子有限公司 | SBD low forward saturation special material and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5612567A (en) * | 1996-05-13 | 1997-03-18 | North Carolina State University | Schottky barrier rectifiers and methods of forming same |
| CN101114670A (en) * | 2006-07-28 | 2008-01-30 | 松下电器产业株式会社 | Schottky barrier semiconductor device |
| CN102694034A (en) * | 2011-03-25 | 2012-09-26 | 株式会社东芝 | Semiconductor device |
| CN102916055A (en) * | 2012-10-11 | 2013-02-06 | 杭州立昂微电子股份有限公司 | Trenched Schottky-barrier diode and manufacturing method thereof |
-
2017
- 2017-08-08 CN CN201710669356.8A patent/CN109390233A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5612567A (en) * | 1996-05-13 | 1997-03-18 | North Carolina State University | Schottky barrier rectifiers and methods of forming same |
| CN101114670A (en) * | 2006-07-28 | 2008-01-30 | 松下电器产业株式会社 | Schottky barrier semiconductor device |
| CN102694034A (en) * | 2011-03-25 | 2012-09-26 | 株式会社东芝 | Semiconductor device |
| CN102916055A (en) * | 2012-10-11 | 2013-02-06 | 杭州立昂微电子股份有限公司 | Trenched Schottky-barrier diode and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113066856A (en) * | 2021-04-27 | 2021-07-02 | 厦门吉顺芯微电子有限公司 | Trench MOS Schottky rectifier device with double-layer epitaxial structure and manufacturing method |
| CN113299539A (en) * | 2021-05-24 | 2021-08-24 | 深圳市联冀电子有限公司 | SBD low forward saturation special material and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103400865B (en) | GaN Schottky diode based on polarization doping | |
| CN105405895B (en) | A kind of low storage charge fast recovery diode chip | |
| US9123769B2 (en) | Power semiconductor device and fabrication method thereof | |
| CN101694842B (en) | Power AlGaN/GaN Schottky diode and manufacturing method thereof | |
| CN104201211B (en) | Preparation SiC Ultrafast recovery diode and technique | |
| CN103578978A (en) | Method for manufacturing high-voltage fast recovery diodes based on silicon-based bonding materials | |
| CN105720110A (en) | SiC annular floating-point type P+ structured junction barrier Schottky diode and preparation method thereof | |
| EP4141960A1 (en) | Field effect transistor having same gate and source doping, cell structure, and preparation method | |
| CN102916055B (en) | Trenched Schottky-barrier diode and manufacturing method thereof | |
| CN109390233A (en) | A kind of manufacturing method of channel schottky | |
| CN110190128A (en) | A kind of MOSFET element and preparation method thereof of silicon carbide bilateral depth L shape base region structure | |
| CN110534559A (en) | A kind of sic semiconductor device terminal and its manufacturing method | |
| CN103187250B (en) | Repeatedly epitaxial growth method | |
| CN104701385B (en) | The high stability low loss microwave diode of nanocrystalline embedding single crystal epitaxial carborundum | |
| CN109950299A (en) | A kind of power integrated diode chip structure and preparation method thereof | |
| CN105957865A (en) | MOSFET (Metal Oxide Semiconductor Field Effect Transistor) integrated with trench Schottky | |
| CN206574721U (en) | A kind of double trench MOSFET devices of SiC of integrated schottky diode | |
| CN108206220A (en) | The preparation method of diamond Schottky diode | |
| CN110896098B (en) | Reverse switch transistor based on silicon carbide base and preparation method thereof | |
| CN107256884A (en) | A kind of silicon carbide power diode component and preparation method thereof | |
| CN217881518U (en) | Novel silicon carbide planar power MOSFET device | |
| CN203351609U (en) | Polarized doping-based GaN Schottky diode | |
| CN107785427A (en) | Vertical DMOS device and preparation method thereof | |
| CN103400853A (en) | Silicon carbide Schottky barrier diode and manufacturing method thereof | |
| CN106098781B (en) | A kind of VDMOS of groove structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190226 |