CN109950299A - A kind of power integrated diode chip structure and preparation method thereof - Google Patents
A kind of power integrated diode chip structure and preparation method thereof Download PDFInfo
- Publication number
- CN109950299A CN109950299A CN201910306433.2A CN201910306433A CN109950299A CN 109950299 A CN109950299 A CN 109950299A CN 201910306433 A CN201910306433 A CN 201910306433A CN 109950299 A CN109950299 A CN 109950299A
- Authority
- CN
- China
- Prior art keywords
- layer
- type
- power integrated
- polysilicon
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of power integrated diode chip structure and preparation method thereof, which includes the lower metal layer stacked gradually from bottom to up, substrate, epitaxial layer, well region, polysilicon layer and front metal layer；Well region conduction type positioned at epitaxial layer top is opposite with epitaxial layer；Polysilicon layer is isolated with well region by oxide layer, and polysilicon layer is divided into n-type region and p type island region domain；Portion is provided with dielectric layer on the polysilicon layer, is front metal layer above dielectric layer；Components multiple in circuit are integrated in same chip by above-mentioned semiconductor structure, keep the semiconductor devices of production small in size, it is integrated and at low cost to be conducive to miniaturization.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of power integrated diode chip structure and its production side
Method.
Background technique
Applied to the fly-back converter circuit of various small-power powers and power supply adaptor, RCD clamper is generallyd use
Integrated circuit, and the diode in RCD clamper integrated circuit is usually slow recovery diode.To further increase suppressed ringing
Effect, can also be in one damping resistance Rdamp of the side of diode series connection.More optimal solution is in parallel again in damping resistance Rdamp
One fast recovery diode.As shown in Figure 1.
But using the circuit structure, electronic component quantity is more, and volume is big, is unfavorable for miniaturization and integrates, and cost
It is higher.In patent CN 207320125U, by two diodes (a slow recovery diode and a fast recovery diode) and
Damping resistance Rdamp is integrated in same chip, and which strongly simplifies circuits, save circuit space, is conducive to electronics and is set
Standby miniaturization.But due to needing to be internally integrated resistance and multiple diodes in silicon epitaxy layer, technical matters process is complicated, and
Due to the influence of parasitic parameter, device parameters are not easy to be controlled.
Summary of the invention
In order to solve the above-mentioned technical problem the present invention, provides chip structure and its production side of a kind of power integrated diode
Method.
The present invention is achieved through the following technical solutions:
A kind of power integrated diode chip structure, including the lower metal layer, substrate, extension stacked gradually from bottom to up
Layer, polysilicon layer and front metal layer, an electrode of the lower metal layer as power integrated diode, on the epitaxial layer
Portion is formed with well region, and well region conduction type is opposite with substrate and epitaxial layer conduction type.Polysilicon is disposed on the top of well region
Layer, has oxide layer to be isolated, polysilicon is divided into n-type region and p type island region domain between polysilicon layer and epitaxial layer.In the upper of polysilicon layer
There is front metal layer in portion, another electrode as power integrated diode.In the semiconductor structure, well region and below
Epitaxial layer constitutes the PN junction of slow recovery diode, and the doping concentration and thickness of epitaxial layer determine reversely hitting for slow recovery diode
Wear voltage and reverse recovery time.The n-type region of polysilicon layer and p type island region domain constitute the PN junction of fast recovery diode, pass through
The width in control n-type region and p type island region domain adjusts the reverse recovery time of fast recovery diode in which can be convenient.It simultaneously will damping
Resistance is also made in this polysilicon layer, adjusts it with can be convenient by the doping concentration and length-width ratio that control polysilicon layer
The size of resistance value.This programme realizes foregoing circuit by above-mentioned semiconductor chip structure, and all components are integrated in same
In chip, and it is made in the fast recovery diode on polysilicon and damping resistance, does not increase chip area additionally, therefore more have
It is integrated conducive to miniaturization, it is also beneficial to reduce device manufacturing cost.
A kind of production method of power integrated diode chip, comprising the following steps:
A, epitaxial layer identical with substrate conduction type is formed on the substrate；
B, the well region opposite with epitaxial layer conduction type is formed by ion implanting and method for annealing on epitaxial layer, and same
When form the oxide layer be isolated with polysilicon；
C, depositing polysilicon layer, and make polysilicon p-type or N-type by way of doping；
D, by lithography and etching, polysilicon layer is made to form required figure；
E, N-type or p type island region domain are formed on polycrystalline by way of photoetching and ion implanting；
F, dielectric layer is formed by way of aoxidizing or depositing in silicon chip surface；
G, contact hole is formed in dielectric layer by the method for lithography and etching；
H, one layer of upper metal layer is deposited in dielectric layer upper surface, each component is produced by way of lithography and etching
Connecting line and front electrode；
I, chip is carried out thinned, and makes lower metal layer below substrate.
Preferably, the doping concentration of conductive impurity is 1E18 to 1E21 in the substrate；
Preferably, the doping concentration of the epitaxial layer conductive impurity be 1E13 to 1E17, epitaxy layer thickness be 30~
150um.Epitaxial layer may be configured as single-layer or multi-layer, for example, two layers, three layers etc., when multilayer is set, the conductive matter of epitaxial layer doping
Concentration from top to bottom successively increase.
Compared with prior art, the present invention at least having the following advantages and benefits:
1, it is realized by this method and chip structure and is integrated in components multiple in foregoing circuit in same chip favorably
In simplified circuit；
2, the slow recovery diode of high pressure is only made in silicon epitaxy layer, and remaining component is made in polysilicon layer,
It is more advantageous to being precisely controlled for each component parameter, reduces influence of the parasitic parameter to device；
3, polysilicon layer is located at well region top, does not increase chip area additionally, is conducive to save chip area, reduces device
Cost.
Detailed description of the invention
Attached drawing described herein is used to provide to further understand the embodiment of the present invention, constitutes one of the application
Point, do not constitute the restriction to the embodiment of the present invention；
Fig. 1 is the RCD clamper integrated circuit using damping resistance and fast recovery diode；
Fig. 2 is the structural schematic diagram of this power integrated diode；
Fig. 3 is the power integrated diode chip structure schematic diagram using P-type silicon substrate；
Fig. 4 is the power integrated diode chip structure schematic diagram using N-type silicon substrate；
The title of appended drawing reference in figure are as follows:
1, back metal, 2, substrate, 3, epitaxial layer, 4, well region, 5, isolating oxide layer or dielectric layer, 6, connection metal, 7,
Front electrode, 8, polysilicon layer, 9, slow recovery diode PN junction, 10, fast recovery diode PN junction, 11, damping resistance.
Specific embodiment
To better understand the objects, features and advantages of the present invention, with reference to the accompanying drawing and specific real
Applying mode, the present invention is further described in detail.It should be noted that in the case where not conflicting mutually, the application's
Feature in embodiment and embodiment can be combined with each other.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, still, the present invention may be used also
Implemented with being different from the other modes being described herein in range using other, therefore, protection scope of the present invention is not by under
The limitation of specific embodiment disclosed in face.
Embodiment 1
A kind of power integrated diode chip structure as shown in Figure 2, including stack gradually from bottom to up lower metal layer 1,
Substrate 2, epitaxial layer 3, polysilicon layer 8 and front metal layer 6, the substrate and lower metal layer are as power integrated diode
One electrode, the epitaxial layer top are formed with well region, and well region conduction type is opposite with substrate and epitaxial layer conduction type.In trap
The top in area is disposed with polysilicon layer, has oxide layer to be isolated between polysilicon layer and epitaxial layer, and polysilicon is divided into n-type region and P
Type region.There is front metal layer on the top of polysilicon layer, using another electrode as power integrated diode.It partly leads at this
In body structure, well region and epitaxial layer below constitute the PN junction of slow recovery diode.The n-type region of polysilicon layer and p type island region
Domain constitutes the PN junction of fast recovery diode, adjusts fast recovery two by the width of control n-type region and p type island region domain with can be convenient
The reverse recovery time of pole pipe.Damping resistance is also made in this polysilicon layer simultaneously, by the doping for controlling polysilicon layer
Concentration and length-width ratio adjust the size of its resistance value in which can be convenient.
Epitaxial layer may be configured as single-layer or multi-layer, for example, two layers, three layers etc., when multilayer is set, the conduction of epitaxial layer doping
The concentration of matter from top to bottom successively increases.
According to the difference of conduction type, different conductive impurities can be adulterated in layers, and for example: p type impurity or N-type are miscellaneous
Matter.
Embodiment 2
The present embodiment illustrates above-mentioned power integrated diode chip structure and its production side by p-type of the conduction type of substrate
Method.
As shown in figure 3, the power is integrated in figure using the power integrated diode chip structure schematic diagram of P-type silicon substrate
Diode chip for backlight unit includes the silicon substrate of doped p-type impurity, the epitaxial layer of doped p-type impurity；The well region of doped N-type impurity；Polycrystalline
Silicon layer is divided into the region of doped N-type and p-type；I.e. upper metal layer of power integrated diode negative metal layer etc.；Power integrates two poles
The anode of pipe is located at metal layer on back.
Its production method the following steps are included:
Form epitaxial layer in the P-type silicon material substrate that doping concentration is 1E18 to 1E21, epitaxy layer thickness be 10 to
100um, doping concentration are 1E13 to 1E17；
The silicon dioxide layer with a thickness of 0.8 to 2um is formed in chip surface by way of aoxidizing or depositing；
The ion implanted regions of N-type well region are formed above epitaxial layer by the method for lithography and etching, and carry out N-type from
Son injection, preferably the injection ion are phosphorus；Thermal diffusion is carried out to the phosphorus of injection, to achieve the purpose that annealing and knot, thermal expansion
Scattered temperature is 1100~1250 DEG C；While carrying out thermal diffusion, the isolation with a thickness of 0.1 to 1um is formed in chip surface
Oxide layer.
The polysilicon layer for being 0.5 to 2um by being deposited on chip surface deposition thickness；Made by way of ion implanting more
Crystal silicon layer is N-type, and preferably the injection ion is phosphorus or arsenic；
By lithography and etching, polysilicon is made to become required figure；
By way of photoetching and ion implanting, p type island region domain is formed on polycrystal layer, preferably injection ion is boron or fluorine
Change boron, implantation dosage should be higher than that polysilicon layer n-type region implantation dosage；
Dielectric layer is formed in chip surface by way of aoxidizing or depositing, dielectric layer is dioxide layer silicon or boron phosphorus silicon
Glass, with a thickness of 0.2~2um；
Contact hole is made on medium by lithography and etching, a part of contact hole gos deep into epitaxial layer and is located at N-type well region
Inside, a part of contact hole gos deep into polysilicon layer surface.
Metal layer is in chip surface in deposit, and upper metal layer thickness is 2 to 5um, and material is aluminium or aluminium silicon or aluminium copper silicon.
By lithography and etching, make metal layer a part power integrated diode cathode, rest part is slow restores
The connection of diode and fast recovery diode, and the connection of slow recovery diode and damping resistance；
By chip thinning technique, make 150~300um of power integrated diode chip optical thickness；
Lower metal layer is set below substrate by Metal deposition and forms power integrated diode anode.
In the present embodiment, N-type well region and the epitaxial layer being disposed below constitute the PN junction of slow recovery diode, restore two slowly
Pole pipe also has the soft recovery characteristics and slow recovery characteristics when Reverse recovery other than having higher breakdown voltage.On polysilicon
P type island region domain and N-type constitute the PN junction of fast recovery diode, the doping concentration and width of p type island region and N-type region determine fast extensive
The breakdown voltage of multiple diode and reverse recovery time.Damping resistance is also made on polysilicon, the doping concentration of polysilicon and
Length-width ratio determines the size of its resistance value.
Embodiment 3
The present embodiment illustrates above-mentioned power integrated diode chip structure and its production side by N-type of the conduction type of substrate
Method.
As shown in figure 3, the power is integrated in figure using the power integrated diode chip structure schematic diagram of N-type silicon substrate
Diode chip for backlight unit includes the silicon substrate of doped N-type impurity, the epitaxial layer of doped N-type impurity；The well region of doped p-type impurity；Polycrystalline
Silicon layer is divided into the region of doped p-type and N-type；I.e. upper metal layer of power integrated diode negative metal layer etc.；Power integrates two poles
The anode of pipe is located at metal layer on back.
Its production method the following steps are included:
Doping concentration be 1E18 to 1E21 N-type silicon materials substrate on formed with the first epitaxial layer, layer with a thickness of 10 to
100um, doping concentration are 1E13 to 1E17；
The silicon dioxide layer with a thickness of 0.8 to 2um is formed in chip surface by way of aoxidizing or depositing；
By the ion implanted regions of the method for lithography and etching rectangular P type trap zone on epitaxial layer, and carry out P-type ion
Injection, preferably the injection ion are boron；Thermal diffusion is carried out to the boron of injection, to achieve the purpose that annealing and knot, thermal diffusion
Temperature be 1100~1250 DEG C；While carrying out thermal diffusion, the isolation from oxygen with a thickness of 0.1 to 1um is formed in chip surface
Change layer.
The polysilicon layer for being 0.5 to 2um by being deposited on chip surface deposition thickness；Made by way of ion implanting more
Crystal silicon layer is p-type, and preferably the injection ion is boron or boron fluoride；
By lithography and etching, polysilicon is made to become required figure；
By way of photoetching and ion implanting, n-type region is formed on polycrystal layer, preferably injection ion be phosphorus or
Arsenic, implantation dosage should be higher than that polysilicon layer p type island region domain implantation dosage；
Dielectric layer is formed in chip surface by way of aoxidizing or depositing, dielectric layer is dioxide layer silicon or boron phosphorus silicon
Glass, with a thickness of 0.2~2um；
Contact hole is made on dielectric layer by lithography and etching, a part of contact hole gos deep into epitaxial layer and is located at p-type trap
Inside area, a part of contact hole gos deep into polysilicon layer surface.
Metal layer is in chip surface in deposit, and upper metal layer thickness is 2 to 5um, and material is aluminium or aluminium silicon or aluminium copper silicon.
By lithography and etching, keep metal layer a part power integrated diode positive, rest part is slow restores
The connection of diode and fast recovery diode, and the connection of slow recovery diode and damping resistance；
By chip thinning technique, power makes 150~300um of integrated diode chip optical thickness；
Lower metal layer is set below substrate by Metal deposition and forms power integrated diode cathode.
In the present embodiment, P type trap zone and the epitaxial layer being disposed below constitute the PN junction of slow recovery diode, restore two slowly
Pole pipe also has the soft recovery characteristics and slow recovery characteristics when Reverse recovery other than having higher breakdown voltage.On polysilicon
P type island region domain and N-type constitute the PN junction of fast recovery diode, the doping concentration and width of p type island region and N-type region determine fast extensive
The breakdown voltage of multiple diode and reverse recovery time.Damping resistance is also made on polysilicon, the doping concentration of polysilicon and
Length-width ratio determines the size of its resistance value.
By embodiment 2,3 realize power integrated diode slow recovery diode breakdown voltage be 600V~
1200V；The resistance value of damping resistance is the Ω of 10 Ω~500；The fast recovery diode breakdown voltage being in parallel with damping resistance is
10V~200V.Although preferred embodiments of the present invention have been described, once a person skilled in the art knows basic wounds
The property made concept, then additional changes and modifications may be made to these embodiments.So the following claims are intended to be interpreted as includes
Preferred embodiment and all change and modification for falling into the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of power integrated diode chip structure, which is characterized in that the structure includes:
Lower metal layer, substrate, epitaxial layer, polysilicon layer and the front metal layer stacked gradually from bottom to up, the lower metal layer
As an electrode of power integrated diode, the epitaxial layer top is formed with well region, and well region conduction type is with substrate and outside
It is opposite to prolong layer conduction type；It is disposed with polysilicon layer on the top of well region, polysilicon is divided into n-type region and p type island region domain；In polycrystalline
Front metal layer is arranged at the top of silicon layer, another electrode as power integrated diode；In the structure, well region and its under
The epitaxial layer of side constitutes the PN junction of slow recovery diode, and the doping concentration and thickness of epitaxial layer determine the reversed of slow recovery diode
Breakdown voltage and reverse recovery time；The n-type region of polysilicon layer and p type island region domain constitute the PN junction of fast recovery diode, lead to
Spend the reverse recovery time of the width adjustment fast recovery diode in control n-type region and p type island region domain.
2. power integrated diode chip structure according to claim 1, which is characterized in that polysilicon layer and epitaxial layer it
Between have oxide layer isolation.
3. power integrated diode chip structure according to claim 1, which is characterized in that the structure further includes damping
Resistance, damping resistance are made in polysilicon layer, by the doping concentration and length-width ratio adjustment damping electricity that control polysilicon layer
The size of the resistance value of resistance.
4. power integrated diode chip structure according to claim 1, which is characterized in that conductive impurity in the substrate
Doping concentration be 1E18 to 1E21.
5. power integrated diode chip structure according to claim 1, which is characterized in that the epitaxial layer conductive impurity
Doping concentration be 1E13 to 1E17, epitaxy layer thickness be 30~150um；Epitaxial layer may be configured as single-layer or multi-layer, be arranged more
When layer, the concentration of the conductive matter of epitaxial layer doping is from top to bottom successively increased.
6. a kind of production method of power integrated diode chip, which is characterized in that the described method includes:
A, epitaxial layer identical with substrate conduction type is formed on the substrate；
B, the well region opposite with epitaxial layer conduction type is made on epitaxial layer, and is formed simultaneously the oxidation being isolated with polysilicon
Layer；
C, depositing polysilicon layer, and make polysilicon p-type or N-type by way of doping；
D, required figure is formed in polysilicon layer；
E, N-type or p type island region domain are formed on polycrystalline；
F, dielectric layer is formed in silicon chip surface；
G, contact hole is formed in dielectric layer；
H, one layer of upper metal layer is deposited in dielectric layer upper surface, produces the connecting line and front electrode of each component；
I, chip is carried out thinned, and makes lower metal layer below substrate.
7. the production method of power integrated diode chip according to claim 6, which is characterized in that lead on epitaxial layer
It crosses ion implanting and method for annealing forms the well region opposite with epitaxial layer conduction type,.
8. the production method of power integrated diode chip according to claim 6, which is characterized in that by photoetching and
The mode of ion implanting forms N-type or p type island region domain on polycrystalline.
9. the production method of power integrated diode chip according to claim 6, which is characterized in that pass through photoetching and quarter
Erosion, makes polysilicon layer form required figure；Contact hole is formed in dielectric layer by the method for lithography and etching；Pass through photoetching and quarter
The mode of erosion produces the connecting line and front electrode of each component.
10. the production method of power integrated diode chip according to claim 6, it is characterised in that logical in silicon chip surface
The mode of peroxidating or deposit forms dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910306433.2A CN109950299A (en) | 2019-04-16 | 2019-04-16 | A kind of power integrated diode chip structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910306433.2A CN109950299A (en) | 2019-04-16 | 2019-04-16 | A kind of power integrated diode chip structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109950299A true CN109950299A (en) | 2019-06-28 |
Family
ID=67015302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910306433.2A Pending CN109950299A (en) | 2019-04-16 | 2019-04-16 | A kind of power integrated diode chip structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109950299A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113140559A (en) * | 2021-05-18 | 2021-07-20 | 无锡昌德微电子股份有限公司 | Power integrated diode and manufacturing method thereof |
| CN113257674A (en) * | 2021-04-19 | 2021-08-13 | 深圳基本半导体有限公司 | Diode chip structure and manufacturing method |
| WO2021225577A1 (en) * | 2020-05-04 | 2021-11-11 | Power Integrations, Inc. | Voltage shaping circuit with diodes of various recovery times |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0818071A (en) * | 1995-05-25 | 1996-01-19 | Rohm Co Ltd | Manufacture of individual diode device |
| JP2006086417A (en) * | 2004-09-17 | 2006-03-30 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| US20070145411A1 (en) * | 2005-12-28 | 2007-06-28 | Qufei Chen | Trench polysilicon diode |
| CN101442051A (en) * | 2008-12-15 | 2009-05-27 | 深圳市联德合微电子有限公司 | Monocrystallinetype knot-type field effect tube device and preparation method thereof |
| JP5867623B2 (en) * | 2012-11-08 | 2016-02-24 | 富士電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN207320125U (en) * | 2017-11-13 | 2018-05-04 | 成都方舟微电子有限公司 | A kind of power buffer diode fabric chip |
-
2019
- 2019-04-16 CN CN201910306433.2A patent/CN109950299A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0818071A (en) * | 1995-05-25 | 1996-01-19 | Rohm Co Ltd | Manufacture of individual diode device |
| JP2006086417A (en) * | 2004-09-17 | 2006-03-30 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| US20070145411A1 (en) * | 2005-12-28 | 2007-06-28 | Qufei Chen | Trench polysilicon diode |
| CN101442051A (en) * | 2008-12-15 | 2009-05-27 | 深圳市联德合微电子有限公司 | Monocrystallinetype knot-type field effect tube device and preparation method thereof |
| JP5867623B2 (en) * | 2012-11-08 | 2016-02-24 | 富士電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN207320125U (en) * | 2017-11-13 | 2018-05-04 | 成都方舟微电子有限公司 | A kind of power buffer diode fabric chip |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021225577A1 (en) * | 2020-05-04 | 2021-11-11 | Power Integrations, Inc. | Voltage shaping circuit with diodes of various recovery times |
| CN113257674A (en) * | 2021-04-19 | 2021-08-13 | 深圳基本半导体有限公司 | Diode chip structure and manufacturing method |
| CN113257674B (en) * | 2021-04-19 | 2023-03-07 | 深圳基本半导体有限公司 | Diode chip structure and manufacturing method |
| CN113140559A (en) * | 2021-05-18 | 2021-07-20 | 无锡昌德微电子股份有限公司 | Power integrated diode and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7846814B2 (en) | Semiconductor layer structure and method of making the same | |
| EP2525410A1 (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| US20220037515A1 (en) | Bidirectional blocking monolithic heterogeneous integrated cascode-structure field effect transistor, and manufacturing method thereof | |
| CN109950299A (en) | A kind of power integrated diode chip structure and preparation method thereof | |
| CN110350035A (en) | SiC MOSFET power device and preparation method thereof | |
| CN103094359B (en) | High pressure Schottky diode and preparation method thereof | |
| CN111211175A (en) | Fast recovery diode device structure and manufacturing method thereof | |
| CN109037206B (en) | Power device protection chip and manufacturing method thereof | |
| CN115579399A (en) | Silicon carbide MOSFET cell layout structure | |
| CN105789331A (en) | Semiconductor rectifying device and manufacturing method therefor | |
| CN107731932A (en) | A kind of power buffer diode chip structure and preparation method thereof | |
| CN207320125U (en) | A kind of power buffer diode fabric chip | |
| US10644147B2 (en) | Vertical semiconductor device and method of manufacturing vertical semiconductor device | |
| KR100928204B1 (en) | CMOS-based flat-panel avalanche photodiode using silicon epilayer and its manufacturing method | |
| CN109065634B (en) | Current protection chip and manufacturing method thereof | |
| CN113451138B (en) | Planar MOSFET with self-biased terminal and preparation method thereof | |
| CN103021936B (en) | Bipolar circuit manufacture method | |
| CN106409827A (en) | Rectifying device and preparation method thereof | |
| KR20100122281A (en) | Schottky barrier diode and fabricating method thereof | |
| CN211789033U (en) | Fast recovery diode device structure | |
| CN103779416B (en) | The power MOSFET device of a kind of low VF and manufacture method thereof | |
| CN111463282A (en) | Low-voltage super-junction DMOS structure integrating starting tube and sampling tube and preparation method | |
| CN108565259B (en) | Semiconductor device and method for manufacturing the same | |
| CN110690294A (en) | Fast recovery diode | |
| CN116190420B (en) | Fast recovery diode structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190628 |