CN106409827A - Rectifying device and preparation method thereof - Google Patents
Rectifying device and preparation method thereof Download PDFInfo
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- CN106409827A CN106409827A CN201510449706.0A CN201510449706A CN106409827A CN 106409827 A CN106409827 A CN 106409827A CN 201510449706 A CN201510449706 A CN 201510449706A CN 106409827 A CN106409827 A CN 106409827A
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Abstract
The present invention discloses a rectifying device and a preparation method thereof. The device comprises a substrate of a first conductive type, a cell area and a terminal area, wherein a groove type area is arranged on the right side of the substrate of the cell area, the bottom of the groove type area is equipped with a buried layer area of a second conductive type, and the rest areas of the right side of the substrate of the cell area except the groove type area are equipped with the body areas of the second conductive types. The rectifying device contains an MOS structure and a PN junction simultaneously, the advantages of the MOS device and a PN diode can be combined together, and by a groove type structure, the junction type field effect transistor parasitic resistance is not generated, the reduction of the positive conduction voltage drop is not limited, at the same time, the channel density of the device in the unit area also can be increased, and the device cost is reduced. The buried layer area of the second conductive type at the bottom of the groove type area enables a blocking voltage to be improved effectively. Therefore, the rectifying device is simple in structure and excellent in performance, and also has the low positive conduction voltage drop and the high blocking voltage.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of rectifying device and preparation method thereof.
Background technology
Semiconductor diode has the characteristic of forward conduction, reverse blocking, is widely used in the various electronic circuits such as power supply, signal processing.For certain types of diode component, forward bias voltage its forward current before reaching certain particular value (forward conduction voltage drop, also known as forward voltage drop) is substantially negligible.Traditional commutation diode mainly has PN junction diode and Schottky diode two class.PN junction diode forward voltage drop VF is larger, and reverse recovery time, Trr was longer, but the stability of PN junction diode is preferably, can work under high voltages；Schottky diode is that it has absolute advantagess in low-voltage with noble metal (as gold, silver, titanium etc.) and semiconductor contact, the semiconductor device made with forming potential barrier of heterogenous junction：Its forward voltage drop VF is little, and reverse recovery time, Trr was short, had a wide range of applications in High Speed Field.But Schottky diode has that reverse leakage current is big and manufacturing cost is high.
Fig. 1 is a kind of typical case's application schematic diagram of semiconductor diode, and the left side is input, and the right is outfan, and diode therein serves output rectified action in circuit.The forward conduction voltage drop of diode brings two shortcomings to Circuits System：First, reduce the efficiency of converter, such as, it is contemplated that the forward conduction voltage drop of diode in the case of the output of 5V power supply, its actual loading is 5.7V, and in the case of not considering other losses, its delivery efficiency has reduced 13%；Second, above-mentioned delivery efficiency loss can lead to device heating, needs in numerous applications to alleviate device heating problem using the encapsulation of appropriate size or increase radiator, thus increased system bulk and preparation cost.Therefore, in order to improve the rectification efficiency of circuit, the forward conduction voltage drop reducing diode as far as possible has very important significance.
In practical application, diode except work in the on-state, is also often in blocking state.Under the conditions of blocking-up, diode has reverse leakage current, and this leakage current will increase circuit loss, reduces circuit conversion efficiency, particularly under high temperature applied environment.Therefore, it is also desirable to device has less reverse leakage current in addition to wishing diode and there is low forward voltage drop.
In many applications, there is inductance device in electronic circuit, and the backward voltage that inductance produces is possible to add on the diode, leads to diode that avalanche breakdown occurs.Avalanche energy is usually used to characterize device in the case of not losing efficacy from the absorbent ceiling capacity of inductance institute, this parameter depends primarily on the junction area size of device dissipation energy.
Content of the invention
The purpose of the present invention is to propose to a kind of rectifying device and preparation method thereof, this rectifying device has relatively low forward conduction voltage drop and high blocking voltage, can solve the problem that the cut-in voltage of the existing PN junction diode as rectifying device is high, the reversely resistance to of Schottky diode forces down and there is current leakage.
In a first aspect, embodiments providing a kind of rectifying device, including the substrate of the first conduction type, cellular region and termination environment；
The substrate face of described cellular region is provided with groove-shaped area；
Described groove-shaped area bottom is provided with the second conduction type buried regions area；
Remaining area in addition to groove-shaped area for the substrate face of described cellular region is provided with the second conductivity type body region；
The substrate face of described cellular region is provided with the first metal electrode；
Described substrate back is provided with the second metal electrode.
Further, described groove-shaped area includes being formed at the groove of described substrate face, is formed at the oxide layer of described trench wall, and the polysilicon being filled in described trench interiors.
Further, the substrate of described first conduction type has the substrate of the first conductive type epitaxial layer for front growth.
Further, described first conduction type is N-type, and described second conduction type is p-type.
Further, described termination environment includes field limiting ring.
Second aspect, embodiments provides a kind of preparation method of rectifying device, including：
Form termination environment in the substrate face of the first conduction type, remaining area in addition to described termination environment for the described substrate face is cellular region；
Form groove-shaped area, the second conduction type buried regions area and the second conductivity type body region in described cellular region, wherein, the substrate face located at described cellular region for the described groove-shaped area, described second conduction type buried regions area is located at the bottom in described groove-shaped area, remaining area in addition to groove-shaped area for the substrate face located at described cellular region for described second conductivity type body region；
Substrate face in above-mentioned cellular region prepares the first metal electrode；
Prepare the second metal electrode in above-mentioned substrate back.
Further, groove-shaped area, the second conduction type buried regions area and the second conductivity type body region are formed in described cellular region, including：
Form groove in described substrate face；
Form the second conduction type buried regions area in described channel bottom；
Form oxide layer in above-mentioned trench wall；
Polysilicon is filled in above-mentioned groove；
Remaining area in addition to groove-shaped area for the substrate face in described cellular region forms the second conductivity type body region.
Further, the substrate of described first conduction type has the substrate of the first conductive type epitaxial layer for front growth.
Further, described first conduction type is N-type, and described second conduction type is p-type.
Further, the substrate face in the first conduction type forms termination environment, specially：Form p-type field limiting ring in N-type substrate front.
Rectifying device provided in an embodiment of the present invention, including the substrate of the first conduction type, cellular region and termination environment.Wherein, the substrate face of cellular region is provided with groove-shaped area, and groove-shaped area bottom is provided with the second conduction type buried regions area, and the substrate face of the cellular region remaining area in addition to groove-shaped area is provided with the second conductivity type body region.Contain Metal-oxide-semicondutor (metal-oxide-semiconductor, MOS) structure and PN junction in this rectifying device simultaneously, the advantage of MOS device and PN diode can be combined；And adopt slot type structure, technotron (Junction Field-Effect Transistor, JFET) dead resistance will not be produced, that is, without limitation on the reduction of forward conduction voltage drop, gully density in unit area for the device also can be increased simultaneously, lower device cost；Second conduction type buried regions area of groove-shaped area bottom can effectively improve blocking voltage.Therefore, this rectifying device is not only simple in structure, and has low forward conduction voltage drop and high blocking voltage, excellent performance.
The preparation method of rectifying device provided in an embodiment of the present invention, forms termination environment in the substrate face of the first conduction type, forms groove-shaped area, the second conduction type buried regions area and the second conductivity type body region in cellular region.This preparation method can be with existing complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor, CMOS) process compatible, new equipment need not be increased or production line is adjusted on a large scale, and step is simple, can effectively reduce production cost.
Brief description
The exemplary embodiment of the present invention will be described in detail by referring to accompanying drawing below, the person of ordinary skill in the art is more clear that the above-mentioned and other feature and advantage of the present invention, in accompanying drawing：
Fig. 1 is a kind of typical case's application schematic diagram of semiconductor diode；
A kind of schematic top plan view of rectifying device that Fig. 2 provides for the embodiment of the present invention one；
Fig. 3 is the schematic cross-section of a structure cell in Fig. 2；
A kind of partial sectional schematic view of rectifying device that Fig. 4 provides for the embodiment of the present invention one；
Fig. 5 is that the anode in the structure cell shown in Fig. 3 adds operation principle schematic diagram during positive voltage；
Fig. 6 is the positive operating characteristic simulation curve figure corresponding to Fig. 5；
Fig. 7 is the operation principle schematic diagram during anode making alive in the structure cell shown in Fig. 3；
Fig. 8 is the reverse operation characteristic Simulation curve chart corresponding to Fig. 7；
A kind of schematic flow sheet of the preparation method of rectifying device that Fig. 9 provides for the embodiment of the present invention two；
Figure 10 is the idiographic flow schematic diagram of S920 in embodiment illustrated in fig. 9 two；
Figure 11 is the corresponding cross-sectional view of S921 shown in Figure 10；
Figure 12 is the corresponding cross-sectional view of S922 shown in Figure 10；
Figure 13 is the corresponding cross-sectional view of S930 shown in Fig. 9；
Figure 14 is the corresponding cross-sectional view of S940 shown in Fig. 9；
Figure 15 is the corresponding cross-sectional view of S950-S960 shown in Fig. 9；
Figure 16 is the corresponding cross-sectional view of S970 shown in Fig. 9；
Figure 17 is the corresponding cross-sectional view of S980 shown in Fig. 9；
Figure 18 is the corresponding cross-sectional view of S990 shown in Fig. 9.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that specific embodiment described herein is used only for explaining the present invention, rather than limitation of the invention.It also should be noted that, for the ease of description, in accompanying drawing, illustrate only part related to the present invention rather than full content.
Embodiment one
A kind of rectifying device that the embodiment of the present invention one provides, this device includes substrate, cellular region and the termination environment of the first conduction type；The substrate face of cellular region is provided with groove-shaped area；Groove-shaped area bottom is provided with the second conduction type buried regions area；Remaining area in addition to groove-shaped area for the substrate face of cellular region is provided with the second conductivity type body region；The substrate face of cellular region is provided with the first metal electrode；Substrate back is provided with the second metal electrode.
Wherein, terminal structure is comprised in termination environment, this terminal structure concretely field limiting ring, field limiting ring extra show plate, by knot termination extension (Junction termination extension, JTE) terminal structure of the terminal structure of technology preparation or the preparation of variety lateral doping (VLD) technology etc., in the present embodiment, illustrate taking field limiting ring as a example.Cellular region can comprise thousands of identical structure cells, and the arrangement mode of structure cell can be designed as needed.A kind of schematic top plan view of rectifying device that Fig. 2 provides for the embodiment of the present invention one, as shown in Fig. 2 this rectifying device includes termination environment 201 and cellular region 202, contains multiple structure cells 203 in cellular region 202.Fig. 3 is the schematic cross-section of a structure cell in Fig. 2.
In embodiments of the present invention, the first conduction type concretely N-type, the second conduction type concretely p-type.Accordingly, the partial sectional schematic view of a kind of rectifying device that Fig. 4 provides for the embodiment of the present invention one, as shown in figure 4, this rectifying device includes：N-type substrate 401, cellular region 402 and termination environment 403；The substrate face of cellular region is provided with groove-shaped area 404；Groove-shaped area 404 bottom is provided with p type buried layer area 405；Remaining area in addition to groove-shaped area 404 for the substrate face of cellular region is provided with PXing Ti area 406；The substrate face of cellular region is provided with the first metal electrode 407；Substrate 401 back side is provided with the second metal electrode 408.Wherein, N-type substrate 401 preferably crystal orientation is<100>N-type silicon substrate；First metal electrode 407 and the second metal electrode 408 are preferably metal lead wire.
More specifically, termination environment 403 includes field limiting ring 409；Groove-shaped area 404 includes the groove 4041 being formed at substrate face, is formed at the oxide layer 4042 of trench wall, and the polysilicon 4043 being filled in trench interiors.
Preferably, N-type substrate has the substrate of N-type epitaxy layer 410 for front growth.The thickness range of epitaxial layer 410 can be 2～50um, and the scope of resistivity can be 0.2～20ohm cm.This epitaxial layer 110 can strengthen device resistance to pressure.
Due in rectifying device provided in an embodiment of the present invention actual play rectified action for structure cell, the operation principle of this rectifying device is made an explanation below taking the structure cell shown in Fig. 3 as a example.
First metal electrode can be named as anode, the second metal electrode is named as negative electrode.
Fig. 5 adds operation principle schematic diagram during positive voltage for the anode in the structure cell shown in Fig. 3, and Fig. 6 is the positive operating characteristic simulation curve figure corresponding to Fig. 5.As shown in Figure 5, when anode adds positive voltage, in metal-insulator semiconductor (Metal-Insulator-Semiconductor, MIS) P-type silicon surface transoid in (MOS) structure, form a N-type thin layer, electronics flows from cathode to anode, forms electronic current, now for forward conduction state.
Fig. 7 is the operation principle schematic diagram during anode making alive in the structure cell shown in Fig. 3, and Fig. 8 is the reverse operation characteristic Simulation curve chart corresponding to Fig. 7.As shown in fig. 7, when anode adds negative voltage, using the charge compensation of PN junction and p type buried layer area, forming space-charge region, stopping the movement of carrier, device reverse leakage is less, backward voltage increases.The introducing in p type buried layer area can effectively reduce device inside electric field so that device can bear higher pressure.
The rectifying device that the embodiment of the present invention one provides, including the substrate of the first conduction type, cellular region and termination environment.Wherein, the substrate face of cellular region is provided with groove-shaped area, and groove-shaped area bottom is provided with the second conduction type buried regions area, and the substrate face of the cellular region remaining area in addition to groove-shaped area is provided with the second conductivity type body region.Contain MOS (MIS) structure and PN junction in this rectifying device simultaneously, the advantage of MOS device and PN diode can be combined；And adopt slot type structure, JFET dead resistance will not be produced, that is, without limitation on the reduction of forward conduction voltage drop, also can increase gully density in unit area for the device simultaneously, lower device cost；Second conduction type buried regions area of groove-shaped area bottom can effectively improve blocking voltage.Therefore, this rectifying device is not only simple in structure, and has relatively low forward conduction voltage drop and high blocking voltage, excellent performance.
Embodiment two
The embodiment of the present invention provides a kind of preparation method of rectifying device, and the method includes：Form termination environment in the substrate face of the first conduction type, remaining area in addition to termination environment for the substrate face is cellular region；Form groove-shaped area, the second conduction type buried regions area and the second conductivity type body region in cellular region, wherein, groove-shaped area is located at the substrate face of cellular region, second conduction type buried regions area is located at the bottom in groove-shaped area, remaining area in addition to groove-shaped area for the substrate face located at cellular region for second conductivity type body region；Substrate face in above-mentioned cellular region prepares the first metal electrode；Prepare the second metal electrode in above-mentioned substrate back
Wherein, the order for the preparation process in groove-shaped area, the second conduction type buried regions area and the second conductivity type body region does not limit.Groove-shaped area and the second conduction type buried regions area can first be prepared, then prepare the second conductivity type body region；Also the second conductivity type body region be can first prepare, more groove-shaped area and the second conduction type buried regions area prepared.
Preferably, the substrate of the first conduction type has the substrate of the first conductive type epitaxial layer for front growth.
Preferably, the first conduction type is N-type, and the second conduction type is p-type.
Preferably, the substrate face in the first conduction type forms termination environment, specially：Form p-type field limiting ring in N-type substrate front.
Hereinafter only provide a kind of preferred embodiment.
A kind of schematic flow sheet of the preparation method of rectifying device that Fig. 9 provides for the embodiment of the present invention two.As shown in figure 9, a kind of preparation method of rectifying device provided in an embodiment of the present invention comprises the steps：
S910, offer N-type substrate.
Specifically, using crystal orientation can be<100>N-type silicon substrate.Preferably, in order to strengthen the resistance to pressure of device, there is the substrate of N-type epitaxy layer using front growth.Exemplary, the thickness range of N-type epitaxy layer can be 2～50um, and the scope of resistivity can be 0.2～20ohm cm.
S920, in N-type substrate front formation termination environment, remaining area in addition to termination environment for the substrate face is cellular region.
Exemplary, termination environment includes field limiting ring.Figure 10 is the idiographic flow schematic diagram of S920 in embodiment illustrated in fig. 9 two, and as shown in Figure 10, S920 may particularly include following steps：
S921, p-type field limiting ring is formed using photoetching and ion implantation technology.
Figure 11 is the corresponding cross-sectional view of S921 shown in Figure 10, in order to be contrasted with the partial sectional schematic view of the rectifying device shown in Fig. 4, in Figure 11 and follow-up accompanying drawing, remain the reference of same section in Fig. 4, no longer separately illustrates.Specifically; as shown in figure 11; first gluing (photoresist) can be carried out in substrate face; subsequently using field limiting ring mask plate, substrate face is blocked and be exposed, develop; obtain having effigurate figure photoresist 1101; carry out ion implanting (as boron ion) by the use of this figure photoresist 1101 as masking layer, form p-type terminal protection ring, i.e. p-type field limiting ring 1102.Finally remove figure photoresist 1101.
Preferably, before carrying out gluing, one layer of thin oxide layer 1103 can also be grown, it is possible to decrease implant damage.
S922, grow oxide layer in above-mentioned substrate face, and high temperature is carried out to aforementioned p-type field limiting ring push away trap.
Figure 12 is the corresponding cross-sectional view of S922 shown in Figure 10.Specifically, as shown in figure 12, deposition thickness isThe oxide layer 1201 of (angstrom), and aforementioned p-type field limiting ring 1102 is carried out with high temperature push away trap (knot), form p-type field limiting ring 409.
S930, above-mentioned substrate face formed groove.
Figure 13 is the corresponding cross-sectional view of S930 shown in Fig. 9.Specifically, as shown in figure 13, first gluing can be carried out in above-mentioned substrate face, subsequently using trench mask version, substrate face is blocked and be exposed, develop, obtain having effigurate figure photoresist 1301, carry out oxide layer 1201 by the use of this figure photoresist 1301 as masking layer to etch and silicon etching, form groove (Trench) 4041.
S940, channel bottom formed p type buried layer area.
Figure 14 is the corresponding cross-sectional view of S940 shown in Fig. 9.Specifically, as shown in figure 14, carry out ion implanting by the use of above-mentioned figure photoresist 1301 as masking layer, form p type buried layer area 405.
S950, above-mentioned substrate face generate oxide layer.
S960, in above-mentioned substrate face depositing polysilicon.
Figure 15 is the corresponding cross-sectional view of S950-S960 shown in Fig. 9.Specifically, as shown in figure 15, remove above-mentioned figure photoresist 1301, in above-mentioned substrate face thermal growth oxide layer 1501, wherein, the portion of oxide layer 1501 being grown in above-mentioned trench wall is oxide layer.Then deposit DOPOS doped polycrystalline silicon 1502 again, make polysilicon fill up above-mentioned groove.Carry out ion implanting by the use of above-mentioned figure photoresist 1301 as masking layer, form p type buried layer area 405.
S970, the above-mentioned polysilicon of etching.
Figure 16 is the corresponding cross-sectional view of S970 shown in Fig. 9.Specifically, as shown in figure 16, above-mentioned DOPOS doped polycrystalline silicon 1502 is carried out back carving, leave the polysilicon being filled in above-mentioned groove, this partial polysilicon is polysilicon 4043.
S980, the above-mentioned oxide layer of etching.
Figure 17 is the corresponding cross-sectional view of S980 shown in Fig. 9.Specifically, as shown in figure 17, first gluing can be carried out in above-mentioned substrate face, subsequently substrate face blocked and is exposed, developed using cellular region (active area) mask plate, obtain having effigurate figure photoresist 1701, carry out oxide layer 1201 by the use of this figure photoresist 1701 as masking layer to etch, expose cellular region (active area), and leave the oxide layer 4042 in groove.
S990, the substrate face in the cellular region remaining area in addition to groove-shaped area forms PXing Ti area.
Figure 18 is the corresponding cross-sectional view of S990 shown in Fig. 9.Specifically, as shown in figure 18, above-mentioned figure photoresist 1701 is can be utilized to carry out boron (B) ion implanting twice as masking layer priority, energy is adopted to be 60～120KeV for the first time, dosage is 1e11～1e14, to form PXing Ti area (pbody area), adopts energy 20～40KeV second, dosage is 1e14～1e15, to form good Ohmic contact.Ultimately form PXing Ti area 406.Subsequently, remove figure photoresist 1701.
Preferably, also can carry out quick thermal annealing process afterwards, activate the ion (impurity) of above-mentioned injection.
S9100, the substrate face in above-mentioned cellular region prepare the first metal electrode, prepare the second metal electrode in above-mentioned substrate back.
Specifically, when p-type body surface has oxide layer, oxide layer etching need to be carried out.Subsequently in substrate face splash-proofing sputtering metal, and the techniques such as photoetching, etching formation front metal lead, i.e. the first metal electrode 407 are carried out using metal lithographic mask version；Afterwards reduction processing is done to substrate back, and splash-proofing sputtering metal, the techniques such as photoetching, etching are carried out using metal lithographic mask version and forms back metal lead, i.e. the second metal electrode 408.Ultimately form rectifying device as shown in Figure 4.
The preparation method of the rectifying device that the embodiment of the present invention two provides, forms termination environment in the substrate face of the first conduction type, forms groove-shaped polar region, the second conduction type buried regions area and the second conductivity type body region in cellular region.This preparation method can be compatible with existing complementary metal oxide semiconductors (CMOS) CMOS technology, new equipment need not be increased or production line is adjusted on a large scale, and step is simple, whole technique can be only with 4 lithography mask versions, one time high temperature pushes away trap process, the manufacturing cost of device in the case of not increasing technology difficulty, greatly reduces.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, to those skilled in the art, the present invention can have various change and change.All any modification, equivalent substitution and improvement made within spirit and principles of the present invention etc., should be included within the scope of the present invention.
Claims (10)
1. a kind of rectifying device is it is characterised in that include the substrate of the first conduction type, cellular region and terminal
Area；
The substrate face of described cellular region is provided with groove-shaped area；
Described groove-shaped area bottom is provided with the second conduction type buried regions area；
Remaining area in addition to groove-shaped area for the substrate face of described cellular region is provided with the second conduction type body
Area；
The substrate face of described cellular region is provided with the first metal electrode；
Described substrate back is provided with the second metal electrode.
2. device according to claim 1 is it is characterised in that described groove-shaped area includes being formed at
The groove of described substrate face, is formed at the oxide layer of described trench wall, and is filled in described groove
The polysilicon in portion.
3. device according to claim 1 is it is characterised in that the substrate of described first conduction type
There is the substrate of the first conductive type epitaxial layer for front growth.
4. device according to claim 1 is it is characterised in that described first conduction type is N
Type, described second conduction type is p-type.
5. device according to claim 1 is it is characterised in that described termination environment includes field limiting ring.
6. a kind of preparation method of rectifying device is it is characterised in that include：
Form termination environment in the substrate face of the first conduction type, described substrate face is in addition to described termination environment
Remaining area be cellular region；
Form groove-shaped area, the second conduction type buried regions area and the second conductivity type body region in described cellular region,
Wherein, the substrate face located at described cellular region for the described groove-shaped area, described second conduction type buried regions area sets
In the bottom in described groove-shaped area, the substrate face located at described cellular region for described second conductivity type body region is removed
Remaining area beyond groove-shaped area；
Substrate face in above-mentioned cellular region prepares the first metal electrode；
Prepare the second metal electrode in above-mentioned substrate back.
7. method according to claim 6 it is characterised in that form groove-shaped in described cellular region
Area, the second conduction type buried regions area and the second conductivity type body region, including：
Form groove in described substrate face；
Form the second conduction type buried regions area in described channel bottom；
Form oxide layer in above-mentioned trench wall；
Polysilicon is filled in above-mentioned groove；
Remaining area in addition to groove-shaped area for the substrate face in described cellular region forms the second conduction type body
Area.
8. method according to claim 6 is it is characterised in that the substrate of described first conduction type
There is the substrate of the first conductive type epitaxial layer for front growth.
9. method according to claim 6 is it is characterised in that described first conduction type is N
Type, described second conduction type is p-type.
10. method according to claim 9 it is characterised in that the first conduction type substrate just
Face formation termination environment, specially：
Form p-type field limiting ring in N-type substrate front.
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Application publication date: 20170215 |