CN206412363U - Substrate and epitaxial wafer - Google Patents
Substrate and epitaxial wafer Download PDFInfo
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- CN206412363U CN206412363U CN201621144619.0U CN201621144619U CN206412363U CN 206412363 U CN206412363 U CN 206412363U CN 201621144619 U CN201621144619 U CN 201621144619U CN 206412363 U CN206412363 U CN 206412363U
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- substrate
- silicon layer
- epitaxial
- intrinsic silicon
- layer
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Abstract
The utility model discloses a kind of substrate and epitaxial wafer.The substrate includes substrate bulk and intrinsic silicon layer.The intrinsic silicon layer is laid on the upper surface of the substrate bulk.The epitaxial wafer includes epitaxial layer and substrate.The substrate includes substrate bulk and intrinsic silicon layer.The intrinsic silicon layer is laid on the upper surface of the substrate bulk.The epitaxial layer is laid on the upper surface of the intrinsic silicon layer.The utility model substrate can be separated substrate bulk with epitaxial layer by setting intrinsic silicon layer in the upper surface of substrate bulk, so as to avoid producing auto-dope problem between substrate bulk and epitaxial layer.Thus, the substrate can prevent that the dopant in substrate bulk from entering epitaxial layer, can improve epitaxial layer flat region to improve resistivity evenness.
Description
Technical field
The utility model is related to a kind of semiconductor devices, particularly a kind of substrate and epitaxial wafer.
Background technology
, it is necessary to which epitaxial layer has the crystal structure of better quality for semiconductor devices, and to the thickness of epitaxial layer
There is certain requirement in terms of degree, conduction type, resistivity and resistance homogeneity.And the resistivity of semiconductor is general with temperature
The change of the factors such as degree, doping concentration, magnetic field intensity and intensity of illumination and change.
In semiconductor applications, circuit needs to complete on epitaxial wafer with electronic component, in different applications such as MOS type
PMOS, NMOS, CMOS and ambipolar middle saturation type and unsaturation type.With IC design towards it is light, thin, short, small and save
The development trend of electrification, the product such as Mobile Communications, information household appliances is effected the greatest economy energy resource consumption invariably, for epitaxial wafer class product
It is required that also improving constantly.The change profile of electrical resistivity is solved the problems, such as, can not only meet that epitaxial wafer is light, thin, small, power saving
Development trend, can also improve the utilization rate of road electronic component after epitaxial wafer, effectively the product cost of reduction client.
In epitaxial wafer production process of the prior art, generally existing auto-doping phenomenon.Auto-dope, is due to thermal evaporation
Or diffusion of the accessory substance to substrate of chemical reaction, silicon and impurity in substrate enter gas phase, change the doping in gas phase
Composition and concentration, so that the impurity actual distribution that result in epitaxial layer deviates the phenomenon of ideal situation.By Producing reason, from
Doping can be divided into gas phase auto-dope, solid phase external diffusion and system auto-dope.The dopant of gas phase auto-dope is essentially from wafer
The back side and edge solid phase external diffusion.The dopant of solid phase external diffusion is essentially from the diffusion of substrate, and dopant is in substrate and extension
The contact surface of layer diffuses to epitaxial layer by substrate.The dopant of system auto-dope comes from gas chip, graphite plate and reaction furnace chamber
The inside of body homepitaxy piece process units.It can be seen that by the producing cause of auto-dope, in epitaxial wafer production process, especially gas phase
In the production method of extension, auto-doping phenomenon is difficult to avoid that.
Again because diffusing into one another for the impurity of impurity and epitaxial layer in substrate reduces the resistance homogeneity of epitaxial layer.
How a kind of self-diffusion substrate reduced in epitaxial layer production process is provided, to improve epilayer resistance rate uniformity, one to
It is the problem of being relatively difficult to overcome in the industry.
Fig. 1 shows a kind of epitaxial wafer of the prior art.Due to the influence of auto-dope, generally, 1. locate relative
In outer ring resistivity highest, 2., 3., 4., 5. place takes second place, most edge 6., 7., 8., 9. place resistance it is relatively lower.In addition,
Can also there is a situation where that edge resistivity is higher than close to circle centre position resistivity in some cases.The standard of gauge resistor uniformity
It can be calculated by calculation formula, calculation formula:Resistivity evenness=(MAX-MIN) * 100%/(MAX+MIN), MAX are 9
Maximum resistance rate score in point, MIN is minimum resistance rate score in 9 points.The uniformity calculated by this calculation formula
Numerical value is smaller, then its uniformity is higher, and extension tablet quality is higher.
At present, the resistivity evenness for epitaxial wafer can receive scope less than 5%.And extension of the prior art
Piece, its resistivity evenness is minimum to be also only capable of reaching 2.5%, is produced according to prior art, resistivity evenness numerical value is difficult to again
Reduction.
Utility model content
One of the purpose of this utility model is to overcome deficiency of the prior art to be obtained there is provided a kind of resistivity evenness
To the substrate and epitaxial wafer of lifting.
To realize object above, the utility model is achieved through the following technical solutions：
The utility model provides a kind of substrate.The substrate includes substrate bulk and intrinsic silicon layer.The intrinsic silicon layer paving
On the upper surface for being located at the substrate bulk.The upper surface of the intrinsic silicon layer is used to lay epitaxial layer.
Preferably, the thickness of the intrinsic silicon layer is 0.5-1 μm.
Preferably, the thickness of the intrinsic silicon layer sets the thickness with the substrate bulk to be proportionate.
Preferably, the substrate bulk is N-type.
Preferably, the substrate bulk is doped with least one of arsenic, phosphorus and antimony.
Preferably, the substrate bulk is heavily doped arsenic substrate bulk.
Preferably, the intrinsic silicon layer is reacted by trichlorosilane and hydrogen and generated.
The utility model also provides a kind of epitaxial wafer.The epitaxial wafer includes epitaxial layer and as any one of foregoing
Substrate.The epitaxial layer is laid on the upper surface of the intrinsic silicon layer.
Preferably, the preparation temperature of the epitaxial layer is 1020-1040 DEG C.
Preferably, the growth rate of the epitaxial layer is 0.5-1 μm/min.
The utility model also provides a kind of insulated gate bipolar transistor.The insulated gate bipolar transistor includes described
Epitaxial wafer.The epitaxial wafer includes epitaxial layer and substrate.The substrate includes substrate bulk and intrinsic silicon layer.The intrinsic silicon layer
On the upper surface for being laid on the substrate bulk.The epitaxial layer is laid on the upper surface of the intrinsic silicon layer.
Compared with prior art, the utility model substrate, can be by by setting intrinsic silicon layer in the upper surface of substrate bulk
Substrate bulk is separated with epitaxial layer, so as to avoid producing auto-dope problem between substrate bulk and epitaxial layer.Thus, the substrate
It can prevent the dopant in substrate bulk from entering epitaxial layer, epitaxial layer flat region can be improved to improve resistivity evenness.
In addition, compared to the substrate for being not provided with intrinsic silicon layer, in grown epitaxial layer, the growth rate of intrinsic layer improves 1
Again, temperature can reduce by 20 DEG C, and still be able to produce the higher epitaxial layer of resistance homogeneity.Therefore, using in the utility model
Method production novel substrate, manufacture epitaxial wafer when more save.
The resistivity evenness of the utility model epitaxial layer can be accomplished to be less than 1.5%.It is new compared to this unused practicality
Epilayer resistance rate uniformity in the epitaxial layer of the new epitaxy technology production of type, the utility model can reduce by 1 percentage point.
Use the new epitaxy technology in the utility model, it is possible to decrease subsequent production cost, improve product quality.In addition, the extension
Piece adds flat region SRP curves.
Brief description of the drawings
Fig. 1 is a kind of structural representation of epitaxial wafer of the prior art.
A kind of structural representation for substrate that Fig. 2 provides for the utility model.
A kind of structural representation for epitaxial wafer that Fig. 3 provides for the utility model.
Fig. 4 is extended the curve map of resistance test for the epitaxial wafer shown in Fig. 3.
Embodiment
The utility model is described in detail below in conjunction with the accompanying drawings：
Embodiment one：
Referring to Fig. 2, a kind of its substrate 11 for being provided for the utility model.The substrate 11 is including substrate bulk 1 and originally
Levy silicon layer 2.The intrinsic silicon layer 2 is laid on the upper surface of the substrate bulk 1.The upper surface of the intrinsic silicon layer 2 is used for
Lay following epitaxial layers 3.
The substrate bulk 1, also referred to as substrate.The element that the main body of 3 layers of substrate bulk 1 and extension is constituted is identical, is
Silicon.Dopant mainly has N-type element.N-type element includes arsenic (AS), antimony (Sb) and phosphorus (PH).It that is to say, the substrate bulk 1
Doped with least one of arsenic, antimony and phosphorus.For improving performance, in the present embodiment, the substrate bulk 1 serves as a contrast for heavily doped arsenic
Copy for the record or for reproduction body.It is to be understood that " heavily doped ", i.e. heavy doping, mix relative with light.
The intrinsic silicon layer 2, sheet is made by intrinsic semiconductor.Intrinsic silicon layer 2, can also be referred to as monocrystalline silicon layer.This
Levy semiconductor and refer to and be entirely free of impurity and the pure semiconductor referred to as intrinsic semiconductor without lattice defect.It is understood that real
Border semiconductor can not be utterly pure, and intrinsic semiconductor generally refers to pure half that conduction is mainly determined by the intrinsic excitation of material
Conductor.More generally, complete pure semiconductor is referred to as intrinsic semiconductor or I type semiconductors.Silicon and germanium are all quadrivalent elements,
Its atomic nucleus outermost layer has four valence electrons.They are all, by same atomic building " monocrystal ", to belong to intrinsic semiconductor.
In the present embodiment, the intrinsic silicon layer 2 is reacted by trichlorosilane and hydrogen and generated.That is, the monocrystalline silicon of reaction generation is deposited on
The upper surface of substrate bulk 1 forms the intrinsic silicon layer 2.The specific thickness of the intrinsic silicon layer 2 can be according to following epitaxial wafers 10
General thickness, substrate bulk 1 thickness determine.The thickness of substrate bulk 1 is higher, then intrinsic silicon layer 2 is also thicker, i.e., described intrinsic
The thickness of silicon layer 2 sets the thickness with the substrate bulk 1 to be proportionate.In the present embodiment, the thickness of the intrinsic silicon layer 2
For 0.5-1 μm (micron).The upper surface of the intrinsic silicon layer 2 is used to lay following epitaxial layers 3, that is to say the intrinsic silicon layer 2
Upper surface be used for grown epitaxial layer 3.
Embodiment two：
Referring to Fig. 3, a kind of its epitaxial wafer 10 for being provided for the utility model.The epitaxial wafer 10 include epitaxial layer 3 and
The substrate 11 recorded such as embodiment one.The substrate 11 includes substrate bulk 1 and intrinsic silicon layer 2.The intrinsic silicon layer 2 is spread
On the upper surface for being located at the substrate bulk 1.The epitaxial layer 3 is laid on the upper surface of the intrinsic silicon layer 2.
In order to obtain more uniform resistive performance, the preparation temperature of the epitaxial layer 3 can be 1020-1040 DEG C.
The generating rate of the epitaxial layer 3 is 0.5-1 μm/min ([mu).
Illustrate that the epitaxial wafer 10 compares embodiment with for the setting intrinsic silicon layer 2 below in conjunction with following table
In performance parameter respectively simultaneously under four kinds of preparation methods：
Illustrate, in each group of contrast, two row's substrate bulks 1 from unified batch production.The utility model exists
Laid in the substrate bulk 1 after the intrinsic silicon layer 2, then in the growing epitaxial layers 3 of intrinsic silicon layer 2.Contrast embodiment party
Formula is, the direct growth epitaxial layer in substrate bulk.Outer layer growth technique, the condition all same of above two mode.
Embodiment three：
In the present embodiment, it is in preparation condition one：The preparation temperature of epitaxial layer be all 1020 DEG C, generating rate be
During 0.5 μm/min, the epitaxial wafer 10 and the comparison of contrast embodiment one (the conventional epitaxial piece for being not provided with intrinsic silicon layer)
Obtained following table.
Table 1：
Example IV：
In the present embodiment, it is in preparation condition two：The preparation temperature of epitaxial layer be all 1020 DEG C, generating rate be 1 μ
During m/min, the epitaxial wafer 10 is relatively obtained with contrast embodiment two (the conventional epitaxial piece for being not provided with intrinsic silicon layer)
Following table.
Table 2：
Embodiment five：
In the present embodiment, it is in preparation condition three：The preparation temperature of epitaxial layer be all 1040 DEG C, generating rate be
During 0.5 μm/min, the epitaxial wafer 10 and the comparison of contrast embodiment three (the conventional epitaxial piece for being not provided with intrinsic silicon layer)
Obtained following table.
Table 3：
Embodiment six：
In the present embodiment, it is in preparation condition four：The preparation temperature of epitaxial layer be all 1040 DEG C, generating rate be 1 μ
During m/min, the epitaxial wafer 10 is relatively obtained with contrast embodiment four (the conventional epitaxial piece for being not provided with intrinsic silicon layer)
Following table.
Table 4：
Embodiment seven：
In the present embodiment, when the substrate bulk attaches most importance to p-doped substrate bulk, the epitaxial wafer 10 is in preparation condition
For be 1040 DEG C in the preparation temperature of epitaxial layer, generating rate be 0.5 μm/min (preparation condition three) when, and the epitaxial wafer 10
The preparation temperature that preparation condition is epitaxial layer be all 1040 DEG C, generating rate be 1 μm/min (preparation condition four) when, with contrast
Embodiment 4 (preparation condition four) compares obtained following table.
Table 5：
Note：In table 1- tables 5, point 1- points 9 arrange the resistivity for representing the position corresponding to 9 points as shown in Figure 1 respectively.
AVE row represent the resistivity average value at this nine points.UNI row represent resistance homogeneity, i.e., according to resistivity evenness formula：
The numerical value that resistivity evenness=(MAX-MIN) * 100%/(MAX+MIN) is calculated.
As can be seen from Table 5, when the preparation condition in equally using the utility model produces epitaxial wafer 10,
The more preferable epitaxial layer 3 of resistivity evenness can be obtained under lower temperature and faster growth rate.At that same temperature, make
Preparation method of the present utility model is used, the resistivity evenness than the epitaxial layer 3 manufactured using existing mode is more preferable.
Referring to Fig. 4, its SRP for the epitaxial wafer produced with comparative example 4 of the utility model epitaxial wafer 10
(spreading resistance profile, diffusion resistance technology) figure.Figure 4, it can be seen that the utility model epitaxial wafer
The SRP curves of 10 epitaxial layer 3 are more flat.
By above-mentioned experimental comparison, the utility model epitaxial wafer 10 between substrate bulk 1 and epitaxial layer 3 by setting this
Silicon layer 2 is levied, the dopant in substrate bulk 1 can be enclosed in it, outer delay volatilization can be prevented and auto-doping phenomenon is produced.Nothing
By being p-doped, antimony, or boron-doping, the utility model can play above beneficial effect.Either heavily doped substrate bulk, gently mix lining
Copy for the record or for reproduction body, be respectively provided with improve epilayer resistance uniformity effect, and resistivity evenness data can be reduced at least one hundred
Branch.
The utility model preferred embodiment is these are only, is not used to limit to protection domain of the present utility model, it is any
Modification, equivalent substitution or improvement in the utility model spirit etc., all cover in right of the present utility model.
Claims (9)
1. a kind of substrate, it is characterised in that including substrate bulk and intrinsic silicon layer；The intrinsic silicon layer is laid on the substrate sheet
On the upper surface of body；The upper surface of the intrinsic silicon layer is used to lay epitaxial layer；The thickness of the intrinsic silicon layer is 0.5-1 μm.
2. substrate according to claim 1, it is characterised in that：The thickness of the intrinsic silicon layer is set and the substrate bulk
Thickness be proportionate.
3. substrate according to claim 1, it is characterised in that：The substrate bulk is N-type.
4. substrate according to claim 1, its tagged word is：The substrate bulk doped with arsenic, phosphorus and antimony extremely
Few one kind.
5. substrate according to claim 1, it is characterised in that：The substrate bulk is heavily doped arsenic substrate bulk or heavily doped phosphorus
Substrate bulk.
6. substrate according to claim 1, it is characterised in that：The intrinsic silicon layer is reacted by trichlorosilane and hydrogen gives birth to
Into.
7. a kind of epitaxial wafer, it is characterised in that the substrate including epitaxial layer and as any one of claim 1 to 6；It is described
Epitaxial layer is laid on the upper surface of the intrinsic silicon layer.
8. epitaxial wafer according to claim 7, it is characterised in that：The preparation temperature of the epitaxial layer is 1020-1040 DEG C.
9. epitaxial wafer according to claim 7, it is characterised in that：The growth rate of the epitaxial layer is 0.5-1 μm/min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621144619.0U CN206412363U (en) | 2016-10-21 | 2016-10-21 | Substrate and epitaxial wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621144619.0U CN206412363U (en) | 2016-10-21 | 2016-10-21 | Substrate and epitaxial wafer |
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| Publication Number | Publication Date |
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| CN206412363U true CN206412363U (en) | 2017-08-15 |
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ID=59549195
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| Application Number | Title | Priority Date | Filing Date |
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| CN201621144619.0U Active CN206412363U (en) | 2016-10-21 | 2016-10-21 | Substrate and epitaxial wafer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111415864A (en) * | 2020-03-18 | 2020-07-14 | 上海晶盟硅材料有限公司 | Super-heavy red phosphorus doped substrate epitaxy method |
-
2016
- 2016-10-21 CN CN201621144619.0U patent/CN206412363U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111415864A (en) * | 2020-03-18 | 2020-07-14 | 上海晶盟硅材料有限公司 | Super-heavy red phosphorus doped substrate epitaxy method |
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