EP1198838A1

EP1198838A1 - Protective structure against electrostatic discharges

Info

Publication number: EP1198838A1
Application number: EP00958220A
Authority: EP
Inventors: Harald Gossner
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 1999-08-04
Filing date: 2000-08-03
Publication date: 2002-04-24
Also published as: US6713841B2; DE19936636A1; US20020096722A1; WO2001011684A1

Abstract

The invention concerns a protective structure against electrostatic discharges (ESD), designed for integrated circuits.

Description

description

ESD protection

The _E rfindung relates to an ESD protection structure for an integrated circuit according to the preamble of claim. 1

A generic ESD protective structure is m "Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS / Bipolar Circuits", J. Chen, X. Zhang, A. erasekera and T. Vrotsos, Proceedmgs of the IEEE IRPS (1996) , Pp. 227 ff.

Circuits integrated in a chip contain protective structures to protect the inputs or outputs (I / O ports) against electrostatic overvoltages and the resulting electrostatic discharge (ESD). These ESD protection structures are arranged between the input pad of the integrated circuit and the input or output connections to be protected and ensure that when a parasitic overvoltage is coupled in, the ESD protection structure switches through and the parasitic overvoltage pulse is derived. In extreme cases, such overvoltage pulses can lead to the destruction of the integrated circuit.

With the ever increasing structure jamming in semiconductor technology, however, it is becoming increasingly difficult to provide ESD protective structures which recognize such a parasitic overvoltage pulse. In the case of current and future CMOS technologies in particular, it is very important due to the small window width between operating voltage and breakdown voltage of the circuit elements of the integrated circuits that the corresponding ESD protection structures are defined and reproducibly switched on in a very narrowly specified voltage range. In the article by Chen et al. and m 1 is indicated a gattungsgemaße ESD protection structure, _b ei of the protective element urchbruchdiode by a series circuit of a _D and a resistor is triggered. FIG. 1 shows an integrated circuit 1 which is connected to a connection pad 3 via a connecting line 2. An ESD protection structure 4 is arranged between the connection pad 3 and the integrated circuit 1. The ESD protective structure 4 m in FIG. 1 consists of a protective transistor 5, the load path of which is connected between the connecting line 2 and a connection 6 which is supplied with a reference potential VSS. A series circuit consisting of a trigger diode 7 and a resistor 8 is connected in parallel with the load path of the protective transistor 5. The center tap 9 of this Seπenschaltung is with the control connection of

Protection transistor 5 connected. If the voltage applied to the connection pad 3 exceeds the breakdown voltage of the trigger diode 7, the control terminal of the protective transistor 6 is controlled via the potential at the center tap 9 in such a way that the protective transistor 5 and thus the protective structure 4 are switched on.

However, the problem with this is the production of such a trigger diode, which has a breakdown voltage that is as definable and reproducible as possible. In addition, the value of the breakdown voltage must not fluctuate too much with various ESD protective structures.

Another requirement is that the trigger diode may have the lowest possible leakage current when switched off.

An n + / p + zener diode is therefore often used as the trigger diode. With such a trigger diode, very low breakdown voltages can be achieved, but a very high leakage current is undesirably generated. In contrast, trigger diodes have low doped p ⁺ components and / or n ⁺ units and thus have lower leakage currents, very high breakdown voltage values.

Another problem is that the breakdown voltage values of the trigger diodes can generally only be set via the doping concentrations, which sometimes interferes very strongly with the functionality of the other circuit elements (left protective transistor, resistor) of the ESD protective structure.

Lateral trigger diodes are therefore often used, which are generated by adjusting the p ⁺ regions relative to the corresponding n ⁺ regions, which are arranged at a short distance from one another. With such lateral trigger diodes, the breakdown voltage can be set in a simple manner exclusively by means of layout measures. However, due to the limited adjustment accuracy of these layout measures, undesirable or unacceptable fluctuations in the breakdown voltage generally occur.

Based on this prior art, the present invention is therefore based on the object of providing an ESD protective structure of the type mentioned at the beginning, the trigger diode of which has the lowest possible breakdown voltage with a simultaneously low leakage current. Furthermore, the breakdown voltage of this trigger diode should be adjustable as defined as possible and should not be subject to excessive fluctuations.

According to the invention, this object is achieved by an ESD protective structure with the features of patent claim 1 and by a method for producing such an ESD protective structure with the features of patent claim 9.

The inventive ESD protective structure has a self-aligned, lateral p ⁺ / n ⁺ diode as a trigger diode. This lateral trigger diode is nearly independent of CANDIES Justiergenau ^¬. The n ⁺ and p ⁺ units are implanted on opposite sides of a gate electrode. The edges of the lacquer asks of the respective process diffusions are placed on this gate electrode in such a way that they always lie on the gate electrode within the limits of the adjustment possibilities. In this way, the distance between the n ⁺ unit and the p ⁺ unit is given only by the gate electrode length or width, which are very easy to control. This procedure is only limited by the fact that the minimum gate electrode length must not be less than twice the maximum adjustment inaccuracy in order to meet the above-mentioned conditions.

The value of the breakdown voltage can be exactly determined or reproduced using the ESD protection structure according to the invention or the layout method according to the invention for producing the trigger diode of this ESD protection structure.

The particular advantage of the invention is that the

Gate electrode is used to a certain extent as a "spacer" between the p ⁺ regions and n ⁺ regions of the trigger diode. This trigger diode thus produced then serves as a trigger element for the ESD protective structure.

A switching transistor, which can be bipolar or CMOS technology, is typically used as the switching element for the ESD protective structure. It would of course also be conceivable for the protective element to be designed as a Thyπ-disturbance.

In an advantageous embodiment of the invention, the breakdown voltage of the trigger diode can also be influenced additionally by means of a suitable gate electrode circuit.

Advantageous refinements and developments are the characteristics of the further dependent claims. The invention is explained in more detail below with reference to the exemplary embodiments given in the figures of the drawing. It shows:

Figure 1 shows a known ESD protection structure for an integrated circuit;

Figure 2 is a schematic representation of the inventive method for producing a self-adjusting

Trigger diode of the ESD protective structure according to the invention;

Figure 3 is a schematic representation of the implementation of an ESD protection structure, which is designed as a thyristor with self-adjusting trigger diode.

Identical or functionally identical elements are provided with the same reference symbols in all the figures of the drawing.

FIG. 2 shows a schematic illustration of the method according to the invention for producing a self-adjusting trigger diode for an ESD protective structure according to the invention;

In FIG. 2, a section of a semiconductor body is designated by 10 em. In the present exemplary embodiment, the semiconductor body 10 consists of doped silicon substrate. A gate electrode 12 is arranged on the surface 11.

The gate electrode 12 is typically rectangular or in the form of a conductor track. It would of course also be conceivable for the gate electrode 12 to be circular, hexagonal, etc. The gate electrode 12 is typically designed as a polysilicon gate electrode. It would of course also be conceivable for the gate electrode 12 to be formed, for example, from metal or metal silicide electrodes UJ L0)> t- ¹ P ¹

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17 generated. The second photoresist mask 14b is then detached again from the surface 11 of the semiconductor body 10 by a suitable etching process.

The doping concentrations of zones 16, 17 can be specifically adjusted via the implantation dose, the depth of zones 16, 17 via the implantation energy.

In the region of the gate electrode 12 and the photoresist masks 14a, 14b, the p-doping atoms do not get into the semiconductor body 10, but remain stuck in the corresponding photoresist of the photoresist masks 14a, 14b or the polysilicon of the gate electrode 12. It is only necessary to ensure that the thicknesses of the gate electrode 12 and the photoresist mask 14 are chosen to be sufficiently thick.

In this way, a trigger diode is produced (see sub-figure 2c), which has a heavily n-doped cathode zone 17 and a heavily p-doped anode zone 16. These two zones 16, 17 have been manufactured with respect to the edges of the gate electrode 12. The two zones 16, 17 are thus spaced apart, the distance L of these two zones 16, 17 essentially corresponding to the corresponding length of the gate electrode 12. The gate electrode 12 thus corresponds to a certain extent to a "spacer" between the anode zone 16 and the cathode zone 17. This trigger diode can then be used as a trigger element for the ESD protective structure. The precisely definable distance L ensures an exactly adjustable breakdown voltage of the trigger diode and thus the ESD protection structure.

FIG. 3 shows a partial section of a schematic representation of the implementation of an ESD protective structure according to the invention, consisting of a thyristor 5a, which is controlled by a trigger diode 3. An n-doped well 20 is arranged in the p-doped substrate of the semiconductor body 10. A first p ⁺ -doped zone 21 is embedded in the tub on the surface 11 of the semiconductor body 10. Furthermore, an n ⁺ -doped cathode zone 17 and a first n ⁺ -doped zone 22 are in this way

Surface 11 of the semiconductor body 10 embedded that they are connected both to the well 21 and to the p-substrate of the semiconductor body 10. Furthermore, a second n ⁺ -doped zone 23 and a second p ⁺ -doped zone 24 are embedded in the semiconductor body 10.

Between the zones 22, 23 there is a channel zone 25 which can be controlled via a channel control electrode.

The zones 23, 24 are each connected to the terminal 6 and thus to the reference potential VSS. The zones 17, 21 are each connected to the connection pad 3. The zones 17, 20, 21, 22, 23, 24 form the thyristor 5a of the ESD protection structure. The anode zone 16, which is connected to the gate electrode, and the cathode zone 17 form the trigger diode, which drives the thyristor.

The mode of operation of the ESD protective structure according to the invention according to FIG. 3 is explained in more detail below.

If an interference signal is coupled in via the connection pad 3 and this interference signal exceeds the breakdown voltage of the trigger diode 7, then this trigger diode 7 controls the control transistor of the thyristor 5a in such a way that the space charge zone at the pn junction of the control transistor connected in diode circuit exists together and the control transistor switches through. As a result, the base connection of the switching transistor of the thyristor 5a is driven in such a way that it is also turned on when the drive current is sufficiently high. This results in a current path from the connection pad 3 via the cathode zone 17, the tub 21, the zone 22, the channel 25 to zone 23 and thus to terminal 6. The interference signal is thus derived from terminal 6 and thus the reference potential VSS and thus does not reach the integrated circuit 1.

The ESD protection structure according to the invention is particularly suitable in a complex integrated circuit, such as. B. a microcontroller, a semiconductor memory or a logic component. The integrated circuit and the associated ESD protective structure are preferably implemented in a bipolar manner or are produced using smart power technology. However, it is also particularly advantageous if the integrated circuit and the ESD protective structure are produced using CMOS technology.

Claims

claims

1. ESD protective structure for protecting integrated circuits,

with a protective element, the load path of which is connected between a connection pad which is connected to the integrated circuit via an electrically conductive connection and a connection which has a reference potential,

with a laterally formed trigger diode which is arranged between the control connection of the protective element and the connection pad and which switches through the protective element when a breakdown voltage is exceeded,

- with a gate electrode,

characterized ,

that the lateral trigger diode has an anode zone and a cathode zone, the anode zone and the cathode zone being adjusted with respect to the gate electrode and the distance between the anode zone and cathode zone corresponding to the width or length of the gate electrode.

2. ESD protection structure according to claim 1, that the protection element is designed as a thyristor or as a transistor.

3. ESD protection structure according to one of claims 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the trigger diode is designed as a zener diode with a low breakdown voltage.

4. ESD protective structure according to one of claims 1 or 2, characterized in that the trigger diode as a PIN diode switch is formed by low ^¬ breakdown voltage.

5. ESD protection structure according to one of the preceding claims, that the length or the width is at least as large as twice the maximum adjustment inaccuracy.

6. ESD protective structure according to one of the preceding claims, that the gate electrode is connected to circuit means by means of which the breakdown voltage of the trigger diode can be changed.

7. ESD protection structure according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the gate electrode consists at least partially of polysilicon.

8. ESD protective structure according to one of the preceding claims, that the anode zone and the cathode zone each have very high doping concentrations.

9. A method for producing an ESD protective structure according to one or more of the preceding claims with the following method steps:

a) A semiconductor body, on the surface of which a gate electrode is arranged, is provided;

b) A part of the surface is structured in such a way that a mask edge is arranged directly above the gate electrode; c) In the unstructured areas of the surface

Introduced dopants of the first conductivity type and then the mask is removed again;

d) The surface of the semiconductor body is patterned again, the mask being arranged on respective other areas of the surface and the edge of the mask being arranged above the gate electrode;

e) dopants of the second conductivity type are introduced into the semiconductor body and then the mask is removed again;

10. The method according to claim 9, d a d u r c h g e k e n n z e i c h n e t that the introduction of the dopants takes place via ion implantation.

11. The method according to any one of claims 9 or 10, that the structure mask is generated by a lithography process and at least partially contains a photoresist.