CN210182384U - Novel four diode integrated chips - Google Patents
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- CN210182384U CN210182384U CN201920611005.6U CN201920611005U CN210182384U CN 210182384 U CN210182384 U CN 210182384U CN 201920611005 U CN201920611005 U CN 201920611005U CN 210182384 U CN210182384 U CN 210182384U
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Abstract
A novel four-diode integrated chip; the boron-doped silicon wafer comprises a silicon wafer substrate, a first P + region is formed by first-time boron impurity doping, a separation wall is formed by penetrating through the silicon wafer substrate in the vertical direction, and four separation blocks are separated from the silicon wafer substrate; the upper surface and the lower surface of each spacing block are doped with phosphorus impurities to form an N + region, or doped with boron impurities for the second time to form a second P + region; the areas of the N + region and the second P + region are smaller than the upper or lower area of the spacing block, and the N + region and the second P + region are arranged at intervals with the first P + region in the horizontal direction; a groove is formed in the edge area of the second P + area; a polycrystalline silicon passivation composite film layer covers the peripheral area of the N + area, the peripheral area of the second P + area and the surface of the groove on the silicon wafer substrate; glass cement is filled in the groove, and a glass passivation layer is formed through high-temperature sintering; and metal layers are deposited on the surfaces of the N + region and the second P + region to form metal electrodes. The utility model has the advantages of simple process, high integration level, small volume, high quality and the like.
Description
Technical Field
The utility model relates to a diode manufacturing process, concretely relates to novel four diode integrated chips.
Background
The diode is widely used in various circuits, and the diodes are arranged at any circuit, so that alternating current is converted into direct current by utilizing the characteristic of unidirectional conduction, and a terminal component of the circuit can obtain stable direct current input. The existing manufacturing method of rectifier diode is to use N-type < 111 > crystal orientation monocrystalline silicon wafer as basic material, to perform boron doping on the upper surface of the silicon wafer to form a flat P region, then to perform phosphorus diffusion on the lower surface to form a flat N region, and then to perform the processes of photo-etching, metallization, alloy, etc. to finally form the PN structure and electrode metal of the diode, so as to manufacture the rectifier diode.
The defects of the prior art include:
when a bridge rectifier circuit is required to be formed, four independent diodes are usually required to be electrically connected, so that the miniaturization of a product is not facilitated, the process flow is complex, and the manufacturing cost is high;
secondly, the existing diode structure has leakage current of the side wall, and the reliability of the device is low;
and thirdly, the conventional diode is reversely cut off and forwardly conducted in the working process, and the diode continuously generates heat due to the forward voltage drop of the conventional diode in the forward current conducting process, wherein P = U × I (U is the forward voltage drop, and I is the current representing normal working). The part of power consumption generated by the diode not only influences the reliability and the service life of the device due to continuous heating, but also consumes a large amount of useless energy, which is beyond the requirement of environmental protection of green energy conservation at present.
Therefore, how to solve the above-mentioned deficiencies of the prior art is a problem to be solved by the present invention.
Disclosure of Invention
The utility model aims at providing a novel four diode integrated chip.
In order to achieve the above purpose, the utility model adopts the technical scheme that:
a novel four-diode integrated chip comprises a silicon chip substrate, wherein a first P + region or a first N + region is formed in the silicon chip substrate through first impurity doping for the first time, the first P + region or the first N + region penetrates through the silicon chip substrate in the vertical direction to form a separation wall, and four spacing blocks which are horizontally arranged at intervals are separated in the silicon chip substrate;
the upper surface and the lower surface of each spacer block are doped with second impurities to form an N + region or a P + region, or doped with second first impurities for the second time to form a second P + region or a second N + region, and the upper surface and the lower surface of the silicon wafer substrate are both formed with two parallel N + regions or P + regions and two parallel second P + regions or second N + regions;
the two N + regions on the upper surface and the two N + regions on the lower surface are arranged at intervals in the horizontal direction and the vertical direction, or the two P + regions on the upper surface and the two P + regions on the lower surface are arranged at intervals in the horizontal direction and the vertical direction;
the two second P + regions on the upper surface and the two second P + regions on the lower surface are arranged at intervals in the horizontal direction and the vertical direction, or the two second N + regions on the upper surface and the two second N + regions on the lower surface are arranged at intervals in the horizontal direction and the vertical direction;
the N + region on the upper surface and the second P + region on the lower surface are aligned in the vertical direction and are arranged at intervals, or the P + region on the upper surface and the second N + region on the lower surface are aligned in the vertical direction and are arranged at intervals;
the N + region on the lower surface and the second P + region on the upper surface are aligned in the vertical direction and arranged at intervals, or the P + region on the lower surface and the second N + region on the upper surface are aligned in the vertical direction and arranged at intervals;
the areas of the N + region and the second P + region or the areas of the P + region and the second N + region are smaller than the upper surface area or the lower surface area of the spacing block, the N + region and the second P + region are arranged at intervals with the first P + region in the horizontal direction, or the P + region and the second N + region are arranged at intervals with the first N + region;
the edge area of the second P + area or the second N + area is provided with a groove;
a polycrystalline silicon passivation composite film layer covers the peripheral area of the N + area or the P + area, the peripheral area of the second P + area or the second N + area and the surface of the groove on the silicon wafer substrate; glass cement is filled in the groove, and a glass passivation layer is formed through high-temperature sintering;
and metal layers are deposited on the surfaces of the N + region or the P + region and the second P + region or the second N + region to form metal electrodes.
The relevant content in the above technical solution is explained as follows:
1. in the above scheme, the silicon wafer substrate is in an N-type < 111 > crystal orientation, the first impurity doping is boron impurity doping or gallium impurity doping, and the second impurity doping is phosphorus impurity doping or arsenic impurity doping;
the first-time first impurities are doped in the isolation belt regions on the upper surface and the lower surface of the silicon wafer substrate to form first P + regions; the second impurities are doped in four first doping regions of the silicon wafer substrate to form N + regions respectively; the second time of first impurity doping forms second P + regions in four second doping regions of the silicon wafer substrate respectively;
the groove is formed in the edge area of the second P + area.
2. In the above scheme, the silicon wafer substrate has an N-type < 111 > crystal orientation, the first P + region is cross-shaped, and the silicon wafer substrate is horizontally isolated into four spacer blocks arranged in a shape of a Chinese character tian.
The distance between the N + region and the second P + region and the first P + region is 200-300 um.
The surface of the N + region has a doping concentration of at least 1021atm/cm3The diffusion depth is 30-50 μm; the surface of the second P + region has a doping concentration of at least 1021atm/cm3The diffusion depth is 50 to 70 μm.
In the later packaging process, the metal electrodes corresponding to the N + region and the second P + region on different diode particles (spacer blocks) are connected through pins, so that the diode becomes a full-bridge rectification product, or becomes a half-bridge and two diodes.
3. In the above scheme, the silicon wafer substrate is in a P-type < 111 > crystal orientation, the first impurity doping is phosphorus impurity doping or arsenic impurity doping, and the second impurity doping is boron impurity doping or gallium impurity doping;
the first time first impurities are doped in the isolation belt regions on the upper surface and the lower surface of the silicon wafer substrate to form first N + regions; the second impurities are doped in four first doping regions of the silicon wafer substrate to form P + regions respectively; the second time of first impurity doping forms second N + regions in four second doping regions of the silicon wafer substrate respectively;
the groove is formed in the edge area of the second N + area.
4. In the above solution, the silicon wafer substrate is in a P-type < 111 > crystal orientation, the first N + region is cross-shaped, and the silicon wafer substrate is horizontally isolated into four spacer blocks arranged in a shape of a Chinese character tian.
The distance between the P + region and the second N + region and the first N + region is 200-300 um.
The surface of the P + region has a doping concentration of at least 1021atm/cm3The diffusion depth is 50-70 μm; the surface of the second N + region has a doping concentration of at least 1021atm/cm3The diffusion depth is 30 to 50 μm.
In the later packaging process, the P + regions and the metal electrodes corresponding to the second N + regions on different diode particles (spacer blocks) are connected through pins, so that the diode becomes a full-bridge rectification product, or becomes a half-bridge and two diodes.
5. In the above scheme, the depth of the groove is 20-40 um.
6. In the scheme, the thickness of the glass cement is 25-35 mu m.
7. In the scheme, the polycrystalline silicon passivation composite film layer is formed by deposition through a CVD (chemical vapor deposition) process, and the process conditions are as follows: firstly, introducing silane gas and nitrous oxide gas at the temperature of 650 +/-1 ℃ for 25 +/-1 minutes, wherein the flow rate of the silane gas is 130 +/-5 ml per minute, and the flow rate of the nitrous oxide gas is 30 +/-2 ml per minute; then, silane gas and nitrous oxide gas are continuously introduced at the temperature of 780 +/-1 ℃ for 15 +/-0.5 minutes, and the flow rates of the two gases are SiH respectively425. + -. 5ml and N per minute2O is 80 plus or minus 5ml per minute; finally, the polycrystalline silicon passivation composite film layer of the oxygen-containing polycrystalline silicon passivation film and the silicon dioxide film is formed.
The utility model discloses a theory of operation and advantage as follows:
the utility model relates to a novel four diode integrated chips; the silicon wafer substrate is provided with a first P + region or a first N + region through first impurity doping for the first time, a separation wall is formed by penetrating through the silicon wafer substrate in the vertical direction, and four spacing blocks are separated from the silicon wafer substrate; the upper surface and the lower surface of each spacing block are doped by second impurities to form an N + region or a P + region, or doped by second first impurities to form a second P + region or a second N + region; the areas of the N + region and the second P + region or the areas of the P + region and the second N + region are smaller than the upper or lower surface area of the spacing block, the N + region and the second P + region are arranged at intervals with the first P + region in the horizontal direction, or the P + region and the second N + region are arranged at intervals with the first N + region; a groove is formed in the edge area of the second P + area or the second N + area; a polycrystalline silicon passivation composite film layer covers the surfaces of the peripheral area of the N + area or the P + area, the peripheral area of the second P + area or the second N + area and the groove on the silicon wafer substrate; glass cement is filled in the groove, and a glass passivation layer is formed through high-temperature sintering; and metal layers are deposited on the surfaces of the N + region or the P + region and the second P + region or the second N + region to form metal electrodes.
Compared with the prior art, the utility model has the advantages that:
the method comprises the following steps that firstly, a U-shaped PN junction is formed through selective diffusion, so that the effective area of the PN junction is increased, and the power consumption of a diode in the application of a circuit is obviously reduced;
secondly, a method combining chemical vapor deposition passivation and glass passivation is adopted, so that the leakage current of the side wall is reduced, and the reliability of the device is improved;
the process flow is simple, the consumption of chemicals is low, the forward power consumption is low, and the effects of low manufacturing cost and high quality are realized;
and fourthly, a shallow trench of 20-40 um is adopted, a PN junction passivation design of the diode with glass is adopted, the four diodes are integrated in the same silicon wafer substrate, the integration level is improved, and the volume of the device can be greatly reduced.
In addition, the utility model discloses an aspect is different from conventional planar technology, and conventional planar technology can only accomplish 600V generally, if need reach more than 800 or 1000V then need complicated technology, realize through a plurality of partial pressure rings promptly, need bigger chip area and complicated technological process, and the processing cost need double at least and can accomplish; on the other hand, the method is different from the conventional groove process of 100-140 microns, the conventional groove process needs more than 3 times of chemicals to corrode a deep groove, the probability of impurity contamination is increased by adopting a large-area glass passivation method, leakage current is high, and the deep groove can cause the problems of silicon wafer warping, increase in the wafer breakage rate in the process and the like.
Compared with the traditional diode chip structure, the utility model discloses can accomplish to simplify the encapsulation by a wide margin to can reduce material cost, labour cost, be favorable to reducing big diode semiconductor device's in batches processing cost, realize can reduce 30% processing cost at most, and can promote unit interval's production efficiency. The method can also reduce the use energy consumption of the client, is more favorable for reducing the waste of resources (the consumption of materials such as resin, soldering tin, copper leads and the like is avoided), and contributes to environmental protection.
Drawings
FIG. 1 is a schematic cross-sectional structure diagram of an embodiment of the present invention;
fig. 2 is a schematic structural diagram (top view) of an embodiment of the present invention.
In the above drawings: 1. a silicon wafer substrate; 2. a first P + region; 3. a spacer block; an N + region; 5. a second P + region; 6. a trench; 7. passivating the composite film layer by polycrystalline silicon; 8. a glass passivation layer; 9. a metal layer; d. distance.
Detailed Description
The invention will be further described with reference to the following drawings and examples:
example (b): referring to fig. 1 and 2, a novel four-diode integrated chip includes a silicon substrate 1, where the silicon substrate 1 can select an N-type < 111 > crystal orientation or a P-type < 111 > crystal orientation, and the embodiment takes the N-type < 111 > crystal orientation as an example for explanation.
A first P + region 2 is formed in the silicon wafer substrate 1 through first boron impurity doping (gallium impurity doping is also available), the first P + region 2 penetrates through the silicon wafer substrate 1 in the vertical direction to form a separation wall, and four spacing blocks 3 which are horizontally arranged at intervals are separated in the silicon wafer substrate 1; the first P + area 2 is in a cross shape, and separates the silicon wafer substrate 1 into four spacing blocks 3 which are arranged in a shape like a Chinese character 'tian' in the horizontal direction.
The upper surface and the lower surface of each spacer block 3 are doped with phosphorus impurities (or arsenic impurities) to form an N + region 4, or doped with boron impurities (or gallium impurities) for the second time to form a second P + region 5, and the upper surface and the lower surface of the silicon wafer substrate 1 are both formed with two N + regions 4 arranged side by side and two second P + regions 5 arranged side by side;
the two N + regions 4 on the upper surface and the two N + regions 4 on the lower surface are arranged at intervals in the horizontal direction and the vertical direction; the two second P + regions 5 on the upper surface and the two second P + regions 5 on the lower surface are arranged at intervals in the horizontal direction and the vertical direction; the N + region 4 on the upper surface and the second P + region 5 on the lower surface are aligned in the vertical direction and are arranged at intervals; the N + region 4 on the lower surface and the second P + region 5 on the upper surface are aligned in the vertical direction and are arranged at intervals;
the areas of the N + region 4 and the second P + region 5 are both smaller than the upper surface area or the lower surface area of the spacer block 3, and the N + region 4 and the second P + region 5 are both arranged at intervals with the first P + region 2 in the horizontal direction; the distances d between the N + region 4 and the first P + region 2 and between the second P + region 5 and the first P + region 2 are both 200-300 um.
Wherein, the edge region of the second P + region 5 is provided with a groove 6; the depth of the groove 6 is 20-40 um.
A polycrystalline silicon passivation composite film layer 7 covers the peripheral area of the N + area 4, the peripheral area of the second P + area 5 and the surface of the groove 6 on the silicon wafer substrate 1; the groove 6 is also filled with glass cement, the thickness of the glass cement is 25-35 mu m, and a glass passivation layer 8 is formed through high-temperature sintering;
and metal layers 9 are deposited on the surfaces of the N + region 4 and the second P + region 5 to form metal electrodes.
The surface of the N + region 4 has a doping concentration of at least 1021atm/cm3The diffusion depth is 30-50 μm; the doping concentration of the surface of the second P + region 5 is at least 1021atm/cm3The diffusion depth is 50 to 70 μm.
The polycrystalline silicon passivation composite film layer 7 is formed by deposition through a CVD (chemical vapor deposition) process, and the process conditions are as follows: firstly, introducing silane gas and nitrous oxide gas at the temperature of 650 +/-1 ℃ for 25 +/-1 minutes, wherein the flow rate of the silane gas is 130 +/-5 ml per minute, and the flow rate of the nitrous oxide gas is 30 +/-2 ml per minute; then, silane gas and nitrous oxide gas are continuously introduced at the temperature of 780 +/-1 ℃ for 15 +/-0.5 minutes, and the flow rates of the two gases are SiH respectively425. + -. 5ml and N per minute2O is 80 plus or minus 5ml per minute; finally, a polysilicon passivation composite film layer 7 of an oxygen-containing polysilicon passivation film and a silicon dioxide film is formed.
In the later packaging process, the metal electrodes corresponding to the N + region 4 and the second P + region 5 on different diode particles (spacer 3) are connected through pins, so that the diode becomes a full-bridge rectification product or a half-bridge and two diodes product.
The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable people skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.
Claims (10)
1. A novel four diode integrated chip which is characterized in that: the silicon wafer substrate is internally provided with a first P + region or a first N + region through first impurity doping for the first time, the first P + region or the first N + region penetrates through the silicon wafer substrate in the vertical direction to form a separation wall, and four spacing blocks which are horizontally arranged at intervals are separated in the silicon wafer substrate;
the upper surface and the lower surface of each spacer block are doped with second impurities to form an N + region or a P + region, or doped with second first impurities for the second time to form a second P + region or a second N + region, and the upper surface and the lower surface of the silicon wafer substrate are both formed with two parallel N + regions or P + regions and two parallel second P + regions or second N + regions;
the two N + regions on the upper surface and the two N + regions on the lower surface are arranged at intervals in the horizontal direction and the vertical direction, or the two P + regions on the upper surface and the two P + regions on the lower surface are arranged at intervals in the horizontal direction and the vertical direction;
the two second P + regions on the upper surface and the two second P + regions on the lower surface are arranged at intervals in the horizontal direction and the vertical direction, or the two second N + regions on the upper surface and the two second N + regions on the lower surface are arranged at intervals in the horizontal direction and the vertical direction;
the N + region on the upper surface and the second P + region on the lower surface are aligned in the vertical direction and are arranged at intervals, or the P + region on the upper surface and the second N + region on the lower surface are aligned in the vertical direction and are arranged at intervals;
the N + region on the lower surface and the second P + region on the upper surface are aligned in the vertical direction and arranged at intervals, or the P + region on the lower surface and the second N + region on the upper surface are aligned in the vertical direction and arranged at intervals;
the areas of the N + region and the second P + region or the areas of the P + region and the second N + region are smaller than the upper surface area or the lower surface area of the spacing block, the N + region and the second P + region are arranged at intervals with the first P + region in the horizontal direction, or the P + region and the second N + region are arranged at intervals with the first N + region;
the edge area of the second P + area or the second N + area is provided with a groove;
a polycrystalline silicon passivation composite film layer covers the peripheral area of the N + area or the P + area, the peripheral area of the second P + area or the second N + area and the surface of the groove on the silicon wafer substrate; glass cement is filled in the groove, and a glass passivation layer is formed through high-temperature sintering;
and metal layers are deposited on the surfaces of the N + region or the P + region and the second P + region or the second N + region to form metal electrodes.
2. The chip of claim 1, wherein: the silicon wafer substrate is in an N-type < 111 > crystal orientation, the first impurity doping is boron impurity doping or gallium impurity doping, and the second impurity doping is phosphorus impurity doping or arsenic impurity doping;
the first-time first impurity is doped in isolation belt regions on the upper surface and the lower surface of the silicon wafer substrate to form first P + regions; the second impurities are doped in four first doping regions of the silicon wafer substrate to form N + regions respectively; the second time of first impurity doping forms second P + regions in four second doping regions of the silicon wafer substrate respectively;
the groove is formed in the edge area of the second P + area.
3. The chip of claim 1, wherein: the silicon wafer substrate is in a P-type < 111 > crystal orientation, the first impurity doping is phosphorus impurity doping or arsenic impurity doping, and the second impurity doping is boron impurity doping or gallium impurity doping;
the first time first impurities are doped in isolation belt regions of the upper surface and the lower surface of the silicon wafer substrate to form first N + regions; the second impurities are doped in four first doping regions of the silicon wafer substrate to form P + regions respectively; the second time of first impurity doping forms second N + regions in four second doping regions of the silicon wafer substrate respectively;
the groove is formed in the edge area of the second N + area.
4. The chip of claim 2, wherein: the first P + area is in a cross shape and separates the silicon wafer substrate into four spacing blocks which are arranged in a shape like a Chinese character tian in the horizontal direction.
5. The chip of claim 2, wherein: the surface of the N + region has a doping concentration of at least 1021atm/cm3The diffusion depth is 30-50 μm; the surface of the second P + region has a doping concentration of at least 1021atm/cm3The diffusion depth is 50 to 70 μm.
6. The chip of claim 2, wherein: the distance between the N + region and the second P + region and the distance between the first P + region are both 200-300 um.
7. The chip of claim 3, wherein: the first N + area is in a cross shape and separates the silicon wafer substrate into four spacing blocks which are arranged in a shape like a Chinese character tian in the horizontal direction.
8. The chip of claim 3, wherein: the surface of the P + region has a doping concentration of at least 1021atm/cm3The diffusion depth is 50-70 μm; the surface of the second N + region has a doping concentration of at least 1021atm/cm3The diffusion depth is 30 to 50 μm.
9. The chip of claim 3, wherein: the distance between the P + area and the second N + area and the distance between the first N + area are both 200-300 um.
10. The chip of claim 1, wherein: the depth of the groove is 20-40 um; the thickness of the glass cement is 25-35 mu m.
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| CN201920611005.6U CN210182384U (en) | 2019-04-30 | 2019-04-30 | Novel four diode integrated chips |
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| CN201920611005.6U CN210182384U (en) | 2019-04-30 | 2019-04-30 | Novel four diode integrated chips |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112130A (en) * | 2019-04-30 | 2019-08-09 | 苏州固锝电子股份有限公司 | A kind of manufacturing process of novel four diode integrated chips |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112130A (en) * | 2019-04-30 | 2019-08-09 | 苏州固锝电子股份有限公司 | A kind of manufacturing process of novel four diode integrated chips |
| CN110112130B (en) * | 2019-04-30 | 2024-02-09 | 苏州固锝电子股份有限公司 | Manufacturing process of novel four-diode integrated chip |
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