CN205194683U - Two step rectification chips based on anti - grooving technology - Google Patents
Two step rectification chips based on anti - grooving technology Download PDFInfo
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- CN205194683U CN205194683U CN201521018061.7U CN201521018061U CN205194683U CN 205194683 U CN205194683 U CN 205194683U CN 201521018061 U CN201521018061 U CN 201521018061U CN 205194683 U CN205194683 U CN 205194683U
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Abstract
The utility model belongs to the semiconductor field, concretely relates to two step rectification chips based on anti - grooving technology, including the silicon chip, wherein, this silicon chip includes N type diffuse layer and P type diffuse layer, and N type diffuse layer is located the top of P type diffuse layer, forms the PN junction between N type diffuse layer and the P type diffuse layer, seted up the grooving on the upper surface of silicon chip, the grooving divides silicon substrate upper surface into the boss that is located in the middle of the chip to and be located the marginal both sides step of chip, and wherein the upper surface of step is less than the upper surface of boss, and the PN junction exposes on the lateral wall of grooving, and it has the glass passivation layer all to cover on the bottom of grooving and the lateral wall. The utility model discloses its electric polarity is opposite with conventional rectification chip, backward withstand voltage can be higher than 2000 volts, simultaneously, can guarantee the electrical property of chip can prevent the chip short circuit again, has improved the resistance to pressure and the reliability of chip.
Description
Technical field
The utility model belongs to semiconductor applications, is specifically related to a kind of double step rectification chip based on anti-grooving technique.
Background technology
Mesa diode is the one of diode, because in manufacturing process, only retain the part of PN junction and necessity thereof, erode unnecessary part, its remaining part just presents mesa shape, thus gains the name.
Mesa diode is mainly used in rectification; at present; the production of domestic rectification chip adopts " glass passivation protection " technique more; the product produced has not containing harmful and noxious substance; in production, heavy metal free pollutes; product electric heating property is excellent, low cost of manufacture, is easy to the advantages such as mass production.
Rectification chip is due to the particularity of its structure and technique; there is its structural advantage and defect; it is the below being positioned at p type diffused layer with N-type substrate in current rectification chip; from p type diffused layer chemical corrosion normal direction monocrystalline silicon piece internal notches; groove width about 300 microns, groove depth about 140 microns, inserts glass frit in groove; burn together with melting under the high temperature conditions with groove side face, solid glass produces the effect of passivation and protection to the PN junction of fracture.The polarity of reverse voltage added by this product is that upper P face adds negative voltage, lower N face adds positive voltage, and product is when adding reverse voltage, and product edge presents negative angle shaped shape.The advantage of this Mechanical Builds is, cross-notching depth requirements is not tight, as long as after the degree of depth can exceed the interface of PN junction, product can bear reverse voltage, the current PN junction degree of depth is started at from P face, and how at 100 microns, groove depth is easy to reach; Along with the rising of reverse voltage, equipotential lines will upwarp, and the border extended of withstand voltage depletion region in N-type base is little, and the rate of finished products of product is high.Shortcoming is, the shaped negative angle structures of product causes equipotential lines intensive at edge, and that can bear is oppositely withstand voltage not high, and rectification chip domestic is at present difficult to more than 1600 volts of levels.Also having shortcoming to be negative lower positive unicity on reverse voltage, there is difficulty in the assembling of Shi Hou road client.In addition, the area in the N-type face of product is large, this face is welded on heat abstractor by client, good heat conduction effect, and the area in P face is little, is used for being connected more appropriate with go between, busbar etc., as needed because of electric polarity, by force rectification chip is inverted welding, not only there will be the problem of heat-conducting effect difference, and there will be short circuit between two electrodes, puncture, the accident such as arcing.As everyone knows, the electric polarity of domestic bolt type rectifying tube is defined as base and is positive pole (should connect the P face of chip), goes between as negative (should connect the N face of chip), is just difficult to use the assembling of GPP rectification chip; A large amount of auto rectifier components and parts, the rectification chip requiring supplying electrode different respectively accounts for half, define current GPP rectification chip apply in blind area, market.
In addition, existing glassivation table type rectification chip mainly contains two kinds of structures, and one is single grooving mesa structure, and as shown in Figure 2, this kind of adjacent two chip chambers of structure have a grooved raceway groove 2-1, and sidewall and the bottom of raceway groove are provided with glass passivation layer 2-2; Another kind is two grooving mesa structures, as shown in Figure 3, this kind of adjacent two chip chambers of structure have two grooved raceway groove 3-1, and have the Cutting Road 3-3 that the table top 3-2 in the middle of one and chip is contour between two grooved raceway groove 3-1, sidewall and the bottom of grooved raceway groove 3-1 are provided with glass passivation layer 3-4.
During segmentation chip, first chip for the first structure carries out break-through cutting from grooved trench bottom to glassy layer and following silicon layer, because glass is more much higher than the hardness of silicon and the two all belongs to fragile material, cutting process can produce inevitable transversal crack on the glass of edge, and some crackles can extend to electrical characteristics and the reliability that PN junction surface affects chip.In order to reduce the crackle of chip edge and collapse limit and collapse angle, cutting speed is very slow, and efficiency is very low.Chip for the second structure then carries out break-through cutting from Cutting Road, this kind of mode not glass-cutting, can not cause glass crack, collapse limit and collapse angle, and cutting speed is very high, considerably increases cutting efficiency.But define such structure: the edge of the upper surface of chip is negative pole, the upper surface of middle table top is positive pole.The defect that this structure is brought is: very easily cause positive and negative polarities short circuit in the fabrication process, brings difficulty can to so follow-up assembling.
Utility model content
According to above the deficiencies in the prior art, the utility model provides a kind of double step rectification chip based on anti-grooving technique, its electric polarity is contrary with conventional rectification chip, oppositely withstand voltage can higher than 2000 volts, simultaneously, the electrical property of chip can be ensured, chip short circuit can be prevented again, improve resistance to pressure and the reliability of chip.
A kind of double step rectification chip based on anti-grooving technique described in the utility model, it is characterized in that: comprise silicon chip, wherein, this silicon chip comprises n type diffused layer and p type diffused layer, and n type diffused layer is positioned at the top of p type diffused layer, PN junction is formed between n type diffused layer and p type diffused layer, the upper surface of described silicon chip offers grooving, silicon chip upper surface is divided into the boss be positioned in the middle of chip by grooving, and be positioned at the both sides step of chip edge, wherein the upper surface of step is lower than the upper surface of boss, PN junction is exposed on the sidewall of grooving, the bottom of grooving and sidewall are all coated with glass passivation layer.
Wherein, preferred version is as follows:
The p type diffused layer degree of depth is 130 ~ 140 microns, and the difference in height bottom PN junction and grooving is 10 ~ 30 microns.The domestic current p type diffused layer degree of depth is many at 100 microns, and during as arrived PN junction again more than 20 microns from the anti-grooving of n type diffused layer, remaining monocrystalline silicon piece thickness only stays 80 microns, monocrystalline silicon piece can be caused cracked in a large number, cannot normally produce in later process operation.The unique method of head it off increases the p type diffused layer degree of depth, so that 130 ~ 140 microns can be reached, and ensure that the difference in height bottom PN junction and grooving is 10 ~ 30 microns, after anti-grooving, the left monocrystalline silicon piece thickness of institute is substantially identical with a conventional products left thickness, then can ensure the full wafer rate of later process.
The upper surface of described step is coated with glass passivation layer.
The difference in height of step upper surface and boss upper surface is 10 ~ 30 microns.
The upper surface of boss and the lower surface of silicon chip are equipped with metal conducting layer.
Manufacturing process of the present utility model is: first choose monocrystalline silicon piece, by diffuseing to form p type diffused layer and n type diffused layer on monocrystalline silicon piece; Pass through photoetching at n type diffused layer, corrode the step of height of formation lower than silicon chip upper surface; Grooving and boss is formed in surface on a silicon substrate again by photoetching, corrosion; Deposit glass passivation layer on the silicon chip forming boss, carries out coated to the PN junction be exposed on grooving sidewall; By the glass passivation layer of erosion removal boss upper surface; At upper surface and the silicon chip lower surface depositing metal conductive layer of boss.
The beneficial effect that the utility model has is: (1) its electric polarity is contrary with conventional rectification chip, the face that on chip, direction area is less is N-type, new product negative pole, beneath chips is P type, new product positive pole to the face that area is larger, electric heating property is better than conventional products, oppositely withstand voltage higher than 2000 volts, high-temperature current leakage also significantly reduces; (2) production cost is not higher than conventional products, can continue the online equipment, instrument, the manufacture of materials that use conventional products, can meet the Different electrodes requirement of client to rectification chip product; (3) because step is provided with glass passivation layer lower than boss on the upper surface of step, hidden problem of splitting and collapsing angle can not be caused to glass passivation layer at step place diced chip, namely cutting speed can be improved, chip short circuit can be prevented again, and be conducive to assembling, improve the resistance to pressure of chip, reliability and electrical property.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model;
Fig. 2 is single channel mesa type diode chip structure schematic diagram of the prior art;
Fig. 3 is double channel mesa diode chip structure schematic diagram of the prior art.
In Fig. 1: 1, n type diffused layer 2, p type diffused layer 3, PN junction 4, grooving 5, boss 6, step 7, glass passivation layer 8, metal conducting layer.
In Fig. 2 and Fig. 3, mark has all given explanation in background technology.
Embodiment
Below in conjunction with embodiment, the utility model is described further.
As shown in Figure 1, a kind of double step rectification chip based on anti-grooving technique, comprise silicon chip, wherein, this silicon chip comprises n type diffused layer 1 and p type diffused layer 2, and n type diffused layer 1 is positioned at the top of p type diffused layer 2, PN junction 3 is formed between n type diffused layer 1 and p type diffused layer 2, the upper surface of described silicon chip offers grooving 4, silicon chip upper surface is divided into the boss 5 be positioned in the middle of chip by grooving, and be positioned at the both sides step 6 of chip edge, wherein the upper surface of step 6 is lower than the upper surface of boss 5, PN junction 3 is exposed on the sidewall of grooving 4, the bottom of grooving 4 and sidewall are all coated with glass passivation layer 7.
P type diffused layer 2 degree of depth is 130 microns, and PN junction 3 is 20 microns with the difference in height bottom grooving 4.Domestic current p type diffused layer 2 degree of depth is many at 100 microns, and during as arrived PN junction again more than 20 microns from the anti-grooving of n type diffused layer 1, remaining monocrystalline silicon piece thickness only stays 80 microns, monocrystalline silicon piece can be caused cracked in a large number, cannot normally produce in later process operation.The unique method of head it off increases p type diffused layer 2 degree of depth, so that 130 microns can be reached, and ensure that PN junction 3 is 20 microns with the difference in height bottom grooving 4, after anti-grooving, the left monocrystalline silicon piece thickness of institute is substantially identical with a conventional products left thickness, then can ensure the full wafer rate of later process.
The upper surface of described step 6 is coated with glass passivation layer 7.
The difference in height of step 6 upper surface and boss 5 upper surface is 20 microns.
The upper surface of boss 5 and the lower surface of silicon chip are equipped with metal conducting layer 8.
Manufacturing process of the present utility model is: first choose monocrystalline silicon piece, by diffuseing to form p type diffused layer 2 and n type diffused layer 1 on monocrystalline silicon piece; Pass through photoetching at n type diffused layer 1, corrode the step 6 of height of formation lower than silicon chip upper surface; Grooving 4 and boss 5 is formed in surface on a silicon substrate again by photoetching, corrosion; Deposit glass passivation layer 7 on the silicon chip forming boss 5, carries out coated to the PN junction 3 be exposed on grooving 4 sidewall; By the glass passivation layer 7 of erosion removal boss 5 upper surface; At upper surface and the silicon chip lower surface depositing metal conductive layer 8 of boss 5.
Claims (5)
1. the double step rectification chip based on anti-grooving technique, it is characterized in that: comprise silicon chip, wherein, this silicon chip comprises n type diffused layer and p type diffused layer, and n type diffused layer is positioned at the top of p type diffused layer, PN junction is formed between n type diffused layer and p type diffused layer, the upper surface of described silicon chip offers grooving, silicon chip upper surface is divided into the boss be positioned in the middle of chip by grooving, and be positioned at the both sides step of chip edge, wherein the upper surface of step is lower than the upper surface of boss, PN junction is exposed on the sidewall of grooving, the bottom of grooving and sidewall are all coated with glass passivation layer.
2. a kind of double step rectification chip based on anti-grooving technique according to claim 1, is characterized in that: the p type diffused layer degree of depth is 130 ~ 140 microns, and the difference in height bottom PN junction and grooving is 10 ~ 30 microns.
3. a kind of double step rectification chip based on anti-grooving technique according to claim 1, is characterized in that: the upper surface of described step is coated with glass passivation layer.
4. a kind of double step rectification chip based on anti-grooving technique according to claim 1, is characterized in that: the difference in height of step upper surface and boss upper surface is 10 ~ 30 microns.
5. a kind of double step rectification chip based on anti-grooving technique according to claim 1, is characterized in that: the upper surface of boss and the lower surface of silicon chip are equipped with metal conducting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521018061.7U CN205194683U (en) | 2015-12-05 | 2015-12-05 | Two step rectification chips based on anti - grooving technology |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201521018061.7U CN205194683U (en) | 2015-12-05 | 2015-12-05 | Two step rectification chips based on anti - grooving technology |
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| CN205194683U true CN205194683U (en) | 2016-04-27 |
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| CN201521018061.7U Expired - Fee Related CN205194683U (en) | 2015-12-05 | 2015-12-05 | Two step rectification chips based on anti - grooving technology |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328718A (en) * | 2016-11-04 | 2017-01-11 | 四川洪芯微科技有限公司 | Mesa diode |
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2015
- 2015-12-05 CN CN201521018061.7U patent/CN205194683U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106328718A (en) * | 2016-11-04 | 2017-01-11 | 四川洪芯微科技有限公司 | Mesa diode |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160427 Termination date: 20161205 |
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| CF01 | Termination of patent right due to non-payment of annual fee |