CN102244096A

CN102244096A - 3300V planar non-punch-through insulated gate bipolar transistor chip and manufacturing process thereof

Info

Publication number: CN102244096A
Application number: CN2011102023220A
Authority: CN
Inventors: 刘闯; 饶祖刚
Original assignee: Tianjin Zhonghuan Semiconductor Joint Stock Co Ltd
Current assignee: Tianjin Zhonghuan Semiconductor Joint Stock Co Ltd
Priority date: 2011-07-19
Filing date: 2011-07-19
Publication date: 2011-11-16

Abstract

The invention relates to a 3300V planar non-punch-through insulated gate bipolar transistor chip and a manufacturing process thereof. A neutron radiation doped zone melting monocrystalline polished wafer is adopted and has the dosage concentration between 2E13cm<-3> and 2.3E13cm<-3> and the minority carrier lifetime distributed between 100 microseconds to 1 millisecond; a step-by-step distributed junction termination extension technology is adopted, and the junction depth is between 6 micrometers and 7 micrometers; the concentration distribution is between E14cm<-3> and E17cm<-3>; before diffusion, the sum of a junction termination injection zone and the space is between 34 micrometers and 40 micrometers; and the space increases outwards gradually by 1-2 millimeters from a cellular region. The transistor chip has the advantages that on the premise of ensuring voltage resistance, the chip area is reduced effectively, and the manufacturing process is simplified; and the adoption of the manufacturing process which is compatible with a planar VDMOS (vertical doubled diffused metal oxide semiconductor) is beneficial to the manufacturing of the transistor chip.

Description

3300 volts of plane non-through insulated-gate gated transistors chips and manufacturing process

Technical field

The present invention relates to technical field of semiconductor device, be particularly related to 3300 volts of plane non-through insulated-gate gated transistors (IGBT) chips and the manufacturing process of the distributed step by step knot termination extension of a kind of employing technology, this technology can with vertical bilateral diffusion field-effect tranisistor (VDMOS) process compatible on plane, concerning manufacturing works, have than convenience.

Background technology

Insulated gate transistor (Insulated Gate Bipolar Transistor is called for short IGBT) is a kind of NEW TYPE OF COMPOSITE power device that grows up on bipolar transistor and insulated-gate type field effect transistor (being called for short " MOSFET ") basis.Existing power MOSFET input impedance height, power controlling is little, is easy to drive, and the advantage that control is simple, switching frequency is high has the conducting voltage of bipolar transistor low again, and on state current is big, the remarkable advantage that loss is little.Epoch advocating energy-saving and emission-reduction, low-carbon economy possess the energy-saving efficiency height, are convenient to large-scale production, realize that easily the IGBT of advantages such as energy-conservation wisdomization has become the main flow device of power semiconductor market development.

The IGBT device is divided into plane formula (planar) and plough groove type (Trench) according to the position of grid; Be divided into punch (Puch-Through according to the back surface field characteristic distributions, PT), non-punch (Non-Punch-Through, NPT), (Field-Stop is FS) with soft punch (Soft-Punch-Through, SPT for the field cut-off type, be also referred to as light punch light-punch-through, LPT); Also promising injection enhancement mode (IEGT) and the slot type charge carrier storage type (CSTBT) that improves the reverse characteristic appearance.What the present invention relates to is the manufacturing process of a kind of plane non-through insulated-gate gated transistors (planar NPT IGBT).

The IGBT device since being proposed first by GE company and MOTOROLA company the eighties in last century, its design and produce and monopolizing by western countries always, domestic semicon industry development relatively lags behind.Aspect the igbt chip manufacturing, the domestic production case that does not still have producer to propose 3300V and above high pressure IGBT device.

Summary of the invention

Purpose of the present invention is exactly for overcoming the deficiencies in the prior art, at the problems referred to above, provide the distributed step by step knot termination extension of a kind of employing technology to make the process of insulated gate transistor, method of the present invention fills the domestic gaps, simultaneously again can with the manufacturing process of the 3300V NPT IGBT of plane VDMOS manufacturing process compatibility, and have certain cost advantage.

For achieving the above object, the present invention takes following technical scheme: 3300 volts of plane non-through insulated-gate gated transistors chips is characterized in that the molten monocrystalline polished silicon wafer in district that adopts neutron irradiation to mix; Its doping content is between 2E13cm-3 and 2.3E13cm-3; Its minority carrier life time is distributed between 100 microseconds to 1 millisecond.

Described 3300 volts of plane non-through insulated-gate gated transistors chips adopt distributed step by step knot termination extension processes, and its junction depth is between 6 microns and 7 microns; CONCENTRATION DISTRIBUTION is at E14 cm ^-3And E17cm ^-3Between; Before the diffusion, knot terminal injection region and spacing and between 34 microns and 40 microns; Its spacing is outwards increased 1 micron to 2 microns step by step by cellular region.

3300 volts of plane non-through insulated-gate gated transistors manufacturing process, the technological process of employing and plane vertical bilateral diffusion field-effect pipe compatibility is characterized in that, and the temperature of knot termination environment diffusion is 1150 degree, and the time is 450 minutes; The oxidizing temperature of field oxide is that thickness is between 1.2 microns and 1.4 microns between 1050 degree and 1150 degree; The diffusion temperature of P base is that the time is 100 minutes between 1050 degree and 1150 degree; The temperature that backside collector activates is that the time is 40 minutes between 420 degree and 500 degree.

The present invention has the following advantages owing to take above technical scheme: adopt the district of neutron transmutation doping to melt single crystalline substrate, minority carrier life time is controlled between 100 microseconds to 1 millisecond, guarantee the voltage endurance capability of chip cut-off state and the forward voltage drop of conducting state; Adopt distributed step by step knot termination extension technology, guaranteeing effectively to reduce chip area, simplified manufacturing technique under the withstand voltage prerequisite; The manufacture craft of employing and plane VDMOS compatibility helps making.

Description of drawings

Fig. 1 is the distribution schematic diagram of the knot terminal injection region that relates in the distributed step by step knot termination extension technology;

Fig. 2 is a schematic diagram of making distributed step by step knot terminal on the molten polished silicon wafer in N type district that adopts neutron irradiation to mix;

Fig. 3 is the schematic diagram that covers field oxide on the knot terminal that has formed;

Fig. 4 is the schematic diagram that forms grid oxic horizon and grid polycrystalline figure;

Fig. 5 is the schematic diagram that injects and spread P base and N+ emitter region in cellular region;

Fig. 6 forms the zone isolation schematic diagram of (comprising tetraethyl orthosilicate TEOS and boron-phosphorosilicate glass layer that plasma strengthens);

Fig. 7 is the schematic diagram that forms front metal (comprising gate metal and emitter metal);

Fig. 8 is the schematic diagram that forms front passivation layer (silica that the chemical meteorological deposit that plasma strengthens forms or mix phosphorus oxidation silicon layer and silicon nitride layer);

Fig. 9 is the schematic diagram that forms backside collector and collector electrode contact metal layer.

Embodiment

For a more clear understanding of the present invention, describe the present invention in conjunction with the accompanying drawings and embodiments in detail:

To shown in Figure 9, the substrate slice that the present invention adopts is the molten monocrystalline polished silicon wafer in district as Fig. 1, and its doping way adopts neutron irradiation technology, its dopant dose 2 and 2.3E13cm ^-3Between, to be that resistivity is radial and axial be evenly distributed its main feature, and minority carrier life time is moderate, helps improving emitter injection efficiency, strengthens electricity and leads modulating action, the forward voltage drop when reducing conducting; Knot terminal injection region and spacing that utilization is different from cellular region to the chip edge direction, form the knot termination environment that doping content distributes step by step, effectively reduce the surface area that finishes the termination environment, simultaneously, the identical surface area that takies when withstand voltage of assurance is minimized by optimizing injection region size and its spacing; Its manufacturing process flow is with vertical bilateral diffusion field-effect pipe (VDMOS) the manufacturing process compatibility on plane, and detailed process comprises the steps:

(1), on the molten monocrystalline polished silicon wafer 1 in district, inject knot terminal doped region 2, the spacing of cellular region and knot terminal stops with photoresistance; Its doped chemical is a boron, and doping content is distributed in E14 cm ^-3And E17cm ^-3Between; Diffusion temperature after the injection is that the time is 450 minutes between 1100 degree and 1180 degree; As shown in Figure 2;

(2), after the diffusion of knot termination environment 2, at surface preparation field oxide 3, oxidizing temperature is between 1050 degree and 1150 degree, oxidated layer thickness feeds dichloroethanes in the oxidizing process between 1.2 to 1.4 microns, pass through wet etching then, remove the field oxide 3 of cellular region, as shown in Figure 3;

(3), finish surface clean after, preparation gate oxide 4 and grid polycrystal layer 5; Feed dichloroethanes in the gate oxide oxidizing process; The grid polycrystal layer adopts autodoping technology, mixes back resistivity between 17ohm-cm and 22ohm-cm; By etching, only stay grid and field plate polycrystal layer 5; As shown in Figure 4;

(4), the autoregistration characteristic that is beneficial to grid finishes P type base 6 and injects and diffusion, and be beneficial to photoresistance and stop and do not need to inject N+ emitter region 7; The doping content of the capable base 6 of P is distributed in E14 cm ^-3With E18 cm ^-3Between; P base diffusion temperature is 1150 degree, and the time is 100 minutes; As shown in Figure 5;

(5), the mode of the chemical meteorological deposit that strengthens with plasma prepares zone isolation 8(and comprises tetraethyl orthosilicate TEOS and the boron-phosphorosilicate glass layer that plasma strengthens); Then at zone isolation layer 8 through after refluxing, use the mode of dry method after the first wet method, carve contact hole; The temperature that refluxes is that the time is 30 minutes between 900 degree and 1000 degree; As shown in Figure 6;

(6), prepare front metal layer 9, and anti-carve with dry method or wet method mode with the sputter mode; As shown in Figure 7;

(7), the chemical meteorological deposit that strengthens with plasma forms front passivation layer (comprise silica or mix phosphorus oxidation silicon layer 10 and silicon nitride layer 11); Wherein the thickness of silicon oxide layer 10 is 200 nanometers, and silicon nitride layer thickness is 1 micron; Use dry etch process to expose the routing district; As shown in Figure 8;

(8), overleaf behind the attenuate, inject with ion and to form backside collector 12, prepare collector electrode contacting metal 13 with evaporation again; Then, use the process annealing method, carry out front metal 9 alloys and the back side and inject 12 activation; As shown in Figure 9.

According to the above description, can realize the solution of the present invention in conjunction with art technology.

Claims

1.3300 volt plane non-through insulated-gate gated transistors chip is characterized in that the molten monocrystalline polished silicon wafer in district that adopts neutron irradiation to mix; Its doping content is between 2E13cm-3 and 2.3E13cm-3; Its minority carrier life time is distributed between 100 microseconds to 1 millisecond.

2. 3300 volts of plane non-through insulated-gate gated transistors chips as claimed in claim 1 is characterized in that adopt distributed step by step knot termination extension processes, its junction depth is between 6 microns and 7 microns; CONCENTRATION DISTRIBUTION is at E14 cm ^-3And E17cm ^-3Between; Before the diffusion, knot terminal injection region and spacing and between 34 microns and 40 microns; Its spacing is outwards increased 1 micron to 2 microns step by step by cellular region.

3.3300 volt plane non-through insulated-gate gated transistors manufacturing process, the technological process of employing and plane vertical bilateral diffusion field-effect pipe compatibility is characterized in that, the temperature of knot termination environment diffusion is 1150 degree, and the time is 450 minutes; The oxidizing temperature of field oxide is that thickness is between 1.2 microns and 1.4 microns between 1050 degree and 1150 degree; The diffusion temperature of P base is that the time is 100 minutes between 1050 degree and 1150 degree; The temperature that backside collector activates is that the time is 40 minutes between 420 degree and 500 degree.