CN111584623A - Bipolar junction transistor device, manufacturing method thereof and electronic product - Google Patents
Bipolar junction transistor device, manufacturing method thereof and electronic product Download PDFInfo
- Publication number
- CN111584623A CN111584623A CN202010487354.9A CN202010487354A CN111584623A CN 111584623 A CN111584623 A CN 111584623A CN 202010487354 A CN202010487354 A CN 202010487354A CN 111584623 A CN111584623 A CN 111584623A
- Authority
- CN
- China
- Prior art keywords
- region
- electrode
- regions
- electrode region
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000009792 diffusion process Methods 0.000 claims abstract description 95
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000002184 metal Substances 0.000 claims description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 16
- 230000003247 decreasing effect Effects 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 10
- 238000002474 experimental method Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 239000011295 pitch Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 238000012369 In process control Methods 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010965 in-process control Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
The embodiment of the application provides a bipolar junction transistor device, a manufacturing method thereof and an electronic product. In an embodiment of the present application, the bipolar junction transistor device includes a first electrode region, a second electrode region, and a junction termination extension region formed on a substrate. The junction termination extension region is located between and adjacent to the first electrode region and the second electrode region. The junction termination extension region comprises a plurality of diffusion regions distributed at intervals, and the widths of the diffusion regions are sequentially reduced from the first electrode region to the second electrode region. Experiments prove that compared with a bipolar junction transistor device with a traditional JTE structure, the bipolar junction transistor device provided by the embodiment of the application has the advantages of better HTRB stability, easier control of a manufacturing process flow, lower electric field spike intensity and better voltage stability.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a bipolar junction transistor device, a manufacturing method thereof and an electronic product.
Background
With the improvement of the voltage resistance of the semiconductor device, the JTE (Junction Termination Extension) technology is widely applied to Bipolar Junction Transistor (BJT) devices. However, JTE technology uses a low-concentration extension region, which has limitations on voltage stability, high requirements on doping precision in process control, and poor stability.
Disclosure of Invention
Based on the deficiencies of the existing designs, further improvements to the JTE termination structure of the existing BJT devices are needed. The application provides a bipolar junction transistor device, a manufacturing method thereof and an electronic product.
The bipolar junction transistor device provided by the embodiment of the application comprises:
a substrate (10);
fabricating a first electrode region (20), a second electrode region (30), and a junction termination extension region (40) formed based on the substrate (10), the junction termination extension region (40) being located between the first electrode region (20) and the second electrode region (30) and contiguous with the first electrode region (20), wherein:
the junction termination extension region (40) includes a plurality of diffusion regions that are spaced apart, and the respective widths of the plurality of diffusion regions decrease in sequence from the first electrode region (20) toward the second electrode region (30).
Preferably, the number of the diffusion regions is greater than or equal to 3, and any two adjacent diffusion regions have a distance therebetween, and the distances increase in sequence from the first electrode regions (20) to the second electrode regions (30).
Preferably, the sum of the width of each of the spaces and the width of a diffusion region adjacent to the space and on the side close to the second electrode region (30) is a preset value, and the width of a diffusion region adjacent to the first electrode region (20) is the preset value.
Preferably, the substrate (10) comprises a heavily doped layer and a lightly doped layer located above the heavily doped layer, the first electrode region (20), the second electrode region (30) and the junction termination extension region (40) being formed on the basis of the lightly doped layer, the heavily doped layer being of the same doping type as the lightly doped layer.
Preferably, the bipolar junction transistor device further comprises a second metal field plate (52) and a first metal field plate (51) which are respectively manufactured above the second electrode region (30) and the first electrode region (20), wherein the first metal field plate (51) and the second metal field plate (52) are insulated and isolated through an insulating dielectric layer (60).
Preferably, the bipolar junction transistor device is an NPN-type transistor or a PNP-type transistor.
The method for manufacturing the bipolar junction transistor device provided by the embodiment of the application comprises the following steps:
providing a substrate (10);
forming an electrode region and a junction termination extension region (40) based on the substrate (10), the electrode region comprising a first electrode region (20) and a second electrode region (30), the junction termination extension region (40) comprising a plurality of diffusion regions distributed at intervals, wherein:
the junction termination extension region (40) is located between the first electrode region (20) and the second electrode region (30) and is adjacent to the first electrode region (20), and the respective widths of the plurality of diffusion regions decrease in sequence from the first electrode region (20) toward the second electrode region (30).
Preferably, the number of the diffusion regions is greater than or equal to 3, a distance is formed between any two adjacent diffusion regions, and the distances increase in sequence from the first electrode region to the second electrode region; the sum of the width of each space and the width of a diffusion region adjacent to the space and close to one side of the second electrode regions (30) is a preset value, and the width of a diffusion region adjacent to the first electrode regions (20) is the preset value.
Preferably, forming electrode regions and junction termination extension regions (40) are fabricated based on the substrate (10), including:
forming a first photoresist layer (71) on the substrate (10);
removing partial areas in the photoresist layer (71) through photoetching to form a first window area for manufacturing a first electrode area (20);
doping the substrate (10) at a position corresponding to the first window region to form the first electrode region (20) on the substrate (10);
forming a second photoresist layer (72) over a side of the substrate (10) adjacent the first electrode regions (20);
removing partial regions of the second photoresist layer (72) by photolithography to form a plurality of second window regions for forming junction termination extension regions (40);
doping the substrate (10) at locations corresponding to the plurality of second window regions to form the junction termination extension region (40) comprising a plurality of diffusion regions on the substrate (10);
forming a third photoresist layer (73) over a side of the substrate (10) proximate to the junction termination extension (10);
removing partial area of the third photoresist layer (73) through photoetching to form a third window area for manufacturing a second electrode area (30);
doping the substrate (10) at a position corresponding to the third window region to form the second electrode region (30) on the substrate (10);
wherein the widths of the plurality of second window regions are sequentially decreased from the first electrode regions (20) to the second electrode regions (30).
An electronic product provided by the embodiment of the present application includes the aforementioned bipolar junction transistor device.
In summary, in the bipolar junction transistor, the manufacturing method thereof, and the electronic product provided in the embodiments of the present application, the junction termination extension region is manufactured as a plurality of diffusion regions gradually shrinking from the first electrode region to the second electrode region. Experiments prove that compared with a bipolar junction transistor device with a traditional JTE structure, the HTRB stability is better, the manufacturing process flow is easier to control, the electric field spike intensity is lower, and the voltage stability is better.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic diagram illustrating a partial cross-sectional structure of a bjt according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of an alternative structure for the junction termination extension region of the bipolar junction transistor device shown in fig. 1.
Fig. 3 a-3 c are schematic diagrams of a process for forming the substrate of the bipolar junction transistor device of fig. 1.
Fig. 4 a-4 e are schematic device structures corresponding to the flow of steps for fabricating the bjt device shown in fig. 1.
Fig. 5 is a schematic diagram of a conventional transistor device having a junction termination extension structure.
Fig. 6 is a schematic diagram of experimental variation curves of reverse breakdown voltages of the bipolar junction transistor device of the present application and the transistor device shown in fig. 5 when different impurity doses are implanted into the junction termination extension region.
Fig. 7 is a schematic diagram of experimental peak electric field curves of the bjt device of the present application and the bjt device shown in fig. 5.
Detailed Description
In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are for illustrative and descriptive purposes only and are not used to limit the scope of protection of the present application. Additionally, it should be understood that the schematic drawings are not necessarily drawn to scale. The flowcharts used in this application illustrate operations implemented according to some of the embodiments of the present application. It should be understood that the operations of the flow diagrams may be performed out of order, and steps without logical context may be performed in reverse order or simultaneously. One skilled in the art, under the guidance of this application, may add one or more other operations to, or remove one or more operations from, the flowchart.
Fig. 1 is a schematic cross-sectional view of a part of a bipolar junction transistor according to an embodiment of the present disclosure. In detail, the bipolar junction transistor device 100 provided by the embodiment of the present application may include a substrate 10, an electrode region formed on the substrate 10, and a junction termination extension region 40.
The electrode regions include a first electrode region 20 and a second electrode region 30. The Junction Termination Extension (JTE) region 40 is located between the first electrode region 20 and the second electrode region 30 and is adjacent to the first electrode region 20. The junction termination extension region 40 includes a plurality of diffusion regions spaced apart. The widths of the plurality of diffusion regions are sequentially decreased from the first electrode regions 20 to the second electrode regions 30. Illustratively, as shown in fig. 1, it is assumed that the junction termination extension region 40 includes a first diffusion region 41, a second diffusion region 42, and a third diffusion region 43. In the extending direction of the first electrode regions 20 to the second electrode regions 30, the width a0 of the first diffusion region 41 is greater than the width a1 of the second diffusion region 42, and the width a1 of the second diffusion region 42 is greater than the width a2 of the third diffusion region 43, for example, a0> a1> a 2. For another example, taking fig. 2 as an example, assuming that the junction termination extension region 40 includes five diffusion regions, i.e., a first diffusion region 41, a second diffusion region 42, a third diffusion region 43, a fourth diffusion region 44, and a fifth diffusion region 45, and the widths of the five diffusion regions are a0, a1, a2, A3, and a4, respectively, a0> a1> a2> A3> a 4.
In a preferred embodiment, the number of the diffusion regions is greater than or equal to 3, and any two adjacent diffusion regions have a distance therebetween, and the distances increase in sequence from the first electrode regions 20 to the second electrode regions 30. For example, taking fig. 1 as an example, if the distance between the first diffusion region 41 and the second diffusion region 42 is B1, and the distance between the second diffusion region 42 and the third diffusion region 43 is B2, then B2> B1.
For another example, taking fig. 2 as an example, if the junction termination extension region 40 includes five diffusion regions, i.e., a first diffusion region 41, a second diffusion region 42, a third diffusion region 43, a fourth diffusion region 44, and a fifth diffusion region 45, and the five diffusion regions extend from the first electrode region 20 to the second electrode region 30 with a distance between adjacent diffusion regions being B1, B2, B3, and B4 in this order, B4> B3> B2> B1.
Further, in a preferred alternative embodiment, the sum of the width of each of the above-mentioned pitches and the width of the diffusion region adjacent to the pitch and on the side close to the second electrode regions 30 is a preset value, and the width of the diffusion region adjacent to the first electrode regions 20 is the preset value. For example, taking fig. 1 as an example, for the distance B1, a diffusion region adjacent to the distance B1 and close to the second electrode regions 30 is the second diffusion region 42, and then the sum of the distance B1 and the width a1 of the second diffusion region 42 is the preset value, for example, C. Secondly, for the distance B2, the sum of the distance B2 and the distance a2 of the third diffusion area 43 is the preset value C. Meanwhile, the first diffusion region 41 is a diffusion region adjacent to the first electrode region 20, and then the width a0 of the first diffusion region 41 is also the preset value C. The sum is, a0 ═ B1+ a1 ═ B2+ a2 ═ C. Taking fig. 2 as an example, a0 ═ B1+ a1 ═ B2+ a2 ═ B3+ A3 ═ B4+ a4 ═ C. The preset value C may be preset according to the actual conditions such as the specific type and parameters of the bjt device 100 in this embodiment.
The substrate 10 may include a heavily doped layer and a lightly doped layer located over the heavily doped layer. The first electrode regions 20, the second electrode regions 30 and the junction termination extension regions 40 are formed based on the fabrication of the lightly doped layer, and the heavily doped layer has the same doping type as the lightly doped layer. In the embodiment of the present application, the bipolar junction transistor device 100 may be an NPN transistor or a PNP transistor. Taking the bjt device 100 as an NPN-type triode as an example, the substrate 10 may include an N-type heavily doped layer (N +) and an N-type lightly doped layer (N-). Referring to fig. 3 a-3 c, a specific way of forming the substrate 10 of such a structure may be to perform doping treatment from both sides simultaneously on the N-type wafer shown in fig. 3a, for example, doping phosphorus (p) by means of liquid phosphorus source diffusion or solid phosphorus source diffusion, so as to form N-type heavily doped regions (N + regions) on both sides of the N-type wafer, and then removing the N + region and a portion of the N-region on one side, so as to form the substrate 10 having N + layers and N-layers shown in fig. 3c, so as to fabricate the bipolar junction transistor device 100.
Correspondingly, the first electrode region 20 and the junction termination extension region 40 can be P-type semiconductor layers, and then PN junctions (or main junctions) are formed at the interface with the substrate 10 of the N-type semiconductor
Further, referring to fig. 1, in the embodiment of the present application, the bipolar junction transistor device 100 further includes a first metal field plate 51 and a second metal field plate 52, which are respectively formed above the first electrode region 20 and the second electrode region 30, and the first metal field plate 51 and the second metal field plate 52 are isolated from each other by an insulating dielectric layer 60. In detail, the first metal field plate 51, the second metal field plate 52 and the insulating dielectric layer 60 are formed on the substrate 10 and cover the first electrode region 20, the second electrode region 30 and the junction termination extension region 40. The first metal field plate 51 is in contact with the first electrode region 20 and partially covers the insulating dielectric layer 60, and the second metal field plate 52 is in contact with the second electrode region 30 and partially covers the insulating dielectric layer 60. The material of the insulating dielectric layer 60 may be, but is not limited to, SiO 2.
In addition, it should be noted that, for convenience of explaining the invention of the present application, the drawings and the description of the present application only show some elements of the bipolar junction transistor provided in the present application. For example, the bipolar junction transistor device 100 provided by the embodiment of the present application may include other electrode regions besides the first electrode regions 20 and the second electrode regions 30. For example, taking the bjt device 100 as an NPN-type triode as an example, the first electrode regions 20 may be base regions (B regions), and the second electrode regions 30 may be collector regions (C regions). Accordingly, the bipolar junction transistor device 100 may further include a third electrode region, such as an emitter region (E-region).
Embodiments of the present application also provide a method for manufacturing the bipolar junction transistor device 100, which will be described in detail below with reference to fig. 4a to 4 d.
First, as shown in fig. 4a, a substrate 10 is provided. The substrate 10 includes a heavily doped layer and a lightly doped layer having the same doping type. For example, the substrate 10 may include a heavily N-doped layer (N +) and a lightly N-doped layer (N-) as shown in FIG. 3 above. The substrate 10 can be formed as described above with reference to fig. 3, and is not described herein again.
Next, as shown in fig. 4b, an electrode region including the first electrode region 20 and the second electrode region 30 and a junction termination extension region 40 including a plurality of diffusion regions spaced apart are formed based on the substrate 10. Wherein the junction termination extension region 40 is located between the first electrode regions 20 and the second electrode regions 30 and adjoins the first electrode regions 20. The widths of the plurality of diffusion regions are sequentially decreased from the first electrode regions 20 to the second electrode regions 30.
In a preferred alternative embodiment, the number of the diffusion regions is greater than or equal to 3, and any two adjacent diffusion regions have a distance therebetween, and the distances increase in the direction from the first electrode regions 20 to the second electrode regions 30. For example, taking fig. 4b as an example, the junction termination extension region 40 includes a first diffusion region 41, a second diffusion region 42, and a third diffusion region 43. The spacing between the first diffusion region 41 and the second diffusion region 42 is B1, and the spacing between the second diffusion region 42 and the third diffusion region 43 is B2, then B2> B1.
Further, the sum of the width of each of the above-mentioned pitches and the width of the diffusion region adjacent to the pitch and on the side close to the second electrode regions 30 is a preset value, and the width of the diffusion region adjacent to the first electrode regions 20 is the preset value. For example, in fig. 4B, a0 ═ B1+ a1 ═ B2+ a2 ═ C.
The above-described method of fabricating the junction termination extension region 40, the first electrode region 20, and the second electrode region 30 is briefly described as follows.
Referring to fig. 4c, first, a first photoresist layer 71 may be formed on the substrate 10 (e.g., on the lightly doped layer N-). Then, a partial region of the first photoresist layer 71 is removed by photolithography to form a first window region for fabricating the first electrode region 20. Finally, the substrate 10 is doped at a position corresponding to the first window region to form the first electrode region 20 on the substrate 10. In detail, the doping process may be a process of doping boron (B) ions with a desired concentration onto the substrate 10 corresponding to the window region by means of high temperature diffusion, so as to obtain the first electrode region 20.
Further, as shown in fig. 4d, after the first electrode regions 20 are formed, a second photoresist layer 72 may be formed over the substrate 10 on a side close to the first electrode regions 20 (the originally remaining first photoresist layer 71 may be removed and then formed). Portions of the second photoresist layer 72 are then removed by photolithography to form a plurality of discrete second window regions for making the junction termination extension regions 40. Finally, the substrate 10 is doped at positions corresponding to the plurality of second window regions to form a plurality of diffusion regions included in the junction termination extension region 40 on the substrate 10. In detail, the widths of the plurality of second window regions are sequentially decreased from the first electrode regions 20 to the second electrode regions 30, so that the widths of the plurality of diffusion regions formed by manufacturing are also sequentially decreased from the first electrode regions 20 to the second electrode regions 30. The doping process may be a process of implanting boron (B) ions of a desired concentration into the substrate 10 corresponding to the second window region by means of high-temperature diffusion, so as to obtain the junction termination extension region 40 including a plurality of diffusion regions.
Further, as shown in fig. 4e, after the first electrode regions 20 and the junction termination extension regions 40 are formed, a third photoresist layer 73 (which may be formed after removing the remaining second photoresist layer 72) may be formed over the substrate 10 on the side close to the junction termination extension regions 40. Then, a partial region of the third photoresist layer 73 is removed by photolithography to form a third window region for fabricating the second electrode regions 30. Finally, doping treatment is performed on the substrate 10 at a position corresponding to the third window region to form the second electrode region 30 on the substrate 10. In detail, the doping process may be a process of doping phosphorus (P) ions with a desired concentration onto the substrate 10 corresponding to the third window region by means of high temperature diffusion, so as to obtain the second electrode region 30.
It should be noted that, in other alternative embodiments, the sequence of the fabrication processes of the first electrode regions 20, the second electrode regions 30, and the junction termination extension regions 40 may be interchanged, or may be performed simultaneously under certain conditions, which is not limited to the exemplary embodiment provided in this application.
After the electrode regions and the junction termination extension regions 40 are fabricated, a first metal field plate 51 located above the first electrode region 20 and a second metal field plate 52 located above the second electrode region 30 can be further fabricated above the substrate 10, and the first metal field plate 51 and the second metal field plate 52 are isolated and insulated by an insulating dielectric layer 60. The method for fabricating the first metal field plate 51 and the second metal field plate 52 can be similar to the conventional fabrication method, and is not described in detail here.
The bipolar junction transistor device 100 and the method for manufacturing the bipolar junction transistor device 100 provided in the embodiments of the present application are explained in detail above, and in order to illustrate the differences and advantages of the bipolar junction transistor device 100 provided in the embodiments of the present application and the conventional transistor device, the following is explained by comparing three aspects.
First, High Temperature Reverse Bias (HTRB) stability
TABLE 1
Referring to table 1 above, the transistor having JTE structure shown in fig. 5 and the bipolar junction transistor device 100 provided in the embodiment of the present application were subjected to HTRB examination under the same conditions (for example, applying 800V reverse bias under 150-degree high temperature condition for 168 hours), and 22 transistors were tested, wherein the pass rate of the conventional structure is 95.45%, and the pass rate of the bipolar junction transistor device 100 of the present application is 100%. Thus, the present application provides a bipolar junction transistor device 100 with higher HTRB reliability.
Second, regarding process control
TABLE 2
Referring to table 2 and fig. 6, curve 1 in fig. 6 is a schematic diagram of the fluctuation range of the reverse Breakdown Voltage (BVCBO) when the doping concentration in the JTE structure of the bjt device 100 of the present application is changed between A, A +, a +2, and a +3, and curve 2 is a schematic diagram of the fluctuation range of the BVCBO in the conventional structure. It is clear that the conventional structure has a much larger fluctuation range of BVCBO, and the present application is smaller. That is, during the doping process, if the impurity concentration is not precisely controlled, the BVCBO voltage stability of the bipolar junction transistor device 100 provided by the present application may be better. In other words, the bipolar junction transistor device 100 provided by the present application has a wider tolerance range for process control, and the process flow is easier to control.
Third, regarding electric field stability
Taking the structure of the bipolar junction transistor device 100 shown in fig. 1 as an example, when a reverse bias is applied, the PN junction depletion region should reach the first diffusion region 41 first, and as the electric field increases, the depletion regions of the first diffusion region 41 and the second diffusion region 42 are communicated, and so on, the depletion regions of the first diffusion region 41, the second diffusion region 42, and the third diffusion region 43 are all connected together.
Referring to fig. 7, curve 1 is a schematic diagram of the electric field of the conventional JTE structure transistor device obtained through experiments along with the JTE structure length, and curve 2 is a schematic diagram of the electric field of the bipolar junction transistor device 100 of the present application obtained through experiments along with the JTE structure length. It can be seen that, compared with the conventional JTE terminal structure, the bipolar junction transistor device 100 provided in the embodiment of the present application can reduce the peak value of the electric field, has better stability of the electric field, and can effectively improve the stability of withstand voltage.
In summary, compared with the conventional bjt device with JTE structure, the bjt device 100 provided in the embodiment of the present application has better HTRB stability, easier control of the manufacturing process, lower electric field spike intensity, and better voltage stability.
In addition, an electronic product including the bipolar junction transistor device 100 is also provided in the embodiments of the present application.
The embodiments described above are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the application, but is merely representative of selected embodiments of the application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims. Moreover, all other embodiments that can be made available by a person skilled in the art without making any inventive step based on the embodiments of the present application shall fall within the scope of protection of the present application.
Claims (10)
1. A bipolar junction transistor device, comprising:
a substrate (10);
fabricating a first electrode region (20), a second electrode region (30), and a junction termination extension region (40) formed based on the substrate (10), the junction termination extension region (40) being located between the first electrode region (20) and the second electrode region (30) and contiguous with the first electrode region (20), wherein:
the junction termination extension region (40) includes a plurality of diffusion regions that are spaced apart, and the respective widths of the plurality of diffusion regions decrease in sequence from the first electrode region (20) toward the second electrode region (30).
2. The bipolar junction transistor device of claim 1 wherein the number of diffusion regions is greater than or equal to 3, and any two adjacent diffusion regions have a spacing therebetween, the spacing increasing in a direction from the first electrode region (20) to the second electrode region (30).
3. The bipolar junction transistor device of claim 2, wherein the sum of the width of each pitch and the width of a diffusion region adjacent to the pitch and on a side close to the second electrode region (30) is a preset value, and the width of a diffusion region adjacent to the first electrode region (20) is the preset value.
4. The bipolar junction transistor device according to any of claims 1-3, wherein said substrate (10) comprises a heavily doped layer and a lightly doped layer located above the heavily doped layer, said first electrode region (20), second electrode region (30) and junction termination extension region (40) being formed on the basis of the fabrication of said lightly doped layer, said heavily doped layer being of the same doping type as said lightly doped layer.
5. The bipolar junction transistor device of any of claims 1-3, further comprising a first metal field plate (51) and a second metal field plate (52) respectively formed over said first electrode region (20) and said second electrode region (30), said first metal field plate (51) and said second metal field plate (52) being insulated and isolated from each other by an insulating dielectric layer (60).
6. A bipolar junction transistor device according to any of claims 1-3 wherein said bipolar junction transistor device is an NPN transistor or a PNP transistor.
7. A method of fabricating a bipolar junction transistor device, comprising:
providing a substrate (10);
forming an electrode region and a junction termination extension region (40) based on the substrate (10), the electrode region comprising a first electrode region (20) and a second electrode region (30), the junction termination extension region (40) comprising a plurality of diffusion regions distributed at intervals, wherein:
the junction termination extension region (40) is located between the first electrode region (20) and the second electrode region (30) and is adjacent to the first electrode region (20), and the respective widths of the plurality of diffusion regions decrease in sequence from the first electrode region (20) toward the second electrode region (30).
8. The manufacturing method of claim 7, wherein the number of the diffusion regions is greater than or equal to 3, and any two adjacent diffusion regions have a distance therebetween, and the distances increase in sequence from the first electrode region (20) to the second electrode region (30); the sum of the width of each space and the width of a diffusion region adjacent to the space and close to one side of the second electrode regions (30) is a preset value, and the width of a diffusion region adjacent to the first electrode regions (20) is the preset value.
9. Manufacturing method according to claim 7 or 8, wherein the fabrication of electrode-forming regions and junction termination extensions (40) on the basis of the substrate (10) comprises:
forming a first photoresist layer (71) on the substrate (10);
removing partial area of the photoresist layer (71) through photoetching to form a first window area for manufacturing a first electrode area (20);
doping the substrate (10) at a position corresponding to the first window region to form the first electrode region (20) on the substrate (10);
forming a second photoresist layer (72) over a side of the substrate (10) adjacent the first electrode regions (20);
removing partial regions of the second photoresist layer (72) by photolithography to form a plurality of second window regions for forming junction termination extension regions (40);
doping the substrate (10) at locations corresponding to the plurality of second window regions to form the junction termination extension region (40) comprising a plurality of diffusion regions on the substrate (10);
forming a third photoresist layer (73) on the substrate (10);
removing partial area of the third photoresist layer (73) through photoetching to form a third window area for manufacturing a second electrode area (30);
doping the substrate (10) at a position corresponding to the third window region to form the second electrode region (30) on the substrate (10);
wherein the widths of the plurality of second window regions are sequentially decreased from the first electrode regions (20) to the second electrode regions (30).
10. An electronic product comprising the bipolar junction transistor device of any of claims 1-6 or comprising a bipolar junction transistor device formed made according to the method of any of claims 7-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010487354.9A CN111584623A (en) | 2020-06-02 | 2020-06-02 | Bipolar junction transistor device, manufacturing method thereof and electronic product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010487354.9A CN111584623A (en) | 2020-06-02 | 2020-06-02 | Bipolar junction transistor device, manufacturing method thereof and electronic product |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111584623A true CN111584623A (en) | 2020-08-25 |
Family
ID=72111160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010487354.9A Pending CN111584623A (en) | 2020-06-02 | 2020-06-02 | Bipolar junction transistor device, manufacturing method thereof and electronic product |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111584623A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6218254B1 (en) * | 1999-09-22 | 2001-04-17 | Cree Research, Inc. | Method of fabricating a self-aligned bipolar junction transistor in silicon carbide and resulting devices |
| JP2006100593A (en) * | 2004-09-29 | 2006-04-13 | Toshiba Corp | High breakdown-voltage semiconductor device |
| US20100289032A1 (en) * | 2009-05-12 | 2010-11-18 | Qingchun Zhang | Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same |
| CN102244096A (en) * | 2011-07-19 | 2011-11-16 | 天津中环半导体股份有限公司 | 3300V planar non-punch-through insulated gate bipolar transistor chip and manufacturing process thereof |
| US20120098064A1 (en) * | 2010-10-21 | 2012-04-26 | Fuji Electric Co., Ltd. | Semiconductor device |
| CN104282537A (en) * | 2013-07-02 | 2015-01-14 | 通用电气公司 | Semiconductor devices and methods of manufacture |
| WO2015104900A1 (en) * | 2014-01-10 | 2015-07-16 | 三菱電機株式会社 | Semiconductor device |
| EP3012870A1 (en) * | 2014-10-20 | 2016-04-27 | ABB Technology AG | Edge termination for high voltage semiconductor devices |
| CN111146273A (en) * | 2019-12-27 | 2020-05-12 | 西安电子科技大学 | Junction terminal extension terminal structure with adjustable intermediate layer coverage and preparation method thereof |
-
2020
- 2020-06-02 CN CN202010487354.9A patent/CN111584623A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6218254B1 (en) * | 1999-09-22 | 2001-04-17 | Cree Research, Inc. | Method of fabricating a self-aligned bipolar junction transistor in silicon carbide and resulting devices |
| JP2006100593A (en) * | 2004-09-29 | 2006-04-13 | Toshiba Corp | High breakdown-voltage semiconductor device |
| US20100289032A1 (en) * | 2009-05-12 | 2010-11-18 | Qingchun Zhang | Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same |
| EP2430651A1 (en) * | 2009-05-12 | 2012-03-21 | Cree, Inc. | Diffused junction termination structures for silicon carbide devices and methods of fabricating silicon carbide devices incorporating same |
| US20120098064A1 (en) * | 2010-10-21 | 2012-04-26 | Fuji Electric Co., Ltd. | Semiconductor device |
| CN102244096A (en) * | 2011-07-19 | 2011-11-16 | 天津中环半导体股份有限公司 | 3300V planar non-punch-through insulated gate bipolar transistor chip and manufacturing process thereof |
| CN104282537A (en) * | 2013-07-02 | 2015-01-14 | 通用电气公司 | Semiconductor devices and methods of manufacture |
| WO2015104900A1 (en) * | 2014-01-10 | 2015-07-16 | 三菱電機株式会社 | Semiconductor device |
| EP3012870A1 (en) * | 2014-10-20 | 2016-04-27 | ABB Technology AG | Edge termination for high voltage semiconductor devices |
| CN111146273A (en) * | 2019-12-27 | 2020-05-12 | 西安电子科技大学 | Junction terminal extension terminal structure with adjustable intermediate layer coverage and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7179893B2 (en) | High voltage MOSFET device and method of manufacturing same | |
| US6566690B2 (en) | Single feature size MOS technology power device | |
| JP2968222B2 (en) | Semiconductor device and method for preparing silicon wafer | |
| TWI467766B (en) | Metal oxide semiconductor field transistor and method of fabricating the same | |
| US20060102908A1 (en) | Semiconductor device | |
| US8212292B2 (en) | High gain tunable bipolar transistor | |
| KR101480601B1 (en) | Integrated circuit devices with well regions and methods for forming the same | |
| US9679999B2 (en) | Bidirectional bipolar transistors with two-surface cellular geometries | |
| US10692999B2 (en) | High voltage MOSFET devices and methods of making the devices | |
| US6548864B2 (en) | High density MOS technology power device | |
| US5940700A (en) | Method for fabricating a semiconductor diode with BCD technology | |
| KR100779005B1 (en) | Semiconductor device and manufacturing method thereof | |
| USRE44140E1 (en) | Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns | |
| CN1938862A (en) | Semiconductor device | |
| US7838927B2 (en) | Process for manufacturing a multi-drain electronic power device integrated in semiconductor substrate and corresponding device | |
| KR20010006152A (en) | Method of manufacturing a semiconductor device | |
| CN107316900B (en) | Double-carrier junction transistor layout structure | |
| CN111584623A (en) | Bipolar junction transistor device, manufacturing method thereof and electronic product | |
| KR100392699B1 (en) | Semiconductor device and manufacturing method thereof | |
| US20230155021A1 (en) | Silicon carbide semiconductor device | |
| EP0673072B1 (en) | Semiconductor device comprising a lateral bipolar transistor | |
| TWI597838B (en) | Semiconductor device and method for fabricating the same | |
| CN111430305A (en) | Method for manufacturing electrostatic discharge protection device and electrostatic discharge protection device | |
| KR100300674B1 (en) | Slope Concentration Epitaxial Board of Semiconductor Device with Resurf Diffusion | |
| TW202431641A (en) | Semiconductor device with innovative edge termination |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200825 |