TWI597838B - Semiconductor device and method for fabricating the same - Google Patents

Description

Semiconductor component and method of manufacturing same

The present invention relates to integrated circuit components, and more particularly to a semiconductor component and a method of fabricating the same.

Power devices need to have high-switching and can withstand high voltages such as hundreds of volts.

At present, HV metal-oxide-semiconductor (HVMOS transistor), insulated gate bipolar transistor (IGBT), Junction Field Effect Transistor (Junction Field Effect Transistor) have been developed. , JFET), and Schottky diode and other power components.

Such power components that have been developed with high-speed switching characteristics are generally used in various applications such as power amplification and power control in power systems of instruments such as home appliances, communication devices, and vehicle generators.

According to an embodiment, the present invention provides a semiconductor device comprising: a semiconductor substrate having a first conductivity type; a semiconductor layer disposed on the semiconductor substrate having the first conductivity type; and a first well region disposed on a portion of the semiconductor layer having a second guide opposite to the first conductivity type a second well region disposed in another portion of the semiconductor layer having the second conductivity type; a pair of third well regions disposed on the opposite side of the semiconductor layer adjacent to the second well region a portion having the first conductivity type, wherein one of the third well regions is separated from the first well region by the semiconductor layer; a plurality of isolation elements are disposed on the semiconductor layer, respectively a third well region and the first well region and the second well region; a deep well region disposed in a portion of the semiconductor substrate and adjacent to the first well region and the second well region a semiconductor layer having the second conductive property; a first doped region disposed in the first well region and having the second conductivity type; and a second doped region disposed in the third well region In one of them, the first conductivity type is present.

According to another embodiment, the semiconductor device of the present invention may further include a third doped region disposed in the second well region.

According to an embodiment, the present invention provides a method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming a plurality of first doped regions in the first semiconductor substrate, having opposite a second conductivity type of the first conductivity type; forming a semiconductor layer on the semiconductor substrate having the first conductivity type; forming a first well region and a second well region in a portion of the semiconductor layer Having the second conductivity type; forming a pair of third well regions in a portion of the semiconductor layer adjacent to an opposite side of the second well region, having the first conductivity type, wherein one of the third well regions The first well region is separated by the semiconductor layer; a thermal tempering process is performed, and the doped regions are diffused and joined into a deep well region having the second conductive property, wherein the deep well region is adjacent to the first a semiconductor layer between the well region and the second well region; forming a plurality of isolation elements on the semiconductor layer, respectively located in the third well regions Between the first well region and the second well region; forming a first doped region in the first well region, having the second conductivity type; and forming a second doped region in the third In the well region, the first conductivity type is present.

According to another embodiment, the method of fabricating the semiconductor device of the present invention further comprises forming a third doped region in the second well region when the first doped region is formed in the first well region.

100‧‧‧Semiconductor substrate

102‧‧‧Doped area

102’‧‧‧Shenjing District

104‧‧‧Semiconductor layer

106a‧‧‧First Well Area

106b‧‧‧Second well area

108‧‧‧ Third Well Area

110‧‧‧ Thermal diffusion process

112‧‧‧Isolation components

114‧‧‧First doped area

116‧‧‧Second doped area

118‧‧‧ Third doped area

120‧‧‧ Third doped area

126‧‧‧ dielectric layer

128‧‧‧First conductive contact

130‧‧‧Second conductive contact

132‧‧‧ Third conductive contact

134‧‧‧ Third conductive contact

150‧‧‧First conductive contact

160‧‧‧Second conductive contact

160a‧‧‧The first part of the second conductive contact

160b‧‧‧Second part of the second conductive contact

160c‧‧‧ Third part of the second conductive contact

The full disclosure is based on the following detailed description and in conjunction with the drawings. It should be noted that the illustrations are not necessarily drawn to scale in accordance with the general operation of the industry. In fact, it is possible to arbitrarily enlarge or reduce the size of the component for a clear explanation.

1-8 are a series of cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention; and FIGS. 9-10 are a series of cross-sectional views showing a semiconductor in accordance with another embodiment of the present invention; The manufacturing method of the component.

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of the particular manner in which the invention is used, which is not To limit the invention.

Please refer to FIGS. 1-8 for a series of cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, first, a semiconductor substrate 100 such as a germanium substrate is provided. In one embodiment, the semiconductor substrate 100 has a first conductivity type such as a p-type conductivity type and a resistivity of between 30 ohm-cm and 60 ohm-cm.

Referring to FIG. 2, a plurality of divided doping regions 102 are formed in the semiconductor substrate 100 by the application of a patterned mask layer (not shown) and the application of an ion implantation process (not shown). Here, the doping regions 102 are formed separately in one portion of the semiconductor substrate 100 and have a second conductivity type such as an N-type conductivity type and between 1.0E12 atoms/cm 2 (atoms/cm ² ) to 5.0E13, respectively. Ion dopant concentration of atoms/cm ² (atoms/cm ² ). The ion implantation process for forming the doping region 102 may be one ion implantation perpendicular to the surface of the semiconductor substrate 100.

Referring to FIG. 3, a semiconductor layer 104 is formed on the semiconductor substrate 100 as shown in FIG. The semiconductor layer 104 can be formed by an epitaxy method and includes a semiconductor material such as germanium. The semiconductor layer 104 has a first conductivity type such as a P-type conductivity characteristic and a resistivity of between 30 ohm-cm and 60 ohm-em. In one embodiment, the semiconductor layer 104 has a thickness of between 0.5 and 10 um (micrometers).

Referring to FIG. 4, a first well region 106a and a first partition are formed in one of the semiconductor layers 104 by the application of a patterned mask layer (not shown) and the application of an ion implantation process (not shown). Erjing District 106b. The first well region 106a and the second well region 106b have a second conductivity type such as an N-type (N-type) and a range of 1.0 E12 atoms/cm 2 (atoms/cm ² ) to 1.0 E13 atoms/cm 2 (atoms/ Ion dopant concentration of cm ² ). The ion implantation process for forming the first well region 106a and the second well region 106b may perform one-ion ion implantation perpendicular to the surface of the semiconductor layer 104.

As shown in FIG. 4, the first well region 106a is generally located on the leftmost doped region 102, and the second well region 106b is generally located on the rightmost doped region 102.

Referring to FIG. 5, by applying the patterned mask layer (not shown) and the ion implantation process (not shown), a spacer is formed in one of the semiconductor layers 104 adjacent to the opposite side of the second well region 106b. One of the third well zones 108. The third well regions 108 have a first conductivity type such as P-type and between 1.0E12 atoms/cm 2 (atoms/cm ² ) to 1.0E13 atoms/cm 2 (atoms/cm ² ). Ion dopant concentration. Here, the third well region 108 located on the left side of the second well region 106b is separated from the first well region 106a by the semiconductor layer 104. The ion implantation process that forms the third well region 108 can be one ion implantation perpendicular to the surface of the semiconductor layer 104.

Referring to FIG. 6, next, a thermal diffusion process 110, such as a tempering process, is performed on the structure as shown in FIG. 5 to diffuse dopants in the doped regions 102 of the phase separation in the semiconductor layer 104, respectively. Become a connected deep well area 102'. Here, the dopants in the first well region 106a, the second well region 106b, and the third well region 108 are also diffused in the thermal diffusion process 110. Figure 6 shows the implementation of the deep well region 102' and the first well region 106a, the second well region 106b, and the third well region 108 after the thermal diffusion process 110 is performed. The deep well region 102' is disposed in the semiconductor substrate 100 below the first well region 106a to the second well region 106b, and is located Below the third well region 108 and one of the semiconductor layers 104 between the first well region 106a and the second well region 106b. In one embodiment, the deep well region 102' has a second conductivity characteristic such as an N-type.

With continued reference to FIG. 6, a plurality of isolation elements 112 are then formed over the semiconductor layer 104. As shown in FIG. 6, the spacer elements 112 are respectively located between one of the third well regions 108 and the first well region 106a and between one of the third well regions 108 and the second well region 106b. Here, the isolation element 112 is depicted as a field oxide (FOX). In other embodiments, the isolation element 112 may also be a shallow trench isolation (STI). The spacer member 112 may include an insulating material such as cerium oxide, and the fabrication may be formed by referring to a conventional field oxide or shallow trench spacer fabrication method.

Referring to FIG. 7, the application of a patterned mask layer (not shown) and the ion implantation process (not shown) are performed to form a first doped region 114 in the first well region 106a, and A second doped region 116 is formed in the second well region 106b. The first doping region 114 and the second doping region 116 have a second conductivity type such as n-type (n-type) and about 5.0E14 atoms/cm 2 (atoms/cm ² ) to 7.0E15 atoms/cm 2 cm. Ion dopant concentration of (atoms/cm ² ). The ion implantation process of forming the first doping region 114 and the second doping region 116 may perform one-ion ion implantation perpendicular to the surface of the semiconductor layer 104.

Please continue to refer to FIG. 7, followed by application of another patterned mask layer (not shown) and another ion implantation process (not shown) to form a third doped region 118 and 120, respectively. In the third well zone 108. The third doped regions 118 and 120 have a first conductivity type such as p-type and about 5.0E14 atoms/cm 2 (atoms/cm ² ) to 7.0E15 atoms/cm 2 (atoms/ Ion dopant concentration of cm ² ). The ion implantation process for forming the third doping regions 118 and 120 may be one ion implantation perpendicular to the surface of the semiconductor layer 104.

Referring to FIG. 8, a dielectric layer 126 is then formed over the semiconductor layer 104 to cover the first well region 106a, the second well region 106b, the third well region 108, and the isolation element 112. In one embodiment, dielectric layer 126 comprises a dielectric material such as hafnium oxide and has a thickness of between about 0.5 um and 2.5 um (microns).

Next, a plurality of openings are formed in the dielectric layer 126, and the openings expose one of the first doping region 114, the second doping region 116, and the third doping regions 118 and 120, respectively. Next, a conductive material (not shown) is blanket deposited onto the dielectric layer 126 and filled into the openings. A patterning process (not shown) is then performed to remove portions of the conductive material and form a first conductive contact 128, a second conductive contact 130, and a plurality of third conductive contacts 132 and 134. The first conductive contact 128 is on the semiconductor layer 104 and physically contacts the first doped region 114. The second conductive contact 130 is on the semiconductor layer 104 and physically contacts the second doped region 116. The third conductive contacts 132 and 134 are respectively located on different portions of the semiconductor layer 104 and physically contact one of the third doping regions 118 and 120.

As shown in Figures 1-8, a related fabrication of a semiconductor device in accordance with an embodiment of the present invention is shown, and Figure 8 illustrates a semiconductor device in accordance with an embodiment of the present invention. The semiconductor device as shown in Fig. 8 is suitable for applications having a high-switching power device capable of withstanding high voltages of hundreds of volts or more, such as 200 volts or more.

In one embodiment, the third doped regions 118 and 120 are used as gates, and the third conductive contacts are connected to the third doped regions 118 and 120. 132 and 134 are used as gate electrodes. In addition, the first doping region 114 serves as a drain, and the first conductive contact 128 connected to the first doping region 114 serves as a drain electrode. Furthermore, the second doped region 116 serves as a source, and the second conductive contact 130 connected to the second doped region 116 serves as a source electrode. Therefore, in operation, the components in the semiconductor device shown in FIG. 8 constitute a lateral junction field effect transistor (Lateral JFET), and can be formed by the above-mentioned gate, source and 汲The poles and other related components perform the related operations of the lateral junction field effect transistor.

In an embodiment, in the operation of the semiconductor device as shown in FIG. 8, the obtained semiconductor device can have a high blocking voltage by the use of the deep well region 102' and the use of other related doping regions (high blocking Voltage) and low pinch-off voltage. Furthermore, the semiconductor element as shown in Fig. 8 has manufacturing-related advantages of being simple to manufacture and requiring no additional process.

9-10 are a series of schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. The method of manufacturing the semiconductor device shown in Figs. 9-10 is a modification of the method of manufacturing the semiconductor device shown in Figs. Here, the same reference numerals are given to the same members in the manufacturing method of the semiconductor element shown in Figs. 9 to 10, and only the related manufacturing processes different from the manufacturing method of the semiconductor element shown in Figs. 1 to 8 are disclosed hereinafter.

Referring to Fig. 9, first, the process shown in the above Figs. 1-6 is performed, and the structure as shown in Fig. 6 has been obtained. Next, by applying a patterned mask layer (not shown) and performing an ion implantation process (not shown), a first doped region 114 is formed in the first well region 106a, but not as in the seventh The second doped region 116 is formed in the second well region 106b as shown. Therefore, no doped regions are formed in the second well region 106b. In one embodiment, the first doped region 114 has a second conductivity type such as an n-type (n-type) and approximately between 5.0E14 atoms/cm 2 (atoms/cm ² ) to 7.0E15 atoms/cm 2 ( Ion dopant concentration of atoms/cm ² ). The ion implantation process for forming the first doping region 114 may be one ion implantation perpendicular to the surface of the semiconductor layer 104.

Continuing to refer to FIG. 9, the application of another patterned mask layer (not shown) and the application of another ion implantation process (not shown) are performed to form a third doped region 118 and 120, respectively. In the third well zone 108. The third doped regions 118 and 120 have a first conductivity type such as p-type and about 5.0E14 atoms/cm 2 (atoms/cm ² ) to 7.0E15 atoms/cm 2 (atoms/ Ion dopant concentration of cm ² ). The ion implantation process for forming the third doping regions 118 and 120 may be one ion implantation perpendicular to the surface of the semiconductor layer 104.

Referring to FIG. 10, a dielectric layer 126 is then formed over the semiconductor layer 104 to cover the first well region 106a, the second well region 106b, the third well region 108, and the isolation element 112. In one embodiment, dielectric layer 126 comprises a dielectric material such as hafnium oxide and has a thickness of between about 0.5 um and 2.5 um (microns).

Next, a plurality of openings are formed in the dielectric layer 126, and the openings expose one of the first doping region 114, the second well region 106b, and the third doping regions 118 and 120, respectively. Next, a conductive material (not shown) is blanket deposited onto the dielectric layer 126 and filled into the openings. A patterning process (not shown) is then performed to remove portions of the conductive material and form a first conductive contact 150 and a second conductive contact 160. The first conductive contact 150 is on the semiconductor layer 104 and physically contacts the first doped region 114. The second conductive contact 160 simultaneously contacts the third doping The doped regions 118 and 120 and the second well region 106b include a first portion 160a on the semiconductor layer 104 and physically contacting the second well region 106b and are respectively located on different portions of the semiconductor layer 104 and physically contact the third doping The second portion 160b and the third portion 160c of one of the zones 118 and 120.

As shown in Figures 9-10, a related fabrication of a semiconductor device in accordance with another embodiment of the present invention is shown, and a fifth embodiment shows a semiconductor device in accordance with another embodiment of the present invention. The semiconductor device as shown in Fig. 10 is suitable for use in a power device having high-switching and capable of withstanding characteristics such as a high voltage of several hundred volts or more.

In one embodiment, the third doped regions 118 and 120 and the second well region 106b serve as an anode side while physically contacting the third doped regions 118 and 120 and the second well region 106b. The second conductive contact 150 is used as an anode electrode. In addition, the first doping region 114 serves as a cathode side, and the first conductive contact 128 connected to the first doping region 114 serves as a cathode electrode. Therefore, in operation, the members in the semiconductor element shown in FIG. 10 constitute a Schottky diode, and the Schottky diode can be performed by the above-mentioned anode and cathode and the like. Related operations.

In an embodiment, in the operation of the semiconductor device as shown in FIG. 10, the obtained semiconductor device can have a high blocking voltage by the use of the deep well region 102' and the use of other related doping regions (high blocking Voltage) and low reverse current. Furthermore, the semiconductor element as shown in Fig. 10 has the manufacturing advantages of being simple to manufacture and requiring no additional process.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

100‧‧‧Semiconductor substrate

102’‧‧‧Shenjing District

104‧‧‧Semiconductor layer

106a‧‧‧First Well Area

106b‧‧‧Second well area

108‧‧‧ Third Well Area

112‧‧‧Isolation components

114‧‧‧First doped area

116‧‧‧Second doped area

118‧‧‧ Third doped area

120‧‧‧ Third doped area

126‧‧‧ dielectric layer

128‧‧‧First conductive contact

130‧‧‧Second conductive contact

132‧‧‧ Third conductive contact

134‧‧‧ Third conductive contact

Claims (20)

A semiconductor device comprising: a semiconductor substrate having a first conductivity type; a semiconductor layer disposed on the semiconductor substrate and having the first conductivity type; a first well region disposed in a portion of the semiconductor layer; Conversely, the second conductivity type is one of the first conductivity types; a second well region is disposed in the other portion of the semiconductor layer and has the second conductivity type; and a pair of third well regions are respectively disposed adjacent to the first a portion of the semiconductor layer on the opposite side of the second well region having the first conductivity type, wherein one of the third well regions is separated from the first well region by the semiconductor layer; a plurality of isolation elements Provided on the semiconductor layer between the third well region and the first well region and the second well region; a deep well region disposed in one of the semiconductor substrates and adjacent to the first well The semiconductor layer between the region and the second well region has the second conductive property; a first doped region disposed in the first well region, having the second conductivity type; and a second doping District, respectively These one of the third well region having the first conductivity type. The semiconductor device of claim 1, further comprising: a first conductive contact on the semiconductor layer and physically contacting the first doped region; A second conductive contact is located on the semiconductor layer and physically contacts the second doped region and the second well region in the third well regions. The semiconductor device of claim 1, wherein the first conductive contact is a cathode electrode and the second conductive contact is an anode electrode. The semiconductor component of claim 1, wherein the deep well region has a dopant concentration higher than the first well region and the second well region. The semiconductor device of claim 1, wherein the first doped region has a dopant concentration higher than the first well region. The semiconductor component of claim 1, wherein the second doped region has a dopant concentration higher than the third well region. The semiconductor component of claim 1, further comprising a third doped region disposed in the second well region. The semiconductor device of claim 7, further comprising: a first conductive contact on the semiconductor layer and physically contacting the first doped region; and a second conductive contact on the semiconductor layer And physically contacting the third doped region; and a third conductive contact on the semiconductor layer and simultaneously physically contacting the second doped region in the third well regions. The semiconductor device of claim 7, wherein the first conductive contact is a drain electrode, the second conductive contact is a source electrode, and the third conductive contact is a gate electrode. The semiconductor component according to claim 7, wherein the third doping region has There is a dopant concentration higher than the second well region. A method of fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first conductivity type; forming a plurality of first doped regions separated in the first semiconductor substrate, having a second opposite to the first conductivity type a conductivity type; forming a semiconductor layer on the semiconductor substrate having the first conductivity type; forming a first well region and a second well region in a portion of the semiconductor layer, having the second conductivity type; forming a pair of third well regions having a first conductivity type in a portion of the semiconductor layer adjacent to an opposite side of the second well region, wherein one of the third well regions is between the first well region and the first well region Dividing the semiconductor layer; performing a thermal tempering process, diffusing and joining the doped regions into a deep well region having the second conductive characteristic, wherein the deep well region is adjacent to the first well region and the second well region a semiconductor layer between the plurality of isolation elements on the semiconductor layer, respectively located between the third well region and the first well region and the second well region; forming a first doped region First well area , Having the second conductivity type; and a second doped region formed in the plurality of third well region having the first conductivity type. The method for manufacturing a semiconductor device according to claim 11, further comprising: forming a first conductive contact on the semiconductor layer and physically contacting the first doped region; Forming a second conductive contact on the semiconductor layer while physically contacting the second doped region and the second well region in the third well regions. The method of manufacturing a semiconductor device according to claim 12, wherein the first conductive contact is a cathode electrode and the second conductive contact is an anode electrode. The method of manufacturing a semiconductor device according to claim 11, wherein the deep well region has a dopant concentration higher than the first well region and the second well region. The method of fabricating a semiconductor device according to claim 11, wherein the first doped region has a dopant concentration higher than the first well region. The method of fabricating a semiconductor device according to claim 11, wherein the second doped region has a dopant concentration higher than the third well region. The method for fabricating a semiconductor device according to claim 11, further comprising forming a third doped region in the second well region when the first doped region is formed in the first well region. The method of fabricating a semiconductor device according to claim 17, wherein the third doped region has a dopant concentration higher than that of the second well region. The method of manufacturing a semiconductor device according to claim 17, further comprising forming a first conductive contact, a second conductive contact and a third conductive contact, wherein the first conductive contact is located in the semiconductor layer Upper and physically contacting the first doped region, the second conductive contact is on the semiconductor layer and simultaneously physically contacting the second doped region in the third well region, and the third conductive contact is located The third doped region is physically and in contact with the semiconductor layer. The method of manufacturing a semiconductor device according to claim 19, wherein the first conductive contact is a drain electrode, the second conductive contact is a source electrode, and the third conductive contact is A gate electrode.