TWI451576B - Semiconductor structure and a method for manufacturing the same - Google Patents

Description

Semiconductor structure and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a diode and a method of fabricating the same.

Diodes in semiconductor structures have a wide range of applications in electronic circuits. The diode can be used to regulate voltage and provide a stable voltage to the circuit. In addition, the diodes can also be used to protect the circuit components of the integrated circuit device from extremely high voltages. However, the general diode still has problems to be improved. For example, the switching speed is low, and the requirements of the integrated circuit device cannot be achieved, and the circuit is easily broken. Therefore, the current trend of circuits is to switch to high-speed switching. However, the general diode requires a large design area, so that the miniaturization of the unit device cannot be made a breakthrough.

The present invention relates to semiconductor structures and methods of making the same. The diode in the semiconductor structure has a high switching speed and a low on-resistance. In addition, the diode can be self-isolated from other components, requiring a small design area and low manufacturing cost.

A semiconductor structure is provided. The semiconductor structure includes a diode. The diode includes a first doped region, a second doped region, and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated by a first doped region. The third doped region has adjacent first portions and second portions, respectively adjacent to and away from the second doped regions. The doping concentration of the first portion is greater than the doping concentration of the second portion.

A method of fabricating a semiconductor structure is provided. A method of fabricating a semiconductor structure includes forming a diode. The method of forming a diode includes the following steps. Forming a second doped region on the first doped region. A third doped region is formed on the first doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated by a first doped region. The third doped region has adjacent first portions and second portions, respectively adjacent to and away from the second doped regions. The doping concentration of the first portion is greater than the doping concentration of the second portion.

A semiconductor structure is provided. The semiconductor structure includes a diode. The diode includes a first doped region, a second doped region, and a third doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated by only the first doped region.

A method of fabricating a semiconductor structure is provided. A method of fabricating a semiconductor structure includes forming a diode. The method of forming a diode includes the following steps. Forming a second doped region on the first doped region. A third doped region is formed on the first doped region. The first doped region and the third doped region have a first conductivity type. The second doped region has a second conductivity type opposite to the first conductivity type. The second doped region and the third doped region are separated by only the first doped region.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment will be described in detail with reference to the accompanying drawings.

1 and 2 are respectively a cross-sectional view and a top view of a semiconductor structure in an embodiment. The dielectric isolation structure 26 of Fig. 1 is not shown in Fig. 2. Referring to Figure 1, the semiconductor structure includes a diode. The diode includes a first doped region 2, a second doped region 4, and a third doped region 6. The first doped region 2 includes a well region 8 and a top layer 10. The top layer 10 is located on the well area 8. The edge 20 of the top layer 10 can be located between the opposite edge 16 of the third doped region 6 and the edge 18. The top layer 10 includes a first sub-layer 12 and a second sub-layer 14. The first layer 12 is located on the second sub-layer 14. The doping concentration of the first layer 12 may be greater than the doping concentration of the second sub-layer 14. The third doped region 6 has adjacent first and second portions 22, 24 adjacent to and away from the second doped region 4, respectively. The doping concentration of the first portion 22 can be greater than the doping concentration of the second portion 24. In an embodiment, the third doping region 6 and the well region 8, the first sub-layer 12 and the second sub-layer 14 of the first doping region 2 have a first conductivity type such as a P conductivity type. The second doping region 4 has a second conductivity type, such as an N conductivity type, opposite to the first conductivity type. The second doped region 4 and the third doped region 6 may be heavily doped. In an embodiment, the diode can be used as a Zener diode.

Referring to FIG. 1 , the semiconductor structure can include a substrate 28 , an epitaxial layer 30 , and a doped isolation structure 32 . Epitaxial layer 30 is formed on substrate 28. The substrate 28 and the epitaxial layer 30 may have a first conductivity type such as a P conductivity type. The doped isolation structure 32 can include the buried layer 34 and the well region 36. Buried layer 34 and well region 36 may have a second conductivity type, such as an N conductivity type. The doped isolation structure 32 provides diode self-isolation so that the diode can be isolated from other components.

Referring to FIG. 1 , in an embodiment, the second doping region 4 and the third doping region 6 are separated only by the top layer 10 of the first doping region 2 . In other words, there is no dielectric isolation between the second doped region 4 and the third doped region 6. Therefore, the area occupied by the diode is small. In an embodiment, compared to the second doped region (eg, the second doped region 704 in FIG. 14) and the third doped region (eg, the third doped region 706 in FIG. 14) a dielectric isolation structure (eg, dielectric isolation structure 744 in FIG. 14) separate diodes, occupied by a diode between the second doped region 4 and the third doped region 6 without a dielectric isolation structure The area is small. For example, for a diode having no dielectric isolation between the second doped region 4 and the third doped region 6, the diode is defined by the spacing of the dielectric isolation structure 26, such as a field oxide. The side length L1 (Fig. 2) of the active region (OD region) can be as small as 12.6 μm. A diode having a dielectric isolation structure (e.g., dielectric isolation structure 744 in Fig. 14) has an active region having a side length of 16.4 μm.

The top layer 10 as shown in Figure 1 allows the diode to have a low on-resistance. In addition, the use of the top layer 10 and omitting the dielectric isolation structure between the second doped region 4 and the third doped region 6 (for example, the dielectric isolation structure 744 in FIG. 14) can improve the switching speed of the diode. . For example, FIG. 3 shows a current-voltage (IV) graph of the diode of the embodiment and the diode of the comparative example, wherein the switching speed of the diode of the embodiment is significantly higher than that of the diode of the comparative example. Switching speed.

The semiconductor structure in the embodiment can be applied to a mix-mode or an analog circuit design, such as a start up circuit or a charge pump circuit.

4 to 8 illustrate a process of fabricating a semiconductor structure in an embodiment. Referring to FIG. 4, a buried layer 134 is formed on the substrate 128. The buried layer 134 can be formed using a doping process with a mask layer. By way of example, the method of forming the buried layer 134 can include forming a patterned mask layer (not shown) on the substrate 128 and then doping the exposed substrate 128 to form the buried layer 134. After the buried layer 134 is formed, the mask layer is removed. In an embodiment, an annealing step may also be performed to drive in the impurities to form the buried layer 134.

Referring to FIG. 5, an epitaxial layer 130 is formed on the substrate 128. Further, for example, well region 136 is formed over substrate 128, epitaxial layer 130, and buried layer 134. Well zone 108 may be formed on buried layer 134 and well zone 136. The well region 136 and the well region 108 can be formed using a doping process with a mask layer, respectively. In some embodiments, an annealing step can be performed to drive impurities into well region 136 and well region 108.

Referring to Figure 6, a second sub-layer 114 is formed on the well region 108. The second layer 114 can be formed using a doping process with a mask layer. For example, the second sub-layer 114 is formed by doping the top portion of the well region 108. In some embodiments, an annealing step can be performed to drive in the impurities to form the second sub-layer 114 as shown in FIG. Referring to FIG. 7, for example, dielectric isolation structure 126 is formed over well region 108, epitaxial layer 130, and well region 136. The first sub-layer 112 is formed on the second sub-layer 114. A second doped region 104 is formed on the first sub-layer 112. A third doped region 106 is formed over the well region 108 and the top layer 110 including the first sub-layer 112 and the second sub-layer 114. The first layer 112, the second doping region 104 and the third doping region 106 can be formed by a doping process with a mask layer, respectively. The method of forming the third doped region 106 includes doping the top portion of the top layer 110 adjacent to each other and the top portion of the well region 108.

Referring to FIG. 8 , an interlayer dielectric layer 138 is formed and a conductive layer 140 and a conductive plug 142 electrically connected to the second doping region 104 and the third doping region 106 are formed. The method of forming the conductive layer 140 may include depositing a conductive material such as a metal on the interlayer dielectric layer 138 and patterning the conductive material. The method of forming the conductive plug 142 may include forming a hole in the interlayer dielectric layer 138 and filling the hole with a conductive material such as metal.

The manufacturing method of the semiconductor structure in the embodiment can be applied to a mix-mode or an analog circuit design such as a start up circuit or a charge pump circuit.

In one embodiment, the method of operating the diode of the semiconductor structure includes electrically connecting the cathode to the second doped region 204 and electrically connecting the anode to the third doped region 206, as shown in FIG.

Figure 10 is a cross-sectional view showing a semiconductor structure in an embodiment. The difference between the semiconductor structure shown in FIG. 10 and the semiconductor structure shown in FIG. 1 is that the dielectric isolation structure 326 is shallow trench isolation.

Figure 11 is a cross-sectional view showing a semiconductor structure in an embodiment. The difference between the semiconductor structure shown in FIG. 11 and the semiconductor structure shown in FIG. 1 is that the dielectric isolation structure 26 shown in FIG. 1 is omitted. In this case, the diode does not form any dielectric isolation structure, thus reducing manufacturing costs. In this example, the active region range of the diode is defined by a doped isolation structure 432 that includes buried layer 434 and well region 436. In addition, the diode is isolated from other components by doping the isolation structure 432 from the buried layer 434.

Figure 12 is a cross-sectional view showing a semiconductor structure in an embodiment. The semiconductor structure shown in Fig. 12 differs from the semiconductor structure shown in Fig. 1 in that the buried layer 34 shown in Fig. 1 is omitted. In addition, a well region 508 that is shallower than the well region 536 is used. In this example, the diode is isolated from other components by the well region 536.

Figure 13 is a cross-sectional view showing a semiconductor structure in an embodiment. The difference between the semiconductor structure shown in FIG. 13 and the semiconductor structure shown in FIG. 1 is that the buried layer 34 and the epitaxial layer 30 shown in FIG. 1 are omitted. In addition, a well zone 608 that is shallower than the well zone 636 is used. In this example, the diode is isolated from other components by the well region 636.

Figure 14 is a cross-sectional view showing a semiconductor structure in an embodiment. The semiconductor structure shown in FIG. 14 differs from the semiconductor structure shown in FIG. 1 in that the second doped region 704 and the third doped region 706 are separated by a dielectric isolation structure 744 such as a field oxide. In other embodiments, the dielectric isolation structure 744 is shallow trench isolation. In one embodiment, the dielectric isolation structure 744 is formed after the top layer 710 including the first sub-layer 712 and the second sub-layer 714. In another embodiment, the dielectric isolation structure 744 is formed after the second sub-layer 714. The first layer 712 is formed after the dielectric isolation structure 744 such that the doped path used to form the first sub-layer 712 passes through the dielectric isolation structure 744. In this case, the opening resistance (Ron) of the diode is thus reduced. In yet another embodiment, the first sub-layer 712 and the second sub-layer 714 are both formed after the dielectric isolation structure 744. In this case, the opening resistance of the diode is thus reduced.

The diode of the semiconductor structure in the embodiment may be disposed in a high side area of a high voltage integrated circuit (HVIC). For example, FIG. 15 is a cross-sectional view showing a semiconductor structure in an embodiment in which a diode is disposed in a high side region HA adjacent to the element region D. There is a well region 860 between the element region D and the high side region HA, which may have a first conductivity type such as a P conductivity type. The elements disposed in the element area D may include a transistor (MOS). The transistor can include a well region 846 such as a high voltage well region, a buried layer 848, a well region 850, a heavily doped region 852, a heavily doped region 854 such as a source, a heavily doped region 856 such as a drain and gate structure 858. The transistor can be an NMOS. In one embodiment, well region 850 and heavily doped region 852 have a first conductivity type, such as a P conductivity type. The well region 846, the buried layer 848, the heavily doped region 854, and the heavily doped region 856 have a second conductivity type such as an N conductivity type. The heavily doped region 856, such as a drain, is required to withstand high voltages such as ultra high voltages greater than 600V.

In an embodiment of the invention, forming the first or second sublayer of the top layer after the dielectric isolation structure reduces the turn-on resistance of the diode. The doping range of the top layer is appropriately adjusted to improve the switching speed of the diode. Omission of the dielectric isolation structure between the second doped region and the third doped region also improves the switching speed of the diode. Further, the required design area of the unit element can be reduced and the manufacturing cost can be reduced. The diode can be self-isolated from other components by doping the isolation structure.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

2. . . First doped region

4, 104, 204, 704. . . Second doped region

6, 106, 206, 706. . . Third doped region

8, 36, 108, 136, 436, 508, 536, 608, 636, 846, 850, 860. . . Well area

10, 110, 710. . . Top

12, 112, 712. . . First layer

14, 114, 714. . . Second layer

16, 18, 20. . . edge

twenty two. . . first part

twenty four. . . first part

26, 126, 326. . . Dielectric isolation structure

28, 128. . . Base

30, 130. . . Epitaxial layer

32,432. . . Doped isolation structure

34, 134, 434, 848. . . Buried layer

138. . . Interlayer dielectric layer

140. . . Conductive layer

142. . . Conductive plug

744. . . Dielectric isolation structure

852, 854, 856. . . Heavily doped region

858. . . Gate structure

D. . . Component area

HA. . . High side area

L1. . . Side length

1 is a cross-sectional view of a semiconductor structure in an embodiment.

2 is a top view of the semiconductor structure in an embodiment.

Fig. 3 is a graph showing the I-V curve of the diode of the example and the diode of the comparative example.

4 to 8 illustrate a process of fabricating a semiconductor structure in an embodiment.

FIG. 9 illustrates a semiconductor structure and an operation method thereof in an embodiment.

Figure 10 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 11 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 12 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 13 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 14 is a cross-sectional view showing a semiconductor structure in an embodiment.

Figure 15 is a cross-sectional view showing a semiconductor structure in an embodiment.

2. . . First doped region

4. . . Second doped region

6. . . Third doped region

8, 36. . . Well area

10. . . Top

12. . . First layer

14. . . Second layer

16, 18, 20. . . edge

twenty two. . . first part

twenty four. . . first part

26. . . Dielectric isolation structure

28. . . Base

30. . . Epitaxial layer

32. . . Doped isolation structure

34. . . Buried layer

Claims (8)

A semiconductor structure comprising a diode, wherein the diode comprises: a first doped region having a first conductivity type; and a second doped region having a second opposite to the first conductivity type a conductive type; and a third doped region having the first conductivity type; wherein the second doped region and the third doped region are separated by the first doped region, the third doped region having a first portion and a second portion adjacent to each other, the first portion and the second portion are respectively adjacent to and away from the second doped region, and the doping concentration of the first portion is greater than the doping concentration of the second portion. The semiconductor structure of claim 1, wherein the second doped region and the third doped region are separated by only the first doped region. The semiconductor structure of claim 1, wherein the first doped region comprises a top layer, and an edge of the top layer is between opposite edges of the third doped region. The semiconductor structure of claim 1, wherein the first doped region comprises a top layer, the top layer comprising a first sub-layer and a second sub-layer, the first sub-layer being located in the second sub-layer The doping concentration of the first sub-layer is greater than the doping concentration of the second sub-layer. A method of fabricating a semiconductor structure, comprising forming a diode, the method of forming the diode includes: forming a second doped region on a first doped region; and forming a first doped region Third doped region, The first doped region and the third doped region have a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type, the second doped region and the The third doped region is separated by the first doped region, the third doped region has a first portion and a second portion adjacent to each other, and the first portion and the second portion are respectively close to and away from the first portion The doping concentration of the first portion is greater than the doping concentration of the second portion. The method of fabricating a semiconductor structure according to claim 5, wherein the first doped region comprises a top layer and a well region, and the top layer is formed by doping a top portion of the well region. The method of fabricating a semiconductor structure according to claim 6, wherein the method of forming the third doped region comprises doping a top portion of the top layer adjacent to each other and a top portion of the well region. The method of fabricating a semiconductor structure according to claim 6, wherein the method of forming the diode includes forming a dielectric isolation structure on the well region, wherein the second doping region and the third doping The regions are separated by the dielectric isolation structure that is formed after the dielectric isolation structure.