TWI443760B - Semiconductor structure and manufacturing method for the same - Google Patents

Description

Semiconductor structure and method of manufacturing same

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a high voltage semiconductor device and a method of fabricating the same.

The semiconductor industry continues to shrink the size of semiconductor structures while improving the unit cost of speed, performance, density, and integrated circuits. For example, a diode such as a Schottky diode in a semiconductor structure can be applied to a non-synchronous device. A typical Schottky diode system has metal contacts, field oxide spacers, and N-type heavily doped portions formed on an N-type substrate. The metal contacts and the N-type heavily doped portions on the substrates on opposite sides of a single field oxide spacer are electrically connected to the anode and cathode, respectively.

The non-synchronous device generally has two power metal oxide semiconductor field effect transistors (power MOSFETs), which are disposed on the high side and the low side, respectively. The Schottky diode can be configured on the low side MOSFET to reduce the switching power loss of the device during buck DC to DC conversion. However, in general, the Schottky diode has a leakage current that seriously affects the performance of the device under reverse bias, which causes a loss of power on the circuit. For example, please refer to Fig. 1. Generally, under the reverse bias voltage, the leakage current of the Schottky diode will gradually increase with the increase of the voltage, and the Schottky diode will not collapse. Therefore, when applied to a high voltage device, the voltage level of the general Schottky diode is shifted.

The present invention relates to semiconductor structures and methods of making the same. The semiconductor structure has elements utilizing the RESURF concept on the drift region between two mutually separated dielectric portions, thereby increasing the operating voltage of the device. The portion of the semiconductor structure that is electrically connected to the anode has a pinch element, thereby reducing leakage current of the device. The semiconductor structure can be applied to a high voltage device. The semiconductor structure can include a high voltage resistant Schottky diode.

A semiconductor structure is provided. The semiconductor structure includes a well region, a dielectric structure, a first doped layer, a second doped layer and a first doped region. The dielectric structure is located on the well area. The dielectric structure has a first dielectric side and a second dielectric side. The dielectric structure includes a first dielectric portion and a second dielectric portion between the first dielectric side and the second dielectric side. The first doped layer is located on the well region between the first dielectric portion and the second dielectric portion. The second doped layer is on the first doped layer. The first doped region is located in the well region on the first dielectric side. The well region, the first doped layer and the first doped region have a first conductivity type. The second doped layer has a second conductivity type opposite to the first conductivity type. A cathode system is electrically connected to the first doped region. An anode is electrically connected to the well region on the second dielectric side.

A semiconductor structure is also provided. The semiconductor structure includes a well region, a dielectric structure, a first doped region, a second doped region, and a third doped region. The dielectric structure is located on the well area. The dielectric structure has a first dielectric side and a second dielectric side. The first doped region is located in the well region on the first dielectric side. The second doped region and the third doped region are located in the well region on the second dielectric side. The well region and the first doped region have a first conductivity type. The second doped region and the third doped region have a second conductivity type opposite to the first conductivity type. A cathode system is electrically connected to the first doped region. An anode is electrically connected to the well region, the second doped region and the third doped region between the second doped region and the third doped region.

A method of fabricating a semiconductor structure is provided. The method includes the following steps. A dielectric structure is formed on a well region. The dielectric structure has a first dielectric side and a second dielectric side. The dielectric structure includes a first dielectric portion and a second dielectric portion between the first dielectric side and the second dielectric side. A first doped layer is formed. The first doped layer is located on the well region between the first dielectric portion and the second dielectric portion. Forming a second doped layer on the first doped layer. A first doped region is formed. The first doped region is located in the well region on the first dielectric side. The well region, the first doped layer and the first doped region have a first conductivity type. The second doped layer has a second conductivity type opposite to the first conductivity type.

A method of fabricating a semiconductor structure is provided. The method includes the following steps. A dielectric structure is formed on a well region. The dielectric structure has a first dielectric side and a second dielectric side. A first doped region is formed. The first doped region is located in the well region on the first dielectric side. A second doped region and a third doped region are formed. The second doped region and the third doped region are located in the well region on the second dielectric side. The second doped region and the third doped region are separated from each other by the well region. The well region and the first doped region have a first conductivity type. The second doped region and the third doped region have a second conductivity type opposite to the first conductivity type.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment will be described in detail with reference to the accompanying drawings.

FIG. 2 illustrates a semiconductor structure and a method of fabricating the same according to an embodiment. Please refer to FIG. 2 to provide a substrate 1. Substrate 1 may comprise a stack of germanium, an overlying insulating layer or other suitable semiconductor material. Substrate 1 can also be a doped well region in the substrate. Alternatively, the substrate 1 may be a film formed by epitaxy or non-elevation, such as vapor deposition. A well region 2 is formed on the substrate 1. A first doped region 12 is formed in the well region 2 on the first dielectric side 8. A second doped region 14 is formed in the well region 2 on the second dielectric side 10. A third doped region 16 is also formed in the well region 2 on the second dielectric side 10.

Referring to FIG. 2, a dielectric structure is formed on the well region 2, including the first dielectric portion 4 and the second dielectric portion 6. The dielectric structure can include an oxide such as hafnium oxide. The first dielectric portion 4 and the second dielectric portion 6 are not limited to the field oxide as shown in FIG. 2, and may include shallow trench isolation. The first dielectric portion 4 and the second dielectric portion 6 respectively have a first dielectric side 8 and a second dielectric side 10 that are apart from each other. A first doped layer 24 is formed on the well region 2 between the first dielectric portion 4 and the second dielectric portion 6. A second doped layer 26 is formed on the first doped layer 24. In an embodiment, the well region 2, the first doped layer 24, the first doped region 12, and the heavily doped portion 18 have a first conductivity type. The second doped region 14, the third doped region 16, the heavily doped portion 20, the heavily doped portion 22, and the first doped layer 26 have a second conductivity type opposite to the first conductivity type. For example, the first conductivity type is N type, and the second conductivity type is P type.

Referring to FIG. 2, a gate structure 28 can be formed on the second doped region 14 and the well region 2 and extended to the second dielectric portion 6. The gate structure 28 can include a gate dielectric layer and a gate electrode layer. A gate electrode layer is formed on the gate dielectric layer. The gate electrode layer may include a metal or a germanium such as a polysilicon or a metal halide.

Referring to FIG. 2, the cathode 30 can be electrically connected to the first doped region 12 via the heavily doped portion 18 and the metal contact 34 that are in ohmic contact therebetween. The anode 32 can be electrically connected to the gate structure 28 via a metal contact 34 that provides an ohmic contact. The anode 32 can also be electrically coupled to the second doped region 14 and the third doped region 16 via a heavily doped portion 20, a heavily doped portion 22, and a metal contact 34 that are in ohmic contact. The anode 32 can also be electrically connected to the well region 2 between the second doped region 14 and the third doped region 16 via the metal contact 34, and a Schottky junction can be formed between the metal contact 34 and the well region 2.

Referring to FIG. 2, in an embodiment, the semiconductor structure may include a diode such as a lateral Schottky diode. The first doped layer 24 and the second doped layer 26 formed on the drift region between the first dielectric portion 4 and the second dielectric portion 6 use the RESURF concept, thereby lifting the Schottky collapse of the device ( Schottky breakdown) and can withstand high operating voltages. In addition, the device has a low Schottky Barrier. The embodiment is not limited to the two-layer RESURF structure having the first doping layer 24 and the second doping layer 26 as shown in FIG. 2, and may be other multilayer RESURF structures. The second doped region 14 and the third doped region 16 may form a pinch element for vacating the well region 2 between the second doped region 14 and the third doped region 16. Therefore the device can have low leakage current.

Figure 3 is a diagram showing the I-V curve of the device under forward bias in an embodiment. Figure 4 shows the I-V curve of the device under reverse bias. Referring to Figure 3, the device has a two-stage on-resistance under forward bias. The turning point of the change in resistance value is about 0.2V (Schottky diode conduction) and 0.55V (PN type diode conduction). Referring to Figure 4, the device has a low leakage current at an operating voltage of about 350V or less. Thus, the semiconductor structure of an embodiment can include a Schottky diode and a PN-type diode.

Figure 5 illustrates a top view of a semiconductor structure in accordance with an embodiment. Referring to FIG. 5, the first doped layer 124 and the second doped layer 126 extend over the entire well region 102 between the first dielectric portion 104 and the second dielectric portion 106. In one embodiment, the first dielectric portion 104 and the second dielectric portion 106 are formed, and then the well region 102 is doped with the first dielectric portion 104 and the second dielectric portion 106 as a mask layer. The first doping layer 124 and the second doping layer 126 are formed. Therefore, the formation of the first doped layer 124 and the second doped layer 126 does not involve a mask with a very precise pattern. The formation method is simple and can reduce the manufacturing cost.

Figure 6 illustrates a top view of a semiconductor structure in accordance with an embodiment. Referring to FIG. 6, the first doped layer 224 and the second doped layer 226 are separated into doped stripes 203 separated from each other by the well region 202.

FIG. 7 is a top view of a semiconductor structure in accordance with an embodiment. Referring to FIG. 7, a dielectric stripe 305 is formed extending between the first dielectric portion 304 and the second dielectric portion 306. The dielectric strips 305 divide the first doped layer 324 and the second doped layer 326 into doped strips 303 that are separated from each other. In one embodiment, the first dielectric portion 304, the second dielectric portion 306, and the dielectric strips 305 are formed, and then the first dielectric portion 304, the second dielectric portion 306, and the dielectric strips 305 are used as a mask. The well region 302 is doped to form a doped stripe 303 comprising a first doped layer 324 and a second doped layer 326. Therefore, the formation of the first doped layer 324 and the second doped layer 326 does not involve a very precise pattern mask. The formation method is simple and can reduce the manufacturing cost.

8 is a cross-sectional view of a semiconductor structure in accordance with an embodiment. Referring to FIG. 8, a dielectric island 407 is formed in the first doped layer 424 and the second doped layer 426. Dielectric island 407 can include an oxide such as hafnium oxide. The dielectric island 407 is not limited to the field oxide as shown in Fig. 8, and may include shallow trench isolation. Figure 9 illustrates a top view of a semiconductor structure in accordance with an embodiment. Referring to Figure 9, the dielectric island 507 extends over the well region 502. Figure 10 illustrates a top view of a semiconductor structure in accordance with an embodiment. Referring to FIG. 10, the dielectric island 607 can be appropriately disposed in the first doping layer 624 and the second doping layer 626 according to desired device characteristics.

11 is a cross-sectional view of a semiconductor structure in accordance with an embodiment. The difference between the semiconductor structure shown in FIG. 11 and the semiconductor structure shown in FIG. 2 is that the buried layer 736 is formed on the well region 702. In an embodiment, the well region 702 and the buried layer 736 have opposite conductivity types, respectively. The use of the buried layer 736 can increase the operating voltage of the device. Figure 12 is a cross-sectional view of a semiconductor structure in accordance with another embodiment. The semiconductor structure shown in FIG. 12 differs from the semiconductor structure shown in FIG. 11 in that deep trench isolation 838 is formed in the substrate 801. The use of deep trench isolation 838 also increases the operating voltage of the device.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1, 801. . . Base

2, 102, 202, 302, 502, 702, 802. . . Well area

4, 104, 304. . . First dielectric part

6, 106, 306. . . Second dielectric part

8. . . First dielectric side

10. . . Second dielectric side

12. . . First doped region

14. . . Second doped region

16. . . Third doped region

18, 20, 22. . . Heavy doped part

24, 124, 224, 324, 424, 624. . . First doped layer

26, 126, 226, 326, 426, 626. . . Second doped layer

28. . . Gate structure

30. . . cathode

32. . . anode

34. . . Metal contact

303, 203. . . Doped stripes

305. . . Dielectric stripe

407, 507, 607. . . Dielectric island

736. . . Buried layer

838. . . Deep trench isolation

Figure 1 is an I-V curve of a semiconductor device under reverse bias.

FIG. 2 illustrates a semiconductor structure and a method of fabricating the same according to an embodiment.

Figure 3 is a diagram showing the I-V curve of the device under forward bias in an embodiment.

Figure 4 shows the I-V curve of the device under reverse bias.

Figure 5 illustrates a top view of a semiconductor structure in accordance with an embodiment.

Figure 6 illustrates a top view of a semiconductor structure in accordance with an embodiment.

FIG. 7 is a top view of a semiconductor structure in accordance with an embodiment.

8 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 9 illustrates a top view of a semiconductor structure in accordance with an embodiment.

Figure 10 illustrates a top view of a semiconductor structure in accordance with an embodiment.

11 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 12 is a cross-sectional view of a semiconductor structure in accordance with another embodiment.

1. . . Base

2. . . Well area

4. . . First dielectric part

6. . . Second dielectric part

8. . . First dielectric side

10. . . Second dielectric side

12. . . First doped region

14. . . Second doped region

16. . . Third doped region

18. . . Heavy doped part

20, 22. . . Heavy doped part

twenty four. . . First doped layer

26. . . Second doped layer

28. . . Gate structure

30. . . cathode

32. . . anode

34. . . Metal contact

Claims (10)

A semiconductor structure comprising: a well region; a dielectric structure located on the well region and having a first dielectric side and a second dielectric side, wherein the dielectric structure comprises a first a dielectric portion and a second dielectric portion between the first dielectric side and the second dielectric side; a first doped layer located between the first dielectric portion and the second dielectric a portion of the well region between the portions; a second doped layer on the first doped layer; and a first doped region in the well region on the first dielectric side, wherein the The well region, the first doped layer and the first doped region have a first conductivity type, and the second doped layer has a second conductivity type opposite to the first conductivity type, and a cathode system Optionally connected to the first doped region, an anode is electrically connected to the well region on the second dielectric side. The semiconductor structure of claim 1, further comprising a dielectric island located in the first doped layer and the second doped layer. The semiconductor structure of claim 1, wherein the first doped layer and the second doped layer are separated into a plurality of mutually separated doped stripes by the well. The semiconductor structure of claim 1, further comprising a dielectric strip extending between the first dielectric portion and the second dielectric portion, and the first doped layer and the second The doped layer is divided into a plurality of doped stripes that are separated from each other. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a Schottky diode and a PN-type diode. A semiconductor structure comprising: a well region; a dielectric structure located on the well region and having a first dielectric side and a second dielectric side; a first doped region located at the In the well region on the first dielectric side; and a second doped region and a third doped region in the well region on the second dielectric side, wherein the well region and the well region The first doped region has a first conductivity type, the second doped region and the third doped region have a second conductivity type opposite to the first conductivity type, and a cathode system is electrically connected to the first In the doped region, an anode is electrically connected to the well region, the second doped region and the third doped region between the second doped region and the third doped region. The semiconductor structure of claim 6, wherein the semiconductor structure comprises a Schottky diode and a PN-type diode. A method of fabricating a semiconductor structure, comprising: forming a dielectric structure on a well region, wherein the dielectric structure has a first dielectric side and a second dielectric side, the dielectric structure including a dielectric structure a first dielectric portion and a second dielectric portion between the first dielectric side and the second dielectric side; forming a first doped layer, wherein the first doped layer is located a well region between the first dielectric portion and the second dielectric portion; forming a second doped layer on the first doped layer; and forming a first doped region, wherein the first doping The doped region is located in the well region on the first dielectric side, the well region, the first doped layer and the first doped region have a first conductivity type, and the second doped layer is There is a second conductivity type opposite to the first conductivity type. The method of fabricating the semiconductor structure of claim 8, further comprising forming a plurality of dielectric stripes, wherein the dielectric stripes extend between the first dielectric portion and the second dielectric portion, The first doped layer is formed on the well region between the dielectric stripes. A method of fabricating a semiconductor structure, comprising: forming a dielectric structure on a well region, wherein the dielectric structure has a first dielectric side and a second dielectric side; forming a first doping a region, wherein the first doped region is located in the well region on the first dielectric side; forming a second doped region and a third doped region, wherein the second doped region and the third region The doped region is located in the well region on the second dielectric side, and the second doped region and the third doped region are separated from each other by the well region, the well region and the first doping region The region has a first conductivity type, and the second doped region and the third doped region have a second conductivity type opposite to the first conductivity type.