WO2015104900A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- WO2015104900A1 WO2015104900A1 PCT/JP2014/080352 JP2014080352W WO2015104900A1 WO 2015104900 A1 WO2015104900 A1 WO 2015104900A1 JP 2014080352 W JP2014080352 W JP 2014080352W WO 2015104900 A1 WO2015104900 A1 WO 2015104900A1
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- semiconductor device
- metal wiring
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- insulating film
- electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 334
- 229910052751 metal Inorganic materials 0.000 claims abstract description 323
- 239000002184 metal Substances 0.000 claims abstract description 323
- 230000005684 electric field Effects 0.000 claims abstract description 142
- 239000000758 substrate Substances 0.000 claims abstract description 120
- 239000012535 impurity Substances 0.000 claims abstract description 113
- 230000007423 decrease Effects 0.000 claims abstract description 25
- 238000007667 floating Methods 0.000 claims description 77
- 239000000463 material Substances 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 49
- 238000009826 distribution Methods 0.000 description 35
- 238000002347 injection Methods 0.000 description 33
- 239000007924 injection Substances 0.000 description 33
- 230000000694 effects Effects 0.000 description 21
- 230000002441 reversible effect Effects 0.000 description 21
- 238000002513 implantation Methods 0.000 description 20
- 230000002829 reductive effect Effects 0.000 description 14
- 150000002500 ions Chemical class 0.000 description 13
- 238000004088 simulation Methods 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 7
- 230000036961 partial effect Effects 0.000 description 7
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000009471 action Effects 0.000 description 4
- 230000004913 activation Effects 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 230000000670 limiting effect Effects 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910020177 SiOF Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012887 quadratic function Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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Definitions
- the present technology relates to a semiconductor device, and more particularly to a semiconductor device suitable as a power electronics semiconductor device having a high breakdown voltage.
- semiconductor devices used in power electronics include diodes, metal-oxide-semiconductor field-effect transistors (Metal-Oxides).
- MOSFET metal-oxide-semiconductor field effect transistor
- IGBT Insulated Gate Bipolar Transistor
- a termination structure is provided so as to surround a region functioning as an active element (hereinafter sometimes referred to as “active region”).
- the function of the termination structure is to maintain a high voltage generated on the substrate surface between the active region and the end of the semiconductor device.
- the high breakdown voltage of the semiconductor device is realized only by providing a termination structure.
- PN junction diode composed of a low concentration N-type semiconductor substrate and a high concentration P-type impurity layer (hereinafter sometimes referred to as “PIN diode”)
- PIN diode a high concentration P-type impurity layer
- most of the depletion layer is in reverse bias. Has spread to the low-concentration N-type semiconductor substrate. A high voltage is held by this depletion layer.
- the breakdown voltage is limited by the electric field concentration at the end of the high concentration P-type impurity layer, specifically, at the outer edge of the high concentration P-type impurity layer.
- the depletion layer extends to both the low-concentration N-type semiconductor substrate and the low-concentration P-type impurity layer. In this way, the electric field at the end of the high concentration P-type impurity layer is relaxed, and the breakdown voltage of the semiconductor device is increased.
- the low-concentration P-type impurity layer is referred to as a RESURF (Reduced Surface Field: RESURF) layer or a JTE (Junction Termination Extension) layer.
- RESURF Reduced Surface Field
- JTE Joint Termination Extension
- a depletion layer also spreads in the RESURF layer.
- the RESURF layer is almost completely depleted to the outermost surface at a desired voltage.
- the condition is defined by the injection amount of the RESURF layer (more precisely, the surface density of acceptor ions (space charge) contained in the RESURF layer).
- the optimal injection amount of the RESURF layer does not depend on the impurity concentration of the semiconductor substrate and is determined by the semiconductor material constituting the semiconductor substrate.
- the optimum implantation amount of the RESURF layer is about 1 ⁇ 10 12 cm ⁇ 2 .
- the optimum injection amount of the RESURF layer is about 1 ⁇ 10 13 cm ⁇ 2 .
- the optimum implantation amount values of these RESURF layers are values when the activation rate of the implanted impurities is 100%. These optimum values for the injection amount of the RESURF layer are called RESURF conditions.
- the RESURF structure is characterized by the fact that the depletion layer extends to both P-type and N-type, so that the termination is about half of the field limiting ring (Field Limiting Ring: FLR) structure, which is a general termination structure.
- FLR Field Limiting Ring
- An equivalent breakdown voltage can be obtained with the width of the structure.
- the RESURF structure has the following problems.
- the electric field is concentrated on the outer edge portion of the RESURF layer in order to obtain a high pressure resistance.
- the breakdown voltage is limited by avalanche breakdown at the outer edge of the RESURF layer, or thermal breakdown and flashover due to a short-circuit current of the avalanche breakdown may occur.
- This problem can be avoided, for example, by gradually reducing the amount of injection of the RESURF layer toward the outside of the semiconductor substrate (in the direction of the end of the semiconductor device) (see, for example, Non-Patent Document 1 and Patent Document 1). .
- a termination structure in which the injection amount of the RESURF layer is gradually reduced, the electric field concentration points are dispersed in countless places, and the maximum electric field inside the semiconductor is greatly reduced.
- Such a RESURF layer (low-concentration P-type impurity layer) is called a graded doping layer or a VLD (Variation of Lateral Doping) layer, and such a termination structure is called a VLD structure.
- the implantation amount of a low-concentration P-type impurity layer in other words, a VLD structure.
- a structure in which the amount of space charge is gradually reduced toward the outside of the semiconductor device is required. That is, in order to obtain a small area semiconductor device with a breakdown voltage of 3300 V or more and a small width of the termination structure, such a termination structure is necessary.
- a semi-insulating polysilicon (Semi-Insulating POlycrystalline Silicon; abbreviated name: SIPOS) film or semi-insulating silicon nitride is formed on one layer of a passivation film covering the surface of the termination structure for the purpose of stabilizing the breakdown voltage.
- a semi-insulating film high resistance film
- a (Semi-insulating Silicon Nitride; abbreviation: SinSiN) film is often used (for example, see Patent Document 2).
- the semi-insulating film is a resistive element having a continuous potential by dividing the voltage between the active region and the edge of the semiconductor device by resistance and capacitively coupling the substrate surface via an insulating film such as a silicon oxide film. Functions as a field plate.
- the resistance of the semi-insulating film is set so that the current flowing through the semi-insulating film is lower than the leak current flowing inside the substrate, and is at least 100 M ⁇ / ⁇ or more in terms of sheet resistance.
- the semi-insulating film (to be precise, the semi-insulating film / insulating film / substrate surface capacity) is charged in a time of about the time constant RC determined by the resistance R of the semi-insulating film and the capacitance C of the insulating film. .
- the charging of the semi-insulating film is completed, not only the carrier distribution on the substrate surface is modulated by the effect of the resistive field plate, but also the electric field from the outside of the semiconductor device is shielded.
- the sealing resin of the power semiconductor module is exposed to an electric field from a semiconductor device (power semiconductor device) or an electric circuit constituting the power semiconductor module.
- the history of the electric field to which the sealing resin is exposed does not become zero in terms of vector time.
- the mobile ions contained in the sealing resin move due to the electric field, and the mobile ions are unevenly distributed in the sealing resin. Then, an electric field due to movable ions is generated, which affects the semiconductor device.
- the electric field from the outside is shielded by the fixed potential surface electrode, but the fixed potential surface electrode does not exist in most of the termination structure. If the breakdown voltage of the termination structure is significantly reduced by the electric field from the movable ions, it means that the breakdown voltage of the semiconductor device is greatly reduced. As a test for simulating the above situation, there is a long-time high temperature reverse bias test, which is used for reliability evaluation of a power semiconductor module or a semiconductor device.
- the reliability of the semiconductor device can be improved.
- the semi-insulating film plays an important role in improving the reliability of the power semiconductor device.
- the present technology has been made to solve the above-described problems.
- a half-shape in an appropriate form is provided.
- An object is to provide a semiconductor device provided with an insulating film and having a small area, high withstand voltage, and high reliability.
- a semiconductor device includes a first conductivity type semiconductor substrate, an active region partially formed on a surface of the semiconductor substrate, a surface of the semiconductor substrate in contact with the active region, and An electric field relaxation layer containing an impurity of a second conductivity type formed to surround the active region; an insulating film formed so as to cover part of the active region and the electric field relaxation layer; and a part on the insulating film And a first electrode formed over the active region and a position on the insulating film corresponding to at least a part of the position where the electric field relaxation layer is formed, and has a floating potential.
- a plurality of metal layers the plurality of metal layers being spaced apart from each other in a direction away from the first electrode, and surrounding each of the first electrodes, and on the insulating film and the semiconductor substrate Straddling A second electrode disposed around the plurality of metal layers, and a semi-insulating film formed on the insulating film extending from the first electrode to the second electrode, An electric field relaxation layer is formed extending in a direction away from the active region, and a space charge amount of the second conductivity type impurity contained decreases as the distance from the active region decreases, and the first electrode of each metal layer The width in the direction away from the outer edge of each of the metal layers, the outer edge being the end closer to the second electrode, and the first adjacent to the metal layer in the direction approaching the first electrode. Assuming that the distance between one electrode or the outer edge of the other metal layer is D, the W / D for each metal layer decreases as the distance from the first electrode increases.
- the potential distribution on the semiconductor substrate surface due to the semi-insulating film after being charged becomes the potential distribution on the semiconductor substrate surface due to the electric field relaxation layer. Get closer to.
- a balance between a plurality of electric field concentration points inside the semiconductor substrate is maintained before and after the semi-insulating film is charged, and a semiconductor device with a small area, high withstand voltage, and high reliability can be realized.
- FIG. 2 is a schematic cross-sectional view showing, in an enlarged manner, a termination structure viewed from a section line II in FIG. 1. It is a figure which shows the electric potential distribution of the radial direction of the semi-insulating film of the semiconductor device regarding embodiment. It is a schematic cross section which expands and shows the termination
- FIG. 1 is a plan view showing a configuration of a semiconductor device 1 according to the present embodiment.
- the semiconductor device 1 is a vertical PIN diode having a simple active region shape.
- FIG. 2 is a schematic cross-sectional view showing, in an enlarged manner, the termination structure seen from the section line II in FIG.
- the semiconductor device 1 includes a semiconductor substrate 11, a base layer 12 (active region), an electric field relaxation layer 13, a stopper layer 14, an anode electrode 15, and a stopper electrode 16.
- the semiconductor substrate 11, the stopper layer 14, and the cathode layer 17 have N-type conductivity.
- the base layer 12 (active region) and the electric field relaxation layer 13 have P-type conductivity.
- the N type corresponds to the first conductivity type
- the P type corresponds to the second conductivity type.
- the semiconductor substrate 11 is an N-type semiconductor substrate.
- the semiconductor substrate 11 contains N-type impurities at a relatively low concentration.
- the N-type impurity having a relatively low concentration may be described as “N ⁇ ”.
- FIG. 1 corresponds to a plan view of the semiconductor device 1 viewed from one side in the thickness direction of the semiconductor substrate 11.
- the semiconductor substrate 11 has a rectangular shape, specifically, a square shape when viewed from one side in the thickness direction.
- the base layer 12 corresponds to an active region of the semiconductor device 1.
- the base layer 12 is formed apart from the outermost edge of the semiconductor substrate 11 in a partial region in the surface portion (the surface of the semiconductor substrate 11) on one side in the thickness direction of the semiconductor substrate 11. Specifically, the base layer 12 is formed at the center of the surface portion on one side in the thickness direction of the semiconductor substrate 11.
- the base layer 12 is formed in a substantially square shape when viewed from one side in the thickness direction of the semiconductor substrate 11, specifically, a square shape constituted by arcuate curves having four corners of 90 °.
- the base layer 12 is composed of a P-type impurity layer containing P-type impurities at a relatively high concentration.
- the electric field relaxation layer 13 is formed in the surface portion on one side in the thickness direction of the semiconductor substrate 11 from the outermost edge of the base layer 12 toward the outermost edge of the semiconductor substrate 11.
- the electric field relaxation layer 13 in the present embodiment is formed in an annular shape so as to surround the base layer 12 when viewed from one side in the thickness direction of the semiconductor substrate 11.
- the radial direction of the electric field relaxation layer 13 may be simply referred to as “radial direction”
- the circumferential direction of the electric field relaxation layer 13 may be simply referred to as “circumferential direction”.
- the electric field relaxation layer 13 is a P-type impurity layer in which the implantation amount gradually decreases from the inner side to the outer side in the radial direction.
- the electric field relaxation layer 13 is a gradient-doped P-type impurity layer and is referred to as a VLD layer (hereinafter, the electric field relaxation layer 13 may be referred to as a VLD layer 13).
- the VLD layer 13 has an injection amount that gradually decreases toward the outside, but the heat treatment is performed collectively for the entire VLD layer 13. Therefore, the P-type impurity concentration of the VLD layer 13 gradually decreases toward the outside, and the PN junction depth of the VLD layer 13 decreases gradually toward the outside.
- the region having the same implantation amount in the VLD layer 13 is a substantially square ring, specifically, a square ring formed of 90 ° arc-shaped curves at the four corners when viewed from one side in the thickness direction of the semiconductor substrate 11. It is formed. The innermost edge of the VLD layer 13 is in contact with the outermost edge of the base layer 12.
- the injection amount of the VLD layer 13 is about 1.2 to 2 times the resurf condition at the inner edge, and about 0.15 to 0.5 times the resurf condition at the outer edge, and the inner edge and the outer edge In between, it decreases gradually and linearly with respect to the radial distance, or gradually and linearly decreases. It is necessary to lower the injection amount of the outer edge portion as the withstand pressure is higher.
- the width of the VLD layer 13 can be made not more than twice the thickness of the semiconductor substrate 11 (more precisely, the thickness of the drift layer which is the N ⁇ region).
- the stopper layer 14 is formed on the outer edge portion of the semiconductor substrate 11 in the surface portion on one side in the thickness direction of the semiconductor substrate 11 so as to be separated from the electric field relaxation layer 13.
- the stopper layer 14 is composed of an N-type impurity layer containing N-type impurities at a relatively high concentration.
- the anode electrode 15 is provided on the surface portion on one side in the thickness direction of the base layer 12.
- the anode electrode 15 is formed in contact with a part of the surface portion on one side in the thickness direction of the base layer 12.
- the anode electrode 15 has a substantially square shape slightly larger than the base layer 12 when viewed from one side in the thickness direction of the semiconductor substrate 11, specifically, a square shape in which the four corners are 90 ° arc-shaped curves. is there.
- the stopper electrode 16 is provided on the surface portion on one side in the thickness direction of the stopper layer 14.
- the stopper electrode 16 is formed in contact with a part of the surface portion on one side in the thickness direction of the stopper layer 14.
- the innermost edge of the stopper electrode 16 is located, for example, in the middle between the outermost edge of the electric field relaxation layer 13 and the innermost edge of the stopper layer 14 when viewed from one side in the thickness direction of the semiconductor substrate 11.
- the cathode layer 17 is in the surface portion of the semiconductor substrate 11 opposite to the side on which the base layer 12 is formed, that is, the surface portion on the other side in the thickness direction of the semiconductor substrate 11 (hereinafter sometimes referred to as “substrate back surface”). Formed inside.
- the cathode layer 17 is formed over the entire back surface of the substrate.
- the cathode layer 17 is composed of an N-type impurity layer containing N-type impurities at a relatively high concentration.
- the cathode electrode 18 is provided on the surface portion on the other side in the thickness direction of the cathode layer 17.
- the cathode electrode 18 is provided over the entire surface portion on the other side in the thickness direction of the cathode layer 17.
- the first insulating film 19 is provided on the surface portion on one side in the thickness direction of the semiconductor substrate 11. Specifically, the first insulating film 19 includes a part on the surface portion of the base layer 12, a surface portion from the innermost edge of the electric field relaxation layer 13 to the innermost edge of the stopper layer 14, and the surface portion of the stopper layer 14. Formed on top part.
- the anode field plate 20 is a portion of the anode electrode 15 that protrudes radially outward from the base layer 12 as seen from one side in the thickness direction of the semiconductor substrate 11 and covers a part of the electric field relaxation layer 13.
- the stopper field plate 21 is a portion of the stopper electrode 16 that protrudes radially inward from the stopper layer 14 when viewed from one side in the thickness direction of the semiconductor substrate 11.
- the floating potential metal wiring group 22 is a metal layer group disposed between the outermost edge of the anode electrode 15 and the innermost edge of the stopper electrode 16 on the surface portion on one side in the thickness direction of the first insulating film 19.
- the floating potential metal wiring group 22 is formed of the same metal as the anode electrode 15 and the stopper electrode 16.
- the floating potential metal wiring group 22 includes a metal wiring 31, a metal wiring 32, a metal wiring 33, a metal wiring 34 and a metal wiring 35 which are a plurality of metal layers.
- the plurality of metal wirings 31 to 35 are each formed in an annular shape when viewed from one side in the thickness direction of the semiconductor substrate 11, and are arranged side by side in the radial direction at intervals.
- Each of the metal wirings 31 to 35 is formed in a substantially square annular shape, specifically, a square annular shape having four corners formed by 90 ° arcuate curves when viewed from one side in the thickness direction of the semiconductor substrate 11. .
- the distance between adjacent ones increases as the distance from the anode electrode 15 toward the stopper electrode 16 increases.
- the radial widths of the metal wirings 31 to 35 become smaller from the anode electrode 15 side toward the stopper electrode 16 side.
- the semi-insulating film 23 consists of the anode electrode 15, the floating potential metal wiring group 22, the stopper electrode 16, and the first insulating film 19 between them from the outer edge of the anode electrode 15 to the outermost edge of the stopper electrode 16. It is provided so as to cover the surface portion on one side in the thickness direction.
- the second insulating film 24 is provided so as to cover the surface portion on one side in the thickness direction of the semi-insulating film 23.
- the structure outside the base layer 12 when viewed from one side in the thickness direction of the semiconductor substrate 11 is a termination structure.
- the termination structure includes the electric field relaxation layer 13, the stopper layer 14, the first insulating film 19, the stopper electrode 16 including the stopper field plate 21, the anode field plate 20, the floating potential metal wiring group 22, the semi-insulating film 23, and
- the second insulating film 24 is provided.
- a bias voltage is applied between the cathode electrode 18 on the back surface of the substrate and the anode electrode 15 in contact with the base layer 12.
- the semiconductor device 1 functions as a PN junction diode.
- the stopper layer 14 and the stopper electrode 16 have substantially the same potential as the cathode electrode 18. Therefore, during reverse bias, the same voltage as the bias voltage is generated between the anode electrode 15 and the stopper electrode 16.
- the injection amount of the VLD layer 13 is about 1.2 to 2 times the resurf condition at the inner edge, and about 0.2 to 0.5 times the resurf condition at the outer edge.
- the resurf condition is a guide amount for depletion to the outermost surface of the impurity layer when a reverse bias close to the withstand voltage is applied. Therefore, the portion closer to the outside of the VLD layer 13 has the reverse bias below the withstand voltage and the outermost surface. Until depleted. On the other hand, the portion closer to the inside of the VLD layer 13 is not depleted to the outermost surface until the reverse bias reaches the withstand voltage.
- the potential of the surface of the semiconductor substrate 11 from the outermost edge of the base layer 12 to the innermost edge of the stopper layer 14 at the time of reverse bias near the withstand voltage is from the anode potential to the cathode. Although it increases monotonously to the potential, it changes with a downward change.
- the potential of the surface of the semiconductor substrate 11 from the outermost edge of the base layer 12 to the innermost edge of the stopper layer 14 changes from the anode potential to the cathode potential, and the first-order derivative with respect to the radial distance is positive.
- the second derivative with respect to the directional distance is positive and takes a value lower than the potential when linearly connected from the anode potential to the cathode potential.
- the radial potential distribution of the semi-insulating film 23 will be considered.
- a voltage is generated between the anode electrode 15 and the stopper electrode 16, a minute current flows through the semi-insulating film 23, and a voltage drop (resistance division) is generated.
- the semi-insulating film 23 is short-circuited by the anode field plate 20, the stopper field plate 21 and the floating potential metal wiring group 22 in a section corresponding to the outermost edge of the base layer 12 and the innermost edge of the stopper layer 14. For this reason, a voltage drop occurs only in a portion where the anode field plate 20, the stopper field plate 21 and the floating potential metal wiring group 22 are not present.
- FIG. 3 is a diagram showing a radial potential distribution of the semi-insulating film 23.
- the vertical axis indicates the potential
- the horizontal axis indicates the radial distance.
- Graph 27 (solid line) is obtained by smoothing graph 25 (solid line).
- the potential of the semi-insulating film 23 in a state where charging is completed monotonically increases from the anode potential to the cathode potential in a state of partial averaging (smoothing) in the radial direction.
- the distribution is convex downward.
- the potential of the semi-insulating film 23 in a state where the charging is completed has a linear distribution as shown by a graph 26 (broken line) in FIG.
- the potential of the semi-insulating film 23 in the state where the charging shown in the graph 25 is completed monotonously increases from the anode potential to the cathode potential, and in the state where the graph 25 is smoothed (that is, the graph 27), the radial direction
- the second derivative with respect to the distance is positive and takes a value lower than the potential when linearly connected from the anode potential to the cathode potential shown in the graph 26.
- the response time of carriers inside the semiconductor substrate 11 is much shorter than the time required for charging the semi-insulating film 23. For this reason, the potential on the surface of the semiconductor substrate 11 is not affected by the semi-insulating film 23 at a time (initial state) shortly after the reverse bias is applied. However, as the semi-insulating film 23 is charged, the semiconductor substrate 11 begins to be affected by the semi-insulating film 23. When the charging of the semi-insulating film 23 is completed (steady state), the potential of the surface of the semiconductor substrate 11 is forcibly drawn to the potential of the semi-insulating film 23.
- the semi-insulating film 23 when the floating potential metal wiring group 22 does not exist, in other words, when the conventional semi-insulating film 23 is provided, the semi-insulating film 23 is linear with respect to the radial direction by charging the semi-insulating film 23. It has a potential distribution (see graph 26). Then, even if the potential distribution on the surface of the semiconductor substrate 11 including the electric field relaxation layer 13 is convex downward in the initial state (by making the impurity implantation amount of the electric field relaxation layer 13 as described above), it is forced in the steady state. To be linear. As a result, the balance of the electric field concentration points appropriately dispersed inside the semiconductor substrate 11 by the electric field relaxation layer 13 may be lost, and the breakdown voltage may appear.
- the problem is solved. That is, by forming the floating potential metal wiring group 22 as in the semiconductor device 1, the potential distribution due to the semi-insulating film 23 in the steady state can be brought close to the potential distribution on the surface of the semiconductor substrate 11 in the initial state. it can. Therefore, even when the potential of the surface of the semiconductor substrate 11 is forcibly attracted to the potential of the semi-insulating film 23 by charging of the semi-insulating film 23, the change in the potential of the surface of the semiconductor substrate 11 before and after charging of the semi-insulating film 23 is Thus, the balance of the electric field concentration points inside the semiconductor substrate 11 is kept unchanged. Therefore, the withstand voltage drop over time of the semiconductor device 1 can be suppressed, and can be eliminated in some cases.
- the smoothed potential distribution of the semi-insulating film 23 in the steady state protrudes downward with respect to the radial distance in the same manner as the potential distribution on the surface of the semiconductor substrate 11 in the initial state.
- the floating potential metal wiring group 22 should not be in contact with the surface of the electric field relaxation layer 13.
- the floating potential metal wiring group 22 and the surface of the electric field relaxation layer 13 should not be directly connected by a contact hole or the like. This is because when the metal wirings 31 to 35 are connected to the surface of the electric field relaxation layer 13 by contact holes, the potentials of the metal wirings 31 to 35 are always equal to the potential of the surface of the electric field relaxation layer 13 connected by the contact holes. Become. As a result, the potential of each of the metal wirings 31 to 35 is fixed at the initial potential on the surface of the electric field relaxation layer 13 to which each of the metal wirings 31 to 35 is connected.
- the semi-insulating film 23 only connects the potentials of the metal wirings 31 to 35 fixed at the initial potential of the surface of the electric field relaxation layer 13 between the metal wirings 31 to 35 linearly. Only the function of will be provided. That is, the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22 does not have the function of the resistive field plate as a whole.
- the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22 does not have the function of a resistive field plate as a whole, the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22 is not supplied from the outside of the semiconductor device.
- the electric field cannot be shielded. This is because, in order to shield the electric field from the outside of the semiconductor device, in the steady state, the potential of the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22 is independent of the semiconductor substrate 11 including the electric field relaxation layer 13. It is necessary to be decided.
- FIG. 4 is an enlarged schematic cross-sectional view showing the termination structure of the semiconductor device 2 according to the modification of the present embodiment.
- the configuration when the semiconductor device 2 is applied to a PIN diode will be described as in the first embodiment. Since the semiconductor device 2 is similar in configuration to the semiconductor device 1 of the first embodiment, the same configuration is denoted by the same reference numeral, and common description is omitted.
- the floating potential metal wiring group 40 includes a metal wiring 41, a metal wiring 42, a metal wiring 43, a metal wiring 44, and a metal wiring 45, which are a plurality of metal layers.
- the plurality of metal wirings 41 to 45 are each formed in an annular shape when viewed from one side in the thickness direction of the semiconductor substrate 11, and are arranged side by side in the radial direction at intervals.
- Each of the metal wirings 41 to 45 is formed in a substantially square ring shape, specifically, a square ring shape having four corners formed by 90 ° arcuate curves as viewed from one side in the thickness direction of the semiconductor substrate 11. .
- the distance between adjacent ones increases as the distance from the anode electrode 15 toward the stopper electrode 16 increases.
- the radial widths of the metal wirings 31 to 35 are the same regardless of the distance from the anode electrode 15. Even in such a configuration, as shown in FIG. 5, the potential of the semi-insulating film 23 in the steady state has a downward convex distribution in a smoothed state.
- the floating potential metal wiring group 22 (or the floating potential metal wiring group 40) includes five metal wirings 31 to 35 (or metal wirings 41 to 45). This is a simplified configuration. Actually, there are appropriate widths, intervals, and numbers of metal wirings depending on the breakdown voltage or the material of the first insulating film, the thickness of the first insulating film, and the material of the semiconductor substrate.
- the width of the electric field relaxation layer 13 should be considered to increase the number of metal wirings first, rather than increasing the width and interval of the corresponding metal wirings 41 to 45. This is because if the width of the metal wirings 41 to 45 is too wide, a strong electric field is generated in the first insulating film 19 and the semiconductor substrate 11 below the ends of the metal wirings 41 to 45. If this electric field is too strong, discharge or breakdown voltage reduction may occur. Therefore, the width of the metal wirings 41 to 45 should be shortened to such an extent that an excessively strong electric field is not generated below the end portions of the metal wirings 41 to 45.
- the width of the metal wirings 41 to 45 can be made relatively wide.
- the width of the metal wirings 41 to 45 is allowed to be about 25 to 50 ⁇ m.
- the floating potential metal wiring group 22 (or the floating potential metal wiring group 40) is provided up to the upper part of the outer edge portion of the electric field relaxation layer 13, as shown in FIG.
- the metal wiring 34 and the metal wiring 35 (or the metal wiring 44 and the metal wiring 45) from the upper part of the outer edge of the electric field relaxation layer 13 to the middle part.
- the floating potential metal wiring group 22a (or the floating potential metal wiring group 40a) is omitted, the potential of the semi-insulating film 23 in the steady state still has a downwardly convex distribution, and the effect of the present invention can be obtained. .
- such a configuration may give a better effect. That is, an appropriate position exists at the outermost edge of the floating potential metal wiring group 22.
- the outermost metal wiring 35 when the optimum width of the outermost metal wiring 35 is below the lower limit of the width of the metal wiring that can be formed in the manufacturing process of the semiconductor device 1, the outermost metal wiring 35 is omitted. I have to. That is, an appropriate form of the floating potential metal wiring group 22 may be limited by a manufacturing process rule (width or interval of metal wiring).
- the area of the floating potential metal wiring group 22 (or the floating potential metal wiring group 40) that short-circuits the semi-insulating film 23 between the outermost edge of the anode field plate 20 and the innermost edge of the stopper field plate 21 is formed.
- Ratio in other words, the ratio of “the width of the metal wiring” and “the distance from the outer edge of the metal wiring to the outer edge of the inner metal wiring (the distance between the outer edges)” As long as it becomes smaller toward, the smoothed potential distribution of the semi-insulating film 23 in the steady state becomes convex downward.
- the width of the metal wiring may be configured to decrease as the distance from the base layer 12 as the active region, or when the width of the metal wiring is constant, The configuration may be such that the distance between the outer edge ends increases with distance from the base layer 12 as the active region.
- the distance between the outer edge ends is made constant up to the middle part of the electric field relaxation layer 13, and the width of the metal wiring is reduced to the minimum width determined by the rules of the manufacturing process.
- the distance between the outer edges may be increased by making the width of the outer edge constant at the minimum width.
- the distance between the inner and outer sides of the outermost metal wiring 35 (or metal wiring 45) is preferably such that the inner distance is smaller than the outer distance.
- the magnitude relationship regarding the inner and outer intervals of the outermost metal wiring 35 (or metal wiring 45) may be reversed. This is because, in the present invention, it is most important that the smoothed potential distribution of the semi-insulating film 23 in the steady state is convex downward at the upper part of the electric field relaxation layer 13 closer to the inner side, and the farthest from there. This is because the influence of the vicinity of the stopper field plate 21 is relatively less susceptible.
- the metal wiring from the upper part of the outer edge of the electric field relaxation layer 13 to the upper part of the middle, for example, the width of the metal wiring 34 b and the width of the metal wiring 35 b is the same as that of the metal wiring 33. Even in the floating potential metal wiring group 22b having the same width, the potential of the semi-insulating film 23 in the steady state still has a downward convex distribution, and the effect of the present invention can be obtained.
- the metal wiring from the upper part of the outer edge of the electric field relaxation layer 13 to the upper part of the middle part for example, [distance between the outer edges of the metal wiring 43 and the metal wiring 44b] and [ Even in the floating potential metal wiring group 40b in which the distance between the outer edges of the metal wiring 44b and the metal wiring 45b is equal to the [distance between the outer edges of the metal wiring 42 and the metal wiring 43], the semi-insulating film 23 is still in a steady state.
- This potential has a downward convex distribution, and the effect of the present invention can be obtained.
- the variation in potential of the semi-insulating film 23 from the upper part of the outer edge of the electric field relaxation layer 13 to the upper part of the middle is reduced as compared with the semiconductor device 1a and the semiconductor device 2a.
- the potential in the circumferential direction of the semi-insulating film 23 is equal at a location where the metal wiring 34b and the metal wiring 35b (or the metal wiring 44b and the metal wiring 45b) are disposed.
- the breakdown voltage is more stable in the semiconductor device 1b and the semiconductor device 2b than in the semiconductor device 1a and the semiconductor device 2a.
- FIG. 8 is a graph showing a simulation result regarding the breakdown voltage in the semiconductor device 1 and the semiconductor device 1a of the present embodiment.
- the vertical axis represents the breakdown voltage (V) at a temperature of 298 K
- the horizontal axis represents the implantation amount (cm ⁇ 2 ) at the inner edge of the VLD layer 13.
- FIG. 9 is a graph showing simulation results regarding the electric field in the semiconductor device 1 and the semiconductor device 1a of the present embodiment.
- the vertical axis represents the maximum electric field (V / cm) inside the semiconductor substrate at a reverse bias of 6500 V
- the horizontal axis represents the implantation amount (cm ⁇ 2 ) at the inner edge of the VLD layer 13.
- the injection amount of the outer edge of the VLD layer 13 is 1/8 of the innermost side.
- the number of metal wirings of the semiconductor device 1 is 40, the width of the innermost metal wiring 31 is 25 ⁇ m, the width of the outermost metal wiring 35 is 5 ⁇ m, and the width of each metal wiring 31 to 35 is from the inside to the outside. Decreases linearly in steps.
- the width of the anode field plate 20 is 30 ⁇ m.
- the semiconductor device 1a is obtained by omitting the fifteenth and subsequent pieces of metal wiring of the semiconductor device 1 counted from the inside.
- the initial state of the semiconductor device 1 from which the anode field plate 20 and the floating potential metal wiring group 22 are omitted is indicated by a thin broken line indicated by reference numeral “51a”.
- the steady state without the floating potential metal wiring group 22 is indicated by a broken line indicated by reference numeral “52a”, and the steady state of the semiconductor device 1 without the floating potential metal wiring group 22 is indicated by reference numeral “53a”.
- the steady state of the semiconductor device 1a is indicated by a one-dot chain line indicated by reference numeral “54a”, and the steady state of the semiconductor device 1 is indicated by a solid line indicated by reference numeral “55a”.
- the initial state of the semiconductor device 1 from which the anode field plate 20 and the floating potential metal wiring group 22 are omitted is indicated by a thin broken line indicated by reference numeral “51 b”, and from the semiconductor device 1 to the anode field plate 20.
- the steady state without the floating potential metal wiring group 22 is indicated by a broken line indicated by reference numeral “52b”, and the steady state of the semiconductor device 1 without the floating potential metal wiring group 22 is indicated by reference numeral “53b”.
- the steady state of the semiconductor device 1a is indicated by a one-dot chain line indicated by reference numeral “54b”, and the steady state of the semiconductor device 1 is indicated by a solid line indicated by reference numeral “55b”.
- the steady state is obtained by omitting the anode field plate 20 and the floating potential metal wiring group 22 from the semiconductor device 1 at an injection amount of 1.2 to 1.6 ⁇ 10 12 cm ⁇ 2 at which a high breakdown voltage is obtained in the initial state.
- the breakdown voltage in the state and the breakdown voltage in the steady state after the floating potential metal wiring group 22 is omitted from the semiconductor device 1 are lower than in the initial state. In other words, the voltage that can be held at the moment of reverse bias cannot be held because the semi-insulating film 23 is charged by the continuous reverse bias.
- a measure of the time to reach a steady state is the dielectric constant and thickness of the first insulating film 19, the resistivity and thickness of the semi-insulating film 23, and the stopper electrode from the outermost edge of the anode electrode 15. Depends on the distance to the 16 innermost edges.
- the breakdown voltage is higher in the steady state of the semiconductor device 1a and in the steady state of the semiconductor device 1 than in the initial state. That is, the decrease in breakdown voltage with time due to charging of the semi-insulating film 23 is eliminated.
- the breakdown voltage is higher than that in the initial state because the electric field inside the semiconductor substrate 11 has a more appropriate distribution due to the charging of the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22.
- the withstand voltage close to the initial state can be obtained if the reverse bias application time required for the withstand voltage measurement is 1 second.
- the reverse bias is maintained in the avalanche breakdown state, a creep phenomenon in which the breakdown voltage fluctuates is observed, and finally a steady-state breakdown voltage is reached.
- the resistivity of the semi-insulating film 23 decreases exponentially with increasing temperature. If the activation energy of the semi-insulating film 23 is 0.5 eV, the resistivity of the semi-insulating film 23 at a temperature of 398K is 1/100 of the temperature 298K, and the time constant at the temperature 398K is 0.1 second. Therefore, when the pressure resistance is measured at a temperature of 398K, a steady-state pressure resistance can be obtained.
- the withstand voltage obtained in the actual withstand voltage measurement largely depends on the magnitude relationship between the charging time constant of the semi-insulating film 23 and the time during which the reverse bias is applied.
- the semiconductor device 1 and the semiconductor device 1a cannot be used in a range outside the injection amount of 1.2 to 1.6 ⁇ 10 12 cm ⁇ 2 .
- the steady-state semiconductor internal maximum electric field of the semiconductor device 1a and the steady-state semiconductor internal maximum electric field of the semiconductor device 1 at an injection amount of 1.2 to 1.6 ⁇ 10 12 cm ⁇ 2 are the initial state. And not much different.
- the semiconductor device includes a first conductivity type (N-type) semiconductor substrate 11, a base layer 12 as an active region partially formed on the surface of the semiconductor substrate 11, an electric field relaxation layer 13, and the like. , A first insulating film 19, an anode electrode 15, metal wirings 31 to 35 as a plurality of metal layers, a stopper electrode 16, and a semi-insulating film 23.
- the electric field relaxation layer 13 contains a second conductivity type (P-type) impurity formed in contact with the base layer 12 and surrounding the base layer 12 on the surface of the semiconductor substrate 11.
- the first insulating film 19 is formed so as to cover a part of the base layer 12 and the electric field relaxation layer 13.
- the anode electrode 15 is formed across a part of the first insulating film 19 and the base layer 12.
- the metal wirings 31 to 35 are formed at a position on the first insulating film 19 corresponding to at least a part of the position where the electric field relaxation layer 13 is formed, and have a floating potential.
- the metal wires 31 to 35 are separated from each other in a direction away from the anode electrode 15 and are formed so as to surround the anode electrode 15.
- the stopper electrode 16 is formed over the first insulating film 19 and the semiconductor substrate 11 and is disposed so as to surround the metal wirings 31 to 35.
- the semi-insulating film 23 is formed on the first insulating film 19 extending from the anode electrode 15 to the stopper electrode 16.
- the electric field relaxation layer 13 is formed extending in a direction away from the base layer 12, and the concentration of the second conductivity type impurity contained decreases as the distance from the base layer 12 increases.
- each metal wiring in the direction away from the anode electrode 15 is W
- the outer edge end that is the end of each metal wiring close to the stopper electrode 16 and the metal wiring in the direction approaching the anode electrode 15 are arranged adjacent to each other.
- the W / D for each metal wiring decreases as the distance from the anode electrode 15 increases.
- the width W of the metal wiring 31 is W1
- the width W of the metal wiring 32 is W2
- the width W of the metal wiring 33 is W3
- the width W of the metal wiring 34 is W4, and the width W of the metal wiring 35 is W5.
- the distance D between the anode electrode 15 including the anode field plate 20 and the metal wiring 31 is D1
- the distance D between the metal wiring 31 and the metal wiring 32 is D2
- the distance D between the metal wiring 32 and the metal wiring 33 is D3.
- the semi-insulating film 23 is short-circuited by the metal wirings 31 to 35, so that the potential distribution on the surface of the semiconductor substrate 11 by the charged semi-insulating film 23 becomes the semiconductor substrate by the electric field relaxation layer 13. 11 approaches the potential distribution on the surface.
- the electric field concentration point in the semiconductor substrate 11 is kept balanced before and after the semi-insulating film 23 is charged, and a semiconductor device having a small area, high withstand voltage, and high reliability can be realized.
- the anode electrode 15 including the anode field plate 20 may be referred to as a “first electrode”, and the stopper electrode 16 including the stopper field plate 21 may be referred to as a “second electrode”.
- the injection amount of the electric field relaxation layer (VLD layer) 13 is preferably seamlessly and linearly reduced with respect to the radial distance between the inner edge portion and the outer edge portion, or gradually and gradually reduced gradually. It does not necessarily have to be linear. In other words, the effect of the present invention can be obtained regardless of whether the injection amount of the electric field relaxation layer (VLD layer) 13 gradually decreases upward or downward from the inside to the outside.
- the electric field relaxation layer 13 can be replaced with an electric field relaxation layer 59, an electric field relaxation layer 66, and an electric field relaxation layer 69 which will be described later.
- metal wirings 31 to 35 can be replaced with the metal wirings 41 to 45.
- FIG. 10 is an enlarged schematic cross-sectional view showing the termination structure of the semiconductor device 3 in the present embodiment.
- the electric field relaxation layer 59 includes a P-type impurity layer 60, a P-type impurity layer 61, a P-type impurity layer 62, a P-type impurity layer 63, a P-type impurity layer 64, and a P-type impurity having a plurality of layer structures.
- Layer 65 is provided.
- the plurality of P-type impurity layers 60 to 65 have the same implantation amount and are spaced apart from each other in the direction away from the base layer 12.
- the plurality of P-type impurity layers 60 to 65 are formed so as to surround the base layer 12 when viewed from one side in the thickness direction of the semiconductor substrate 11.
- the P-type impurity layer 60 formed on the innermost side in the radial direction of the electric field relaxation layer 59 is formed in contact with the base layer 12.
- the spacing between adjacent P-type impurity layers in the radial direction increases linearly from the inner side to the outer side in the radial direction.
- the widths of the P-type impurity layers 61 to 65 excluding the innermost P-type impurity layer 60 are linearly reduced from the inner side to the outer side in the radial direction.
- the distance between the outer edges of adjacent P-type impurity layers 60 to 65 is constant.
- the width of the innermost P-type impurity layer 60 is determined separately based on the concentration and depth of the base layer 12.
- the electric field relaxation layer 59 has a distribution of discrete acceptor ions in the radial direction.
- the partial average in the radial direction of the space charge amount of the acceptor ions is gradually decreased stepwise in a linear manner toward the outside of the semiconductor device.
- the electric field relaxation layer 59 is called LNFLR (Linearly-Narrowed Field Limiting Ring) (hereinafter, the electric field relaxation layer 59 may be called LNFLR 59).
- the optimum injection amount of LNFLR 59 is about 2.5 times the RESURF condition. However, if the injection amount is in the range of about 1.5 to 3.5 times the RESURF condition, a sufficiently high breakdown voltage can be obtained.
- the anode field plate 20 and the plurality of metal wires 31 to 35 constituting the floating potential metal wire group 22 are provided corresponding to the upper portions of the P-type impurity layers 60 to 65, respectively.
- the width of the anode field plate 20 and the width of the metal wirings 31 to 35 are approximately equal to the widths of the P-type impurity layers 60 to 65, respectively.
- the surface potential of the semiconductor substrate 11 from the outermost edge of the base layer 12 to the innermost edge of the stopper layer 14 during reverse bias is partially averaged (smoothed) from the anode potential to the cathode potential. Then, it changes with a convex change downward.
- the gap region of the P-type impurity layers 60 to 65 is depleted to the outermost surface with a relatively low reverse bias voltage, and a lateral electric field, that is, a potential is generated in the gap region of the P-type impurity layers 60 to 65. A gradient occurs.
- the smoothed potential on the surface of the semiconductor substrate 11 in the initial state has a downwardly convex quadratic distribution.
- the smoothed potential in the steady state of the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22 has a quadratic distribution that is convex downward, but in the semiconductor device 3, the position of the anode field plate 20 and Since the width and the position and width of the metal wirings 31 to 35 are respectively matched with the P-type impurity layers 60 to 65, the potential distribution on the surface of the semiconductor substrate 11 in the steady state is the same as that of the surface of the semiconductor substrate 11 in the initial state. It becomes quite close to the potential distribution.
- the electric field inside the semiconductor substrate 11 is not easily disturbed by the semi-insulating film 23 after charging. That is, fluctuations in breakdown voltage due to charging of the semi-insulating film 23 are unlikely to occur.
- the metal wiring 34 and the metal wiring 35 arranged on the upper part of 65 may be omitted. That is, a position on the first insulating film 19 corresponding to a position where at least a part of the LNFLR 59 is formed, that is, a position where the P-type impurity layer 61, the P-type impurity layer 62, and the P-type impurity layer 63 are formed.
- the floating potential metal wiring group 22a may be formed.
- the floating potential metal wiring group 22b is disposed on the outer side of the P-type impurity layer 64 and the P-type impurity layer 65.
- the widths of the metal wiring 34 b and the metal wiring 35 b may be equal to the width of the metal wiring 33 disposed on the P-type impurity layer 63.
- the metal wiring 34c having the same width as the metal wiring 33 covers the entire upper portion of the P-type impurity layer 64, and the metal wiring 35c having the same width as the metal wiring 33 is P.
- the entire upper portion of the type impurity layer 65 may be covered.
- the metal wiring disposed on the P-type impurity layer 64 is omitted, and the metal wiring 35c having the same width as the metal wiring 33 is formed on the P-type impurity layer 65. You may arrange.
- the P-type impurity layers 60 to 65 are formed to be spaced apart from each other.
- an electric field relaxation layer 66 (LNFLR 66) in which some of the P-type impurity layers 60 to 65 are connected to each other inside may be formed. That is, the P-type impurity layer 60 in contact with the base layer 12 and the P-type impurity layer 61 disposed adjacent to the P-type impurity layer 60 may be connected to each other. Even in such a form, the partial average in the radial direction of the space charge amount of the acceptor ions is gradually reduced stepwise linearly toward the outside of the semiconductor device.
- the portion corresponding to the diffusion layer is a lower concentration P-type impurity region, it is easily depleted with a relatively low reverse bias voltage. Therefore, the portion corresponding to the diffusion layer extending in the radial direction along the surface of the semiconductor substrate 11 is depleted to the outermost surface with a relatively low reverse bias voltage. That is, even in a form in which the diffusion layer is expanded by relatively strong thermal diffusion, the potential of the surface of the semiconductor substrate 11 in the initial state has a downward convex quadratic function distribution in a smoothed state.
- the diffusion layer is widened by relatively strong thermal diffusion, electric field concentration inside the semiconductor substrate 11 can be suppressed, and higher breakdown voltage can be obtained.
- an electric field relaxation layer 66 (LNFLR 66) in which some of the P-type impurity layers 60 to 65 are connected to each other is formed.
- the “width of the P-type impurity layers 60 to 65” described above is the “region into which impurity ions are implanted to form the P-type impurity layers 60 to 65 (P In other words, the width of the implantation windows of the type impurity layers 60 to 65). That is, the width of the metal wirings 31 to 35 is smaller than the width of the P-type impurity layers 60 to 65.
- the interval between adjacent P-type impurity layers increases linearly from the inside to the outside, and the widths of the P-type impurity layers 61 to 65 decrease linearly from the inside to the outside. Therefore, it is desirable that the distance between the outer edges of the adjacent P-type impurity layers 60 to 65 is constant, but the partial average implantation amount of the electric field relaxation layers 59 and 66 may be gradually decreased from the inside toward the outside. For example, it is not always necessary to follow this rule. In other words, the effect of the present invention can be obtained regardless of whether the partial average injection amount of the electric field relaxation layers 59 and 66 gradually decreases upward or downward from the inside to the outside.
- FIG. 13 is an enlarged schematic cross-sectional view showing the termination structure of the semiconductor device 4 in a modification of the present embodiment.
- the electric field relaxation layer 69 includes a P-type impurity layer 70, a P-type impurity layer 71, a P-type impurity layer 72, a P-type impurity layer 73, a P-type impurity layer 74, and a P-type impurity layer 75 as a plurality of layer structures.
- the plurality of P-type impurity layers 70 to 75 are formed at intervals.
- the plurality of P-type impurity layers 70 to 75 are formed so as to surround the base layer 12 when viewed from one side in the thickness direction of the semiconductor substrate 11.
- the P-type impurity layer 70 formed on the innermost side in the radial direction of the electric field relaxation layer 69 is formed in contact with the base layer 12.
- the interval between the P-type impurity layers 70 to 75 adjacent in the radial direction increases from the inner side to the outer side in the radial direction.
- the widths of the P-type impurity layers 70 to 75 are constant.
- the amount of space charge contained in the electric field relaxation layer 69 (more precisely, the partial average of the amount of space charge) is gradually reduced toward the outside of the semiconductor device.
- the injection amount of the electric field relaxation layer 69 is optimally about 2.5 times the RESURF condition. However, if the injection amount is in the range of about 1.5 to 3.5 times the RESURF condition, a relatively high breakdown voltage can be obtained.
- the anode field plate 20 and the plurality of metal wires 41 to 45 constituting the floating potential metal wire group 40 are provided corresponding to the upper portions of the P-type impurity layers 70 to 75, respectively.
- the width of the anode field plate 20 and the width of the metal wirings 41 to 45 are approximately equal to the widths of the P-type impurity layers 70 to 75, respectively.
- the effect of the semiconductor device 4 is the same as that of the semiconductor device 3. Further, in the semiconductor device 4, since the width of the floating potential metal wiring group 40 is constant, it is difficult to be restricted by the manufacturing process. However, since the electric field relaxation layer 69 of the semiconductor device 4 is more difficult to reduce the electric field inside the semiconductor substrate than the LNFLR 59 of the semiconductor device 3, the semiconductor device 4 has a slightly lower breakdown voltage in the initial state.
- the form in which the diffusion layer is expanded by thermal diffusion is the same as that of the semiconductor device 3b of the second embodiment.
- the arrangement positions of the P-type impurity layers 61 to 65 (or P-type impurity layers 71 to 75) and the metal wirings 31 to 35 (or metal wirings 41 to 45) are aligned. Even if the number, position, width, and interval of the impurity layer and the metal wiring are set independently, the effect according to the first embodiment can be obtained. However, depending on the positional relationship between the P-type impurity layer and the metal wiring, the electric field inside the semiconductor substrate 11 may locally increase and the initial breakdown voltage may decrease. This point is different from the first embodiment.
- FIG. 14 is a graph showing a simulation result regarding the breakdown voltage in the semiconductor device 3b of the present embodiment.
- the vertical axis represents the breakdown voltage (V) at a temperature of 298K
- the horizontal axis represents the injection amount (cm ⁇ 2 ) of LNFLR 66.
- FIG. 15 is a graph showing a simulation result regarding the electric field in the semiconductor device 3b of the present embodiment.
- the vertical axis represents the maximum electric field (V / cm) inside the semiconductor substrate at the reverse bias of 6500 V
- the horizontal axis represents the injection amount (cm ⁇ 2 ) of LNFLR 66.
- the number of P-type impurity layers 60 to 65 is 41
- the width of the implantation window of the innermost P-type impurity layer 60 is 30 ⁇ m
- the implantation of the second P-type impurity layer 61 from the innermost is performed.
- the width of the window is 25 ⁇ m
- the width of the implantation window of the outermost P-type impurity layer 65 is 5 ⁇ m
- the width of the implantation windows of the P-type impurity layers 61 to 65 excluding the innermost P-type impurity layer 60 is from the inside. Linearly decreases toward the outside.
- the anode field plate 20 and the 40 metal wirings 31 to 35 of the semiconductor device 3 are provided above the positions of the implantation windows of the lower P-type impurity layers 60 to 65.
- the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 3b, but the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 3b.
- a steady state in which the floating potential metal wiring group 22 is omitted from the semiconductor device 3b, a steady state in which the fifteenth and subsequent metal wirings 34 and the metal wiring 35 are omitted from the semiconductor device 3b, and a semiconductor The simulation result of the steady state of the apparatus 3b is shown.
- the initial state other than that in which the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 3b is almost the same as the initial state in which the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 3b. The same.
- the initial state of the semiconductor device 3b from which the anode field plate 20 and the floating potential metal wiring group 22 are omitted is indicated by a dotted line indicated by reference numeral “81a”.
- the steady state without the potential metal wiring group 22 is indicated by a broken line indicated by reference numeral “82a”, and the steady state when the floating potential metal wiring group 22 is omitted from the semiconductor device 3b is indicated by reference numeral “83a”.
- the steady state of the semiconductor device 3b from which the fifteenth and subsequent metal wirings 34 and metal wirings 35 are omitted is indicated by a one-dot chain line denoted by reference numeral "84a”
- the steady state of the device 3b is indicated by a solid line denoted by reference numeral “85a”.
- the initial state of the semiconductor device 3b from which the anode field plate 20 and the floating potential metal wiring group 22 are omitted is indicated by a dotted line indicated by reference numeral “81b”.
- the steady state without the potential metal wiring group 22 is indicated by a broken line indicated by reference numeral “82b”, and the steady state when the floating potential metal wiring group 22 is omitted from the semiconductor device 3b is indicated by reference numeral “83b”.
- the steady state of the semiconductor device 3b from which the fifteenth and subsequent metal wires 34 and metal wires 35 are omitted from the inside is indicated by a one-dot chain line indicated by reference numeral "84b”
- the steady state of the device 3b is indicated by a solid line indicated by reference numeral “85b”.
- the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 3b at an injection amount of 1.9 to 3.8 ⁇ 10 12 cm ⁇ 2 at which a particularly high breakdown voltage is obtained in the initial state.
- the steady-state withstand voltage and the steady-state withstand voltage of the semiconductor device 3b without the floating potential metal wiring group 22 are significantly lower than in the initial state.
- the breakdown voltage close to the initial state is obtained in the steady state and the steady state of the semiconductor device 3b although the fifteenth and subsequent metal wires 34 and metal wires 35 counted from the inside of the semiconductor device 3b are omitted. Has been obtained.
- the injection amount is 2.5 ⁇ 10 12 cm ⁇ 2
- the change in breakdown voltage before and after charging of the semi-insulating film 23 is small.
- the injection amount is 3.8 ⁇ 10 12 cm ⁇ 2
- the maximum electric field inside the semiconductor substrate in a steady state is remarkable although the fifteenth and subsequent metal wirings 34 and metal wirings 35 from the inside are omitted from the semiconductor device 3b. It is getting higher.
- strong electric field concentration occurs in the lower part of the innermost edge of the stopper field plate 21.
- a significant electric field concentration occurs in the lowermost portion of the innermost edge of the stopper field plate, a high breakdown voltage may be obtained, but a significant increase in leakage current and fluctuations in characteristics due to charge-up of the oxide film are caused. Therefore, it is not preferable to increase the injection amount more than necessary.
- the termination structure if a sufficiently high breakdown voltage can be obtained, it is preferable as the termination structure that the semiconductor substrate internal maximum electric field is low.
- an ideal termination structure is often not realized due to various constraints such as design, manufacturing, and cost. In that case, it is necessary to select a configuration in which a sufficiently high breakdown voltage can be obtained and the maximum electric field inside the semiconductor substrate is as low as possible within a realizable range.
- the semiconductor device 1 including the VLD layer is more advantageous in terms of the maximum electric field inside the semiconductor substrate.
- the semiconductor device 3b including LNFLR is more advantageous in view of the withstand voltage, ease of design, and ease of manufacture. In this way, the optimum form varies depending on what is important.
- the present invention can also be applied to a semiconductor device in which a current flows parallel to the substrate surface, that is, a lateral device.
- a lateral device Even in a lateral device, an electric field relaxation layer such as a VLD layer is required to achieve a breakdown voltage of 3300 V or higher.
- the semi-insulating film covers the floating potential metal wiring and the first insulating film between the metal wirings. However, even if the semi-insulating film on the floating potential metal wiring is removed. good. Further, the semi-insulating film is disposed between the upper surface of the first insulating film and the bottom surface of the metal wiring. In other words, the semi-insulating film is formed on the first insulating film and then the metal wiring is formed on the semi-insulating film. It may be formed. Even in these forms, the semi-insulating film is short-circuited by the floating potential metal wiring, and the same effect can be obtained.
- the semiconductor device in which the conductivity type of the semiconductor substrate and each impurity layer is specified as P-type or N-type has been described, but the same applies even if these conductivity types are all reversed. The effect is obtained.
- the implantation amount and the space charge amount of the acceptor ions shown above are values on the assumption that the activation rate is 100% and does not disappear in the manufacturing process after ion implantation. Therefore, when the activation rate is low, when acceptor ions are sucked out by thermal oxidation, or when the surface is shaved by etching, based on the number of activated acceptor ions finally existing in the semiconductor substrate, The injection volume should be adjusted.
- a fixed charge for example, an interface charge exists at the interface between the semiconductor substrate and the insulating film. Even when this fixed charge cannot be ignored with respect to the injection amount, the injection amount should be adjusted.
- the base layer is illustrated as being deeper than the electric field relaxation layer, but the base layer may be the same depth as the electric field relaxation layer or shallower than the electric field relaxation layer. Good.
- the base layer may have the same depth direction concentration profile as the innermost portion of the electric field relaxation layer.
- the device to which the present invention is applied is a PIN diode.
- the present invention is a Schottky barrier diode, a JBS (Junction Barrier Schottky) diode, and an MPS (Merged PIN Schottky) diode.
- a diode such as a diode, a MOSFET, an IGBT, a transistor such as a BJT (Bipolar Junction Transistor), or a thyristor.
- the device to which the present invention is applied is a PIN diode
- the electrode disposed at the outer edge of the active region is an anode electrode having the same potential as the base layer. It may be.
- the device when the device is an IGBT, the same effect can be obtained even if the electrode disposed at the outer edge of the active region is a gate electrode. This is self-evident when the gate-emitter voltage is zero when the IGBT is off. Even when the gate is negatively biased with respect to the emitter when the IGBT is off, the gate-emitter voltage is at most -15 V, which is negligible compared to the collector-emitter voltage, and this is not substantially a problem. .
- the withstand voltage class is set to 6500 V at the rated voltage, but the present invention can be applied to any withstand voltage class.
- the material of the semiconductor substrate 11 is not limited to silicon, and may be a wide band gap semiconductor having a relatively wide band gap.
- the wide band gap semiconductor for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ) -based material, or diamond may be used.
- Switching elements and diode elements composed of wide band gap semiconductors have a high withstand voltage and a high allowable current density, so that they can be made smaller than silicon.
- By using these miniaturized switching devices and rectifying devices it is possible to reduce the size of power semiconductor modules incorporating these power semiconductor devices.
- since the heat resistance is high it is possible to downsize the heat dissipating fins of the heat sink and to cool by air cooling instead of water cooling, and further reduce the size of the power semiconductor module.
- Impurities used for implantation are activated by substituting atoms of a semiconductor material, such as boron (B), nitrogen (N), aluminum (Al), phosphorus (P), arsenic (As), and indium (In). Any thing can be used. However, when the electric field relaxation layer is formed using thermal diffusion, it is desirable that the diffusion length is relatively large and the diffusion controllability is high.
- the material of the metal wiring is not only metals such as aluminum, copper or alloys, but also oxide semiconductors represented by polysilicon or indium oxide containing a large amount of impurities, other conductive ceramics, or conductive Any organic material such as a conductive polymer may be used as long as it has a sufficiently high conductivity compared to the semi-insulating film.
- the semi-insulating film material can be semi-insulating, such as ceramic or organic polymer with a reduced number of carriers. Anything is acceptable.
- SiO 2 silicon oxide
- Si 3 N 4 silicon nitride
- TEOS normal tetraethyl silicate
- SiOF fluorine-added silicon oxide which is a low dielectric constant material
- SiOC A ceramic such as (carbon-added silicon oxide) may be used, or any resin such as a resin such as polyimide or an organic polymer may be used as long as the insulating property can be obtained.
- any combination of the embodiments, or any modification of any component in each embodiment, or any component in each embodiment can be omitted.
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Abstract
The present invention is a semiconductor device that has achieved small size, high withstand voltage properties and high reliability. The present invention comprises: an electrical field alleviation layer (13) that surrounds an active region on the surface of a semiconductor substrate (11); an insulating film (19) that covers the electrical field alleviation layer; a first electrode (15) which is disposed on top of the active region; a plurality of metal layers (31-35) formed on top of the insulating film at the electrical field alleviation layer formation position; a second electrode (16) that surrounds the plurality of metal layers; and a semi-insulating film (23) disposed on top of the insulating film stretching from the first electrode to the second electrode. The space charge amount of impurities in the electrical field alleviation layer decreases with distance from the active region, and the metal layer width (W)/the distance (D) between outer edges of metal layers decreases with distance from the first electrode.
Description
本技術は、半導体装置に関し、より詳細には、高耐圧を有するパワーエレクトロニクス用半導体装置として好適な半導体装置に関する。
The present technology relates to a semiconductor device, and more particularly to a semiconductor device suitable as a power electronics semiconductor device having a high breakdown voltage.
パワーエレクトロニクスに用いられる半導体装置（以下「パワー半導体デバイス」と記載する場合がある）、特に耐圧が１００ボルト以上の半導体装置としては、ダイオード、金属－酸化膜－半導体電界効果型トランジスタ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ：ＭＯＳＦＥＴ）、絶縁ゲートバイポーラトランジスタ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ：ＩＧＢＴ）が挙げられる。これらの半導体装置には、耐圧を保持するための終端構造が設けられている。
Semiconductor devices used in power electronics (hereinafter sometimes referred to as “power semiconductor devices”), particularly semiconductor devices having a withstand voltage of 100 volts or more include diodes, metal-oxide-semiconductor field-effect transistors (Metal-Oxides). -Semiconductor field effect transistor (MOSFET), insulated gate bipolar transistor (Insulated Gate Bipolar Transistor: IGBT). These semiconductor devices are provided with a termination structure for maintaining a withstand voltage.
例えば、半導体基板の厚み方向一方側の表面（以下「基板表面」と記載する場合がある）に対して垂直に電流を流す半導体装置（以下「縦型デバイス」と記載する場合がある）では、能動素子として機能する領域（以下「活性領域」と記載する場合がある）を取り囲んで終端構造が設けられている。
For example, in a semiconductor device (hereinafter sometimes referred to as “vertical device”) that allows current to flow perpendicularly to the surface on one side of the thickness direction of the semiconductor substrate (hereinafter sometimes referred to as “substrate surface”), A termination structure is provided so as to surround a region functioning as an active element (hereinafter sometimes referred to as “active region”).
終端構造の機能は、活性領域と半導体装置の端部との間の基板表面に発生する高電圧を保持するものである。半導体装置の高耐圧性は、終端構造を設けることによって初めて実現される。
The function of the termination structure is to maintain a high voltage generated on the substrate surface between the active region and the end of the semiconductor device. The high breakdown voltage of the semiconductor device is realized only by providing a termination structure.
例えば、低濃度Ｎ型半導体基板と高濃度Ｐ型不純物層とによって構成されるＰＮ接合ダイオード（以下「ＰＩＮダイオード」と記載する場合がある）の場合、逆方向バイアス時において、空乏層はそのほとんどが低濃度Ｎ型半導体基板に広がっている。そして、この空乏層によって高電圧が保持される。しかし耐圧は、高濃度Ｐ型不純物層の端部、具体的には高濃度Ｐ型不純物層の外縁部における電界集中によって制限される。
For example, in the case of a PN junction diode composed of a low concentration N-type semiconductor substrate and a high concentration P-type impurity layer (hereinafter sometimes referred to as “PIN diode”), most of the depletion layer is in reverse bias. Has spread to the low-concentration N-type semiconductor substrate. A high voltage is held by this depletion layer. However, the breakdown voltage is limited by the electric field concentration at the end of the high concentration P-type impurity layer, specifically, at the outer edge of the high concentration P-type impurity layer.
そこで、高濃度Ｐ型不純物層の端部に隣接させて低濃度Ｐ型不純物層を形成すると、空乏層が低濃度Ｎ型半導体基板と低濃度Ｐ型不純物層との両方に広がる。このようにして、高濃度Ｐ型不純物層の端部の電界が緩和され、半導体装置の耐圧が高められる。
Therefore, when the low-concentration P-type impurity layer is formed adjacent to the end portion of the high-concentration P-type impurity layer, the depletion layer extends to both the low-concentration N-type semiconductor substrate and the low-concentration P-type impurity layer. In this way, the electric field at the end of the high concentration P-type impurity layer is relaxed, and the breakdown voltage of the semiconductor device is increased.
この低濃度Ｐ型不純物層は、リサーフ（Ｒｅｄｕｃｅｄ Ｓｕｒｆａｃｅ Ｆｉｅｌｄ：ＲＥＳＵＲＦ）層又はＪＴＥ（Ｊｕｎｃｔｉｏｎ Ｔｅｒｍｉｎａｔｉｏｎ Ｅｘｔｅｎｓｉｏｎ）層と呼称される。また、このような終端構造は、リサーフ構造と呼称される。
The low-concentration P-type impurity layer is referred to as a RESURF (Reduced Surface Field: RESURF) layer or a JTE (Junction Termination Extension) layer. Such a termination structure is called a RESURF structure.
リサーフ構造では、リサーフ層にも空乏層が広がる。高耐圧性を得るためには、所望の電圧でリサーフ層が最表面までほぼ完全に空乏化することが望ましい。その条件は、リサーフ層の注入量（正確には、リサーフ層に含まれるアクセプタイオン（空間電荷）の面密度）で規定される。
In the RESURF structure, a depletion layer also spreads in the RESURF layer. In order to obtain a high breakdown voltage, it is desirable that the RESURF layer is almost completely depleted to the outermost surface at a desired voltage. The condition is defined by the injection amount of the RESURF layer (more precisely, the surface density of acceptor ions (space charge) contained in the RESURF layer).
リサーフ層全体の注入量が単一である場合、リサーフ層の最適な注入量は、半導体基板の不純物濃度に依存せず、半導体基板を構成する半導体材料で決まる。例えば、シリコン（Ｓｉ）では、リサーフ層の最適な注入量は、約１×１０１２ｃｍ－２である。ポリタイプ４Ｈの炭化珪素（ＳｉＣ）では、リサーフ層の最適な注入量は、約１×１０１３ｃｍ－２である。これらリサーフ層の最適な注入量の値は、注入された不純物の活性化率が１００％である場合の値である。これらリサーフ層の最適な注入量の値は、リサーフ条件と呼ばれる。
When the injection amount of the entire RESURF layer is single, the optimal injection amount of the RESURF layer does not depend on the impurity concentration of the semiconductor substrate and is determined by the semiconductor material constituting the semiconductor substrate. For example, in silicon (Si), the optimum implantation amount of the RESURF layer is about 1 × 10 12 cm −2 . In polytype 4H silicon carbide (SiC), the optimum injection amount of the RESURF layer is about 1 × 10 13 cm −2 . The optimum implantation amount values of these RESURF layers are values when the activation rate of the implanted impurities is 100%. These optimum values for the injection amount of the RESURF layer are called RESURF conditions.
リサーフ構造は、Ｐ型とＮ型との両方に空乏層を広げるという特徴により、一般的な終端構造であるフィールドリミッティングリング（Ｆｉｅｌｄ Ｌｉｍｉｔｉｎｇ Ｒｉｎｇ；略称：ＦＬＲ）構造に対して、およそ半分の終端構造の幅で同等の耐圧を得ることができる。
The RESURF structure is characterized by the fact that the depletion layer extends to both P-type and N-type, so that the termination is about half of the field limiting ring (Field Limiting Ring: FLR) structure, which is a general termination structure. An equivalent breakdown voltage can be obtained with the width of the structure.
ただし、リサーフ構造には次の問題がある。リサーフ構造では、高耐圧性を得るために、リサーフ層の外縁部にも電界が集中してしまう。その結果、耐圧がリサーフ層の外縁部でのアバランシェ降伏によって制限されたり、そのアバランシェ降伏の短絡電流による熱破壊及びフラッシオーバが生じたりする。
However, the RESURF structure has the following problems. In the RESURF structure, the electric field is concentrated on the outer edge portion of the RESURF layer in order to obtain a high pressure resistance. As a result, the breakdown voltage is limited by avalanche breakdown at the outer edge of the RESURF layer, or thermal breakdown and flashover due to a short-circuit current of the avalanche breakdown may occur.
この問題は、例えば、リサーフ層の注入量を、半導体基板の外側（半導体装置の端部の方向）に向かうにしたがって漸減させることによって回避される（例えば、非特許文献１及び特許文献１参照）。このように、リサーフ層の注入量が漸減する終端構造にすることによって、電界集中点が無数の箇所に分散され、半導体内部の最大電界が大幅に低減される。このようなリサーフ層（低濃度Ｐ型不純物層）は傾斜ドーピング層、又は、ＶＬＤ（Ｖａｒｉａｔｉｏｎ ｏｆ Ｌａｔｅｒａｌ Ｄｏｐｉｎｇ）層と呼ばれ、このような終端構造は、ＶＬＤ構造と呼称される。
This problem can be avoided, for example, by gradually reducing the amount of injection of the RESURF layer toward the outside of the semiconductor substrate (in the direction of the end of the semiconductor device) (see, for example, Non-Patent Document 1 and Patent Document 1). . In this way, by using a termination structure in which the injection amount of the RESURF layer is gradually reduced, the electric field concentration points are dispersed in countless places, and the maximum electric field inside the semiconductor is greatly reduced. Such a RESURF layer (low-concentration P-type impurity layer) is called a graded doping layer or a VLD (Variation of Lateral Doping) layer, and such a termination structure is called a VLD structure.
特に、３３００Ｖ以上の耐圧を持つ半導体装置を、単一の注入量の単純なリサーフ構造で実現することは困難であり、ＶＬＤ構造のように、低濃度Ｐ型不純物層の注入量、換言すれば、空間電荷量を半導体装置の外側に向かって漸減させた構造が必要になる。つまり、３３００Ｖ以上の耐圧で終端構造の幅の小さい小面積な半導体装置を得るには、このような終端構造が必要である。
In particular, it is difficult to realize a semiconductor device having a withstand voltage of 3300 V or more with a simple resurf structure having a single implantation amount. In other words, the implantation amount of a low-concentration P-type impurity layer, in other words, a VLD structure. A structure in which the amount of space charge is gradually reduced toward the outside of the semiconductor device is required. That is, in order to obtain a small area semiconductor device with a breakdown voltage of 3300 V or more and a small width of the termination structure, such a termination structure is necessary.
ところで、パワー半導体デバイスでは、耐圧の安定化を目的として、終端構造表面を覆うパッシベーション膜の１層に、半絶縁性ポリシリコン（Ｓｅｍｉ－Ｉｎｓｕｌａｔｉｎｇ ＰＯｌｙｃｒｙｓｔａｌｌｉｎｅ Ｓｉｌｉｃｏｎ；略称：ＳＩＰＯＳ）膜又は半絶縁性窒化シリコン（Ｓｅｍｉ－ｉｎｓｕｌａｔｉｎｇ Ｓｉｌｉｃｏｎ Ｎｉｔｒｉｄｅ；略称：ＳｉｎＳｉＮ）膜といった半絶縁膜（高抵抗膜）がしばしば用いられる（例えば、特許文献２参照）。
By the way, in a power semiconductor device, a semi-insulating polysilicon (Semi-Insulating POlycrystalline Silicon; abbreviated name: SIPOS) film or semi-insulating silicon nitride is formed on one layer of a passivation film covering the surface of the termination structure for the purpose of stabilizing the breakdown voltage. A semi-insulating film (high resistance film) such as a (Semi-insulating Silicon Nitride; abbreviation: SinSiN) film is often used (for example, see Patent Document 2).
半絶縁膜は、活性領域と半導体装置の端部との間の電圧を抵抗分圧し、酸化シリコン膜などの絶縁膜を介して基板表面と容量結合することで、連続的な電位を持つ抵抗性フィールドプレートとして機能する。通常、半絶縁膜の抵抗は、半絶縁膜に流れる電流が基板内部を流れるリーク電流よりも低くなるように設定され、シート抵抗換算で少なくとも１００ＭΩ／□以上である。
The semi-insulating film is a resistive element having a continuous potential by dividing the voltage between the active region and the edge of the semiconductor device by resistance and capacitively coupling the substrate surface via an insulating film such as a silicon oxide film. Functions as a field plate. Usually, the resistance of the semi-insulating film is set so that the current flowing through the semi-insulating film is lower than the leak current flowing inside the substrate, and is at least 100 MΩ / □ or more in terms of sheet resistance.
半絶縁膜（正確に言えば、半絶縁膜／絶縁膜／基板表面の容量）は、半絶縁膜の抵抗Ｒと絶縁膜の静電容量Ｃとで決まる時定数ＲＣ程度の時間で充電される。半絶縁膜の充電が完了すると、抵抗性フィールドプレートの効果により基板表面のキャリア分布が変調されるだけでなく、半導体装置外部からの電界が遮蔽される。
The semi-insulating film (to be precise, the semi-insulating film / insulating film / substrate surface capacity) is charged in a time of about the time constant RC determined by the resistance R of the semi-insulating film and the capacitance C of the insulating film. . When the charging of the semi-insulating film is completed, not only the carrier distribution on the substrate surface is modulated by the effect of the resistive field plate, but also the electric field from the outside of the semiconductor device is shielded.
例えば、パワー半導体モジュールを動作させるとき、パワー半導体モジュールの封止樹脂は、パワー半導体モジュールを構成する半導体装置（パワー半導体デバイス）又は電気回路からの電界に晒される。このとき、封止樹脂が晒される電界の履歴は、ベクトル量の時間平均で０にならない。その結果、封止樹脂に含まれる可動イオンが電界により移動し、封止樹脂内で可動イオンが偏って分布する。すると、可動イオンによる電界が発生し、半導体装置に影響を及ぼす。
For example, when the power semiconductor module is operated, the sealing resin of the power semiconductor module is exposed to an electric field from a semiconductor device (power semiconductor device) or an electric circuit constituting the power semiconductor module. At this time, the history of the electric field to which the sealing resin is exposed does not become zero in terms of vector time. As a result, the mobile ions contained in the sealing resin move due to the electric field, and the mobile ions are unevenly distributed in the sealing resin. Then, an electric field due to movable ions is generated, which affects the semiconductor device.
半導体装置の活性領域では固定電位の表面電極により外部からの電界は遮蔽されるが、終端構造の大部分には固定電位の表面電極が存在しない。可動イオンからの電界により終端構造の耐圧が大幅に低下すれば、それは半導体装置の耐圧が大幅に低下することを意味する。上記のような状況を模擬する試験として長時間の高温逆バイアス試験があり、パワー半導体モジュール又は半導体装置の信頼性評価に用いられている。
In the active region of the semiconductor device, the electric field from the outside is shielded by the fixed potential surface electrode, but the fixed potential surface electrode does not exist in most of the termination structure. If the breakdown voltage of the termination structure is significantly reduced by the electric field from the movable ions, it means that the breakdown voltage of the semiconductor device is greatly reduced. As a test for simulating the above situation, there is a long-time high temperature reverse bias test, which is used for reliability evaluation of a power semiconductor module or a semiconductor device.
つまり、半絶縁膜によって、終端構造に影響を及ぼす半導体装置外部からの電界を遮蔽すれば、半導体装置（パワー半導体デバイス）の信頼性を高めることができる。
That is, if the electric field from the outside of the semiconductor device that affects the termination structure is shielded by the semi-insulating film, the reliability of the semiconductor device (power semiconductor device) can be improved.
以上に述べたように、半絶縁膜はパワー半導体デバイスの信頼性を高める上で重要な役割を果たす。
As described above, the semi-insulating film plays an important role in improving the reliability of the power semiconductor device.
しかし、半絶縁膜を、低濃度Ｐ型不純物層の空間電荷量を半導体装置の外側に向かって漸減させた終端構造に適用する際の適切な形態は、確立されていない。
However, an appropriate form for applying the semi-insulating film to the termination structure in which the space charge amount of the low-concentration P-type impurity layer is gradually decreased toward the outside of the semiconductor device has not been established.
本技術は、上記のような問題を解決するためになされたものであり、低濃度Ｐ型不純物層の空間電荷量を半導体装置の外側に向かって漸減させた終端構造において、適切な形態の半絶縁膜を設け、小面積、高耐圧性及び高信頼性を鼎立した半導体装置を提供することを目的とする。
The present technology has been made to solve the above-described problems. In the termination structure in which the space charge amount of the low-concentration P-type impurity layer is gradually decreased toward the outside of the semiconductor device, a half-shape in an appropriate form is provided. An object is to provide a semiconductor device provided with an insulating film and having a small area, high withstand voltage, and high reliability.
本技術の一態様に関する半導体装置は、第１導電型の半導体基板と、前記半導体基板表面において部分的に形成された活性領域と、前記半導体基板表面において、前記活性領域に接触し、かつ、前記活性領域を囲んで形成された第２導電型の不純物を含有する電界緩和層と、前記活性領域の一部及び前記電界緩和層を覆って形成された絶縁膜と、前記絶縁膜上の一部及び前記活性領域上に跨がって形成された第１電極と、前記電界緩和層が形成された位置の少なくとも一部に対応する前記絶縁膜上の位置において形成され、かつ、浮遊電位を有する複数の金属層とを備え、複数の前記金属層が、前記第１電極から離れる方向において互いに離間し、かつ、それぞれが前記第１電極を囲んで形成され、前記絶縁膜上及び前記半導体基板上に跨がって形成され、かつ、複数の前記金属層を囲んで配置された第２電極と、前記第１電極から前記第２電極に亘る前記絶縁膜上に形成された半絶縁膜とを備え、前記電界緩和層が、前記活性領域から離れる方向に延びて形成され、かつ、含有する第２導電型の不純物の空間電荷量が前記活性領域から離れるにつれて減少し、各前記金属層の前記第１電極から離れる方向の幅をＷ、各前記金属層の前記第２電極に近い側の端部である外縁端部と、前記第１電極に近づく方向において当該金属層と隣り合って配置された前記第１電極又は他の前記金属層の前記外縁端部との間の距離をＤとした場合、各前記金属層に関するＷ／Ｄが、前記第１電極から離れるにつれて小さくなる。
A semiconductor device according to an aspect of the present technology includes a first conductivity type semiconductor substrate, an active region partially formed on a surface of the semiconductor substrate, a surface of the semiconductor substrate in contact with the active region, and An electric field relaxation layer containing an impurity of a second conductivity type formed to surround the active region; an insulating film formed so as to cover part of the active region and the electric field relaxation layer; and a part on the insulating film And a first electrode formed over the active region and a position on the insulating film corresponding to at least a part of the position where the electric field relaxation layer is formed, and has a floating potential. A plurality of metal layers, the plurality of metal layers being spaced apart from each other in a direction away from the first electrode, and surrounding each of the first electrodes, and on the insulating film and the semiconductor substrate Straddling A second electrode disposed around the plurality of metal layers, and a semi-insulating film formed on the insulating film extending from the first electrode to the second electrode, An electric field relaxation layer is formed extending in a direction away from the active region, and a space charge amount of the second conductivity type impurity contained decreases as the distance from the active region decreases, and the first electrode of each metal layer The width in the direction away from the outer edge of each of the metal layers, the outer edge being the end closer to the second electrode, and the first adjacent to the metal layer in the direction approaching the first electrode. Assuming that the distance between one electrode or the outer edge of the other metal layer is D, the W / D for each metal layer decreases as the distance from the first electrode increases.
本技術の上記態様によれば、半絶縁膜を複数の金属層によって短絡することにより、充電された後の半絶縁膜による半導体基板表面における電位分布が、電界緩和層による半導体基板表面における電位分布に近づく。その結果、半絶縁膜の充電前後で、半導体基板内部の複数の電界集中点のバランスが保たれ、小面積、高耐圧性及び高信頼性を鼎立した半導体装置を実現することができる。
According to the above aspect of the present technology, by short-circuiting the semi-insulating film with a plurality of metal layers, the potential distribution on the semiconductor substrate surface due to the semi-insulating film after being charged becomes the potential distribution on the semiconductor substrate surface due to the electric field relaxation layer. Get closer to. As a result, a balance between a plurality of electric field concentration points inside the semiconductor substrate is maintained before and after the semi-insulating film is charged, and a semiconductor device with a small area, high withstand voltage, and high reliability can be realized.
本技術の目的、特徴、局面及び利点は、以下の詳細な説明と添付図面とによって、より明白となる。
The purpose, features, aspects and advantages of the present technology will become more apparent from the following detailed description and the accompanying drawings.
以下、添付の図面を参照しながら実施形態について説明する。
Hereinafter, embodiments will be described with reference to the accompanying drawings.
＜第１実施形態＞
＜構成＞
図１は、本実施形態に関する半導体装置１の構成を示す平面図である。半導体装置１は、活性領域の形状がシンプルな、縦型のＰＩＮダイオードである。図２は、図１の切断面線Ｉ－Ｉから見た終端構造を拡大して示す模式断面図である。 <First Embodiment>
<Configuration>
FIG. 1 is a plan view showing a configuration of asemiconductor device 1 according to the present embodiment. The semiconductor device 1 is a vertical PIN diode having a simple active region shape. FIG. 2 is a schematic cross-sectional view showing, in an enlarged manner, the termination structure seen from the section line II in FIG.
＜構成＞
図１は、本実施形態に関する半導体装置１の構成を示す平面図である。半導体装置１は、活性領域の形状がシンプルな、縦型のＰＩＮダイオードである。図２は、図１の切断面線Ｉ－Ｉから見た終端構造を拡大して示す模式断面図である。 <First Embodiment>
<Configuration>
FIG. 1 is a plan view showing a configuration of a
図１及び図２に示されるように、半導体装置１は、半導体基板１１と、ベース層１２（活性領域）と、電界緩和層１３と、ストッパ層１４と、アノード電極１５と、ストッパ電極１６と、カソード層１７と、カソード電極１８と、第１絶縁膜１９と、アノードフィールドプレート２０と、ストッパフィールドプレート２１と、浮遊電位金属配線群２２と、半絶縁膜２３（高抵抗膜）と、第２絶縁膜２４とを備える。
As shown in FIGS. 1 and 2, the semiconductor device 1 includes a semiconductor substrate 11, a base layer 12 (active region), an electric field relaxation layer 13, a stopper layer 14, an anode electrode 15, and a stopper electrode 16. The cathode layer 17, the cathode electrode 18, the first insulating film 19, the anode field plate 20, the stopper field plate 21, the floating potential metal wiring group 22, the semi-insulating film 23 (high resistance film), the first 2 insulating film 24.
半導体基板１１、ストッパ層１４及びカソード層１７は、Ｎ型の導電性を有する。ベース層１２（活性領域）及び電界緩和層１３は、Ｐ型の導電性を有する。本実施形態では、Ｎ型は第１導電型に相当し、Ｐ型は第２導電型に相当する。
The semiconductor substrate 11, the stopper layer 14, and the cathode layer 17 have N-type conductivity. The base layer 12 (active region) and the electric field relaxation layer 13 have P-type conductivity. In this embodiment, the N type corresponds to the first conductivity type, and the P type corresponds to the second conductivity type.
半導体基板１１は、Ｎ型の半導体基板である。半導体基板１１は、比較的低い濃度でＮ型不純物を含有する。以下の説明では、Ｎ型不純物が比較的低い濃度であることを「Ｎ－」と記載する場合がある。図１は、半導体装置１を半導体基板１１の厚み方向一方側から見た平面図に相当する。半導体基板１１は、厚み方向一方側から見て、矩形状、具体的には正方形状である。
The semiconductor substrate 11 is an N-type semiconductor substrate. The semiconductor substrate 11 contains N-type impurities at a relatively low concentration. In the following description, the N-type impurity having a relatively low concentration may be described as “N−”. FIG. 1 corresponds to a plan view of the semiconductor device 1 viewed from one side in the thickness direction of the semiconductor substrate 11. The semiconductor substrate 11 has a rectangular shape, specifically, a square shape when viewed from one side in the thickness direction.
ベース層１２は、半導体装置１の活性領域に相当する。ベース層１２は、半導体基板１１の厚み方向一方側の表面部（半導体基板１１表面）内の部分的領域において、半導体基板１１の最外縁から離隔して形成される。具体的には、ベース層１２は、半導体基板１１の厚み方向一方側の表面部の中央部に形成される。ベース層１２は、半導体基板１１の厚み方向一方側から見て、略正方形状、具体的には四隅部が９０°の円弧形の曲線で構成される正方形状に形成される。ベース層１２は、比較的高い濃度でＰ型不純物を含有するＰ型不純物層で構成される。
The base layer 12 corresponds to an active region of the semiconductor device 1. The base layer 12 is formed apart from the outermost edge of the semiconductor substrate 11 in a partial region in the surface portion (the surface of the semiconductor substrate 11) on one side in the thickness direction of the semiconductor substrate 11. Specifically, the base layer 12 is formed at the center of the surface portion on one side in the thickness direction of the semiconductor substrate 11. The base layer 12 is formed in a substantially square shape when viewed from one side in the thickness direction of the semiconductor substrate 11, specifically, a square shape constituted by arcuate curves having four corners of 90 °. The base layer 12 is composed of a P-type impurity layer containing P-type impurities at a relatively high concentration.
電界緩和層１３は、半導体基板１１の厚み方向一方側の表面部内に、ベース層１２の最外縁から半導体基板１１の最外縁に向けて形成される。本実施形態における電界緩和層１３は、半導体基板１１の厚み方向一方側から見て、ベース層１２を囲繞するように環状に形成される。以下の説明では、電界緩和層１３の径方向を、単に「径方向」といい、電界緩和層１３の周方向を、単に「周方向」と記載する場合がある。
The electric field relaxation layer 13 is formed in the surface portion on one side in the thickness direction of the semiconductor substrate 11 from the outermost edge of the base layer 12 toward the outermost edge of the semiconductor substrate 11. The electric field relaxation layer 13 in the present embodiment is formed in an annular shape so as to surround the base layer 12 when viewed from one side in the thickness direction of the semiconductor substrate 11. In the following description, the radial direction of the electric field relaxation layer 13 may be simply referred to as “radial direction”, and the circumferential direction of the electric field relaxation layer 13 may be simply referred to as “circumferential direction”.
電界緩和層１３は、径方向の内側から外側に向かうにしたがって注入量が漸減するＰ型不純物層である。言い換えれば、電界緩和層１３は傾斜ドーピングされたＰ型不純物層であり、ＶＬＤ層と呼称されるものである（以下、電界緩和層１３をＶＬＤ層１３と呼称することがある）。
The electric field relaxation layer 13 is a P-type impurity layer in which the implantation amount gradually decreases from the inner side to the outer side in the radial direction. In other words, the electric field relaxation layer 13 is a gradient-doped P-type impurity layer and is referred to as a VLD layer (hereinafter, the electric field relaxation layer 13 may be referred to as a VLD layer 13).
ＶＬＤ層１３は外側に向かって漸減する注入量を有するが、熱処理はＶＬＤ層１３の全体で一括して実施される。そのため、ＶＬＤ層１３のＰ型不純物濃度は外側に向かって漸減し、ＶＬＤ層１３のＰＮ接合深さは外側に向かって漸減する。ＶＬＤ層１３で同じ注入量を持つ領域は半導体基板１１の厚み方向一方側から見て、略正方形の環状、具体的には四隅部が９０°円弧形の曲線で構成される正方形の環状に形成される。ＶＬＤ層１３の最内縁はベース層１２の最外縁に接する。
The VLD layer 13 has an injection amount that gradually decreases toward the outside, but the heat treatment is performed collectively for the entire VLD layer 13. Therefore, the P-type impurity concentration of the VLD layer 13 gradually decreases toward the outside, and the PN junction depth of the VLD layer 13 decreases gradually toward the outside. The region having the same implantation amount in the VLD layer 13 is a substantially square ring, specifically, a square ring formed of 90 ° arc-shaped curves at the four corners when viewed from one side in the thickness direction of the semiconductor substrate 11. It is formed. The innermost edge of the VLD layer 13 is in contact with the outermost edge of the base layer 12.
ＶＬＤ層１３の注入量は、内縁部においてリサーフ条件の１．２倍以上２倍以下程度、外縁部においてリサーフ条件の０．１５倍以上０．５倍以下程度であり、内縁部と外縁部との間においては径方向距離に対してシームレスかつ線形に漸減、あるいは、段階的かつ線形に漸減する。外縁部の注入量は耐圧が高いほど下げる必要がある。ＶＬＤ層１３の注入量をこのようにすることで、ＶＬＤ層１３の幅を半導体基板１１の厚み（正確には、Ｎ－領域であるドリフト層の厚み）の２倍以下にすることができる。
The injection amount of the VLD layer 13 is about 1.2 to 2 times the resurf condition at the inner edge, and about 0.15 to 0.5 times the resurf condition at the outer edge, and the inner edge and the outer edge In between, it decreases gradually and linearly with respect to the radial distance, or gradually and linearly decreases. It is necessary to lower the injection amount of the outer edge portion as the withstand pressure is higher. By setting the injection amount of the VLD layer 13 in this way, the width of the VLD layer 13 can be made not more than twice the thickness of the semiconductor substrate 11 (more precisely, the thickness of the drift layer which is the N− region).
ストッパ層１４は、半導体基板１１の厚み方向一方側の表面部内のうち、半導体基板１１の外縁部に、電界緩和層１３から離隔して形成される。ストッパ層１４は、比較的高い濃度でＮ型不純物を含有するＮ型不純物層で構成される。
The stopper layer 14 is formed on the outer edge portion of the semiconductor substrate 11 in the surface portion on one side in the thickness direction of the semiconductor substrate 11 so as to be separated from the electric field relaxation layer 13. The stopper layer 14 is composed of an N-type impurity layer containing N-type impurities at a relatively high concentration.
アノード電極１５は、ベース層１２の厚み方向一方側の表面部上に設けられる。アノード電極１５は、ベース層１２の厚み方向一方側の表面部の一部分に接して形成される。アノード電極１５は、半導体基板１１の厚み方向一方側から見て、ベース層１２よりも少し大きい略正方形状、具体的には、四隅部が９０°円弧形の曲線で構成される正方形状である。
The anode electrode 15 is provided on the surface portion on one side in the thickness direction of the base layer 12. The anode electrode 15 is formed in contact with a part of the surface portion on one side in the thickness direction of the base layer 12. The anode electrode 15 has a substantially square shape slightly larger than the base layer 12 when viewed from one side in the thickness direction of the semiconductor substrate 11, specifically, a square shape in which the four corners are 90 ° arc-shaped curves. is there.
ストッパ電極１６は、ストッパ層１４の厚み方向一方側の表面部上に設けられる。ストッパ電極１６は、ストッパ層１４の厚み方向一方側の表面部の一部分に接して形成される。ストッパ電極１６の最内縁は、半導体基板１１の厚み方向一方側から見て、電界緩和層１３の最外縁とストッパ層１４の最内縁との例えば中間に位置する。
The stopper electrode 16 is provided on the surface portion on one side in the thickness direction of the stopper layer 14. The stopper electrode 16 is formed in contact with a part of the surface portion on one side in the thickness direction of the stopper layer 14. The innermost edge of the stopper electrode 16 is located, for example, in the middle between the outermost edge of the electric field relaxation layer 13 and the innermost edge of the stopper layer 14 when viewed from one side in the thickness direction of the semiconductor substrate 11.
カソード層１７は、ベース層１２が形成される側とは反対側の半導体基板１１の表面部内、すなわち半導体基板１１の厚み方向他方側の表面部（以下「基板裏面」と記載する場合がある）内に形成される。カソード層１７は、基板裏面全体にわたって形成される。カソード層１７は、比較的高い濃度でＮ型不純物を含有するＮ型不純物層で構成される。
The cathode layer 17 is in the surface portion of the semiconductor substrate 11 opposite to the side on which the base layer 12 is formed, that is, the surface portion on the other side in the thickness direction of the semiconductor substrate 11 (hereinafter sometimes referred to as “substrate back surface”). Formed inside. The cathode layer 17 is formed over the entire back surface of the substrate. The cathode layer 17 is composed of an N-type impurity layer containing N-type impurities at a relatively high concentration.
カソード電極１８は、カソード層１７の厚み方向他方側の表面部上に設けられる。カソード電極１８は、カソード層１７の厚み方向他方側の表面部全体にわたって設けられる。
The cathode electrode 18 is provided on the surface portion on the other side in the thickness direction of the cathode layer 17. The cathode electrode 18 is provided over the entire surface portion on the other side in the thickness direction of the cathode layer 17.
第１絶縁膜１９は、半導体基板１１の厚み方向一方側の表面部上に設けられる。具体的には、第１絶縁膜１９は、ベース層１２の表面部上の一部分と、電界緩和層１３の最内縁からストッパ層１４の最内縁までの表面部上と、ストッパ層１４の表面部上の一部分に形成される。
The first insulating film 19 is provided on the surface portion on one side in the thickness direction of the semiconductor substrate 11. Specifically, the first insulating film 19 includes a part on the surface portion of the base layer 12, a surface portion from the innermost edge of the electric field relaxation layer 13 to the innermost edge of the stopper layer 14, and the surface portion of the stopper layer 14. Formed on top part.
アノードフィールドプレート２０は、アノード電極１５のうち、半導体基板１１の厚み方向一方側から見て、ベース層１２から径方向外側に突き出て、電界緩和層１３の一部分に被った部分である。
The anode field plate 20 is a portion of the anode electrode 15 that protrudes radially outward from the base layer 12 as seen from one side in the thickness direction of the semiconductor substrate 11 and covers a part of the electric field relaxation layer 13.
ストッパフィールドプレート２１は、ストッパ電極１６のうち、半導体基板１１の厚み方向一方側から見て、ストッパ層１４から径方向内側に突き出た部分である。
The stopper field plate 21 is a portion of the stopper electrode 16 that protrudes radially inward from the stopper layer 14 when viewed from one side in the thickness direction of the semiconductor substrate 11.
浮遊電位金属配線群２２は、第１絶縁膜１９の厚み方向一方側の表面部上の、アノード電極１５の最外縁とストッパ電極１６の最内縁との間に配置された金属層群である。浮遊電位金属配線群２２は、アノード電極１５及びストッパ電極１６と同一の金属で形成される。
The floating potential metal wiring group 22 is a metal layer group disposed between the outermost edge of the anode electrode 15 and the innermost edge of the stopper electrode 16 on the surface portion on one side in the thickness direction of the first insulating film 19. The floating potential metal wiring group 22 is formed of the same metal as the anode electrode 15 and the stopper electrode 16.
浮遊電位金属配線群２２は、複数の金属層である金属配線３１、金属配線３２、金属配線３３、金属配線３４及び金属配線３５を備える。複数の金属配線３１～３５は、それぞれ、半導体基板１１の厚み方向一方側から見て環状に形成され、互いに間隔をあけて、径方向に並んで配置される。各金属配線３１～３５は、半導体基板１１の厚み方向一方側から見て、略正方形の環状、具体的には四隅部が９０°円弧形の曲線で構成される正方形の環状に形成される。アノード電極１５、金属配線３１～３５及びストッパ電極１６のうち、隣り合うもの同士の間隔は、アノード電極１５からストッパ電極１６に向かうにしたがって大きくなる。金属配線３１～３５の径方向の幅は、アノード電極１５側からストッパ電極１６側に向かうにしたがって小さくなる。
The floating potential metal wiring group 22 includes a metal wiring 31, a metal wiring 32, a metal wiring 33, a metal wiring 34 and a metal wiring 35 which are a plurality of metal layers. The plurality of metal wirings 31 to 35 are each formed in an annular shape when viewed from one side in the thickness direction of the semiconductor substrate 11, and are arranged side by side in the radial direction at intervals. Each of the metal wirings 31 to 35 is formed in a substantially square annular shape, specifically, a square annular shape having four corners formed by 90 ° arcuate curves when viewed from one side in the thickness direction of the semiconductor substrate 11. . Among the anode electrode 15, the metal wirings 31 to 35, and the stopper electrode 16, the distance between adjacent ones increases as the distance from the anode electrode 15 toward the stopper electrode 16 increases. The radial widths of the metal wirings 31 to 35 become smaller from the anode electrode 15 side toward the stopper electrode 16 side.
半絶縁膜２３は、アノード電極１５の外縁部からストッパ電極１６の最外縁までの、アノード電極１５、浮遊電位金属配線群２２、ストッパ電極１６、及び、それらの間にある第１絶縁膜１９の厚み方向一方側の表面部を覆うように設けられる。
The semi-insulating film 23 consists of the anode electrode 15, the floating potential metal wiring group 22, the stopper electrode 16, and the first insulating film 19 between them from the outer edge of the anode electrode 15 to the outermost edge of the stopper electrode 16. It is provided so as to cover the surface portion on one side in the thickness direction.
第２絶縁膜２４は、半絶縁膜２３の厚み方向一方側の表面部を覆うように設けられる。
The second insulating film 24 is provided so as to cover the surface portion on one side in the thickness direction of the semi-insulating film 23.
半導体基板１１の厚み方向一方側から見て、ベース層１２よりも外側の構造が、終端構造である。言い換えれば、終端構造は、電界緩和層１３、ストッパ層１４、第１絶縁膜１９、ストッパフィールドプレート２１を含むストッパ電極１６、アノードフィールドプレート２０、浮遊電位金属配線群２２、半絶縁膜２３、及び、第２絶縁膜２４を備える構造である。
The structure outside the base layer 12 when viewed from one side in the thickness direction of the semiconductor substrate 11 is a termination structure. In other words, the termination structure includes the electric field relaxation layer 13, the stopper layer 14, the first insulating film 19, the stopper electrode 16 including the stopper field plate 21, the anode field plate 20, the floating potential metal wiring group 22, the semi-insulating film 23, and In this structure, the second insulating film 24 is provided.
以上のような構成の半導体装置１において、基板裏面のカソード電極１８と、ベース層１２に接触するアノード電極１５との間にバイアス電圧が印加される。これによって、半導体装置１はＰＮ接合ダイオードとして機能する。逆方向バイアス時には、ストッパ層１４及びストッパ電極１６は、カソード電極１８とほぼ同電位になる。そのため、逆方向バイアス時には、アノード電極１５とストッパ電極１６との間にバイアス電圧と同じ電圧が発生する。
In the semiconductor device 1 configured as described above, a bias voltage is applied between the cathode electrode 18 on the back surface of the substrate and the anode electrode 15 in contact with the base layer 12. Thereby, the semiconductor device 1 functions as a PN junction diode. At the time of reverse bias, the stopper layer 14 and the stopper electrode 16 have substantially the same potential as the cathode electrode 18. Therefore, during reverse bias, the same voltage as the bias voltage is generated between the anode electrode 15 and the stopper electrode 16.
＜作用＞
以下では、本実施形態の作用について説明する。 <Action>
Below, the effect | action of this embodiment is demonstrated.
以下では、本実施形態の作用について説明する。 <Action>
Below, the effect | action of this embodiment is demonstrated.
まず、終端構造の径方向の電位分布を考える。先述の通り、ＶＬＤ層１３の注入量は、内縁部においてリサーフ条件の１．２倍以上２倍以下程度、外縁部においてリサーフ条件の０．２倍以上０．５倍以下程度である。耐圧に近い逆方向バイアスが印加されたときに不純物層の最表面まで空乏化する目安の注入量がリサーフ条件であるから、ＶＬＤ層１３の外側寄りの部分は耐圧以下の逆方向バイアスで最表面まで空乏化する。一方で、ＶＬＤ層１３の内側寄りの部分は逆方向バイアスが耐圧に至るまで最表面まで空乏化しない。その結果、半絶縁膜２３の作用を無視すると、耐圧近傍の逆方向バイアス時における、ベース層１２の最外縁からストッパ層１４の最内縁までの半導体基板１１の表面の電位は、アノード電位からカソード電位まで単調に増加するものの、下に凸の変化で推移する。
First, consider the radial potential distribution of the termination structure. As described above, the injection amount of the VLD layer 13 is about 1.2 to 2 times the resurf condition at the inner edge, and about 0.2 to 0.5 times the resurf condition at the outer edge. The resurf condition is a guide amount for depletion to the outermost surface of the impurity layer when a reverse bias close to the withstand voltage is applied. Therefore, the portion closer to the outside of the VLD layer 13 has the reverse bias below the withstand voltage and the outermost surface. Until depleted. On the other hand, the portion closer to the inside of the VLD layer 13 is not depleted to the outermost surface until the reverse bias reaches the withstand voltage. As a result, if the action of the semi-insulating film 23 is ignored, the potential of the surface of the semiconductor substrate 11 from the outermost edge of the base layer 12 to the innermost edge of the stopper layer 14 at the time of reverse bias near the withstand voltage is from the anode potential to the cathode. Although it increases monotonously to the potential, it changes with a downward change.
換言すれば、ベース層１２の最外縁からストッパ層１４の最内縁までの半導体基板１１の表面の電位は、アノード電位からカソード電位まで変化し、径方向距離に関する１階微分が正であり、径方向距離に関する２階微分が正であり、アノード電位からカソード電位まで線形に結んだ時の電位よりも低い値を取る。
In other words, the potential of the surface of the semiconductor substrate 11 from the outermost edge of the base layer 12 to the innermost edge of the stopper layer 14 changes from the anode potential to the cathode potential, and the first-order derivative with respect to the radial distance is positive. The second derivative with respect to the directional distance is positive and takes a value lower than the potential when linearly connected from the anode potential to the cathode potential.
次に、半絶縁膜２３の径方向の電位分布を考える。逆方向バイアス時には、アノード電極１５とストッパ電極１６との間に電圧が生じ、半絶縁膜２３に微小な電流が流れ、電圧降下（抵抗分圧）が生じる。ただし、ベース層１２の最外縁からストッパ層１４の最内縁までに対応する区間において、半絶縁膜２３はアノードフィールドプレート２０、ストッパフィールドプレート２１及び浮遊電位金属配線群２２によって短絡される。そのため、アノードフィールドプレート２０、ストッパフィールドプレート２１及び浮遊電位金属配線群２２のない部分だけで電圧降下が生じる。
Next, the radial potential distribution of the semi-insulating film 23 will be considered. At the time of reverse bias, a voltage is generated between the anode electrode 15 and the stopper electrode 16, a minute current flows through the semi-insulating film 23, and a voltage drop (resistance division) is generated. However, the semi-insulating film 23 is short-circuited by the anode field plate 20, the stopper field plate 21 and the floating potential metal wiring group 22 in a section corresponding to the outermost edge of the base layer 12 and the innermost edge of the stopper layer 14. For this reason, a voltage drop occurs only in a portion where the anode field plate 20, the stopper field plate 21 and the floating potential metal wiring group 22 are not present.
図３は、半絶縁膜２３の径方向の電位分布を示す図である。図３において、縦軸は電位を示し、横軸は径方向の距離を示す。グラフ２７（実線）は、グラフ２５（実線）をスムージングしたものである。
FIG. 3 is a diagram showing a radial potential distribution of the semi-insulating film 23. In FIG. 3, the vertical axis indicates the potential, and the horizontal axis indicates the radial distance. Graph 27 (solid line) is obtained by smoothing graph 25 (solid line).
図３におけるグラフ２５（実線）に示されるように、充電が完了した状態の半絶縁膜２３の電位は、径方向に部分平均化（スムージング）した状態で、アノード電位からカソード電位まで単調に増加し、かつ、下に凸の分布となる。ここで、浮遊電位金属配線群２２が存在しなければ、図３におけるグラフ２６（破線）に示されるように、充電が完了した状態の半絶縁膜２３の電位は線形的な分布となる。
As shown in the graph 25 (solid line) in FIG. 3, the potential of the semi-insulating film 23 in a state where charging is completed monotonically increases from the anode potential to the cathode potential in a state of partial averaging (smoothing) in the radial direction. However, the distribution is convex downward. Here, if the floating potential metal wiring group 22 does not exist, the potential of the semi-insulating film 23 in a state where the charging is completed has a linear distribution as shown by a graph 26 (broken line) in FIG.
換言すれば、グラフ２５で示される充電が完了した状態の半絶縁膜２３の電位は、アノード電位からカソード電位まで単調に増加し、グラフ２５をスムージングした状態（すなわち、グラフ２７）では、径方向距離に関する２階微分が正であり、グラフ２６に示されるアノード電位からカソード電位まで線形に結んだ時の電位よりも低い値を取る。
In other words, the potential of the semi-insulating film 23 in the state where the charging shown in the graph 25 is completed monotonously increases from the anode potential to the cathode potential, and in the state where the graph 25 is smoothed (that is, the graph 27), the radial direction The second derivative with respect to the distance is positive and takes a value lower than the potential when linearly connected from the anode potential to the cathode potential shown in the graph 26.
ここで、従来技術の従来知られていない課題を示す。
Here, problems that have not been known in the prior art are shown.
半導体基板１１の内部のキャリアの応答時間は、半絶縁膜２３の充電に必要な時間に比べて遥かに短い。そのため、逆方向バイアスを印加して間もない時点（初期状態）では、半導体基板１１の表面の電位は半絶縁膜２３の影響を受けない。しかし、半絶縁膜２３の充電に伴って、半導体基板１１は半絶縁膜２３に影響され始める。そして、半絶縁膜２３の充電が完了した時点（定常状態）では、半導体基板１１の表面の電位は半絶縁膜２３の電位に強制的に引き寄せられる。
The response time of carriers inside the semiconductor substrate 11 is much shorter than the time required for charging the semi-insulating film 23. For this reason, the potential on the surface of the semiconductor substrate 11 is not affected by the semi-insulating film 23 at a time (initial state) shortly after the reverse bias is applied. However, as the semi-insulating film 23 is charged, the semiconductor substrate 11 begins to be affected by the semi-insulating film 23. When the charging of the semi-insulating film 23 is completed (steady state), the potential of the surface of the semiconductor substrate 11 is forcibly drawn to the potential of the semi-insulating film 23.
本実施形態で浮遊電位金属配線群２２が存在しない場合、換言すれば、従来技術の半絶縁膜２３を設けた場合、半絶縁膜２３の充電によって半絶縁膜２３が径方向に対して線形な電位分布を持つ（グラフ２６を参照）。すると、電界緩和層１３を含む半導体基板１１の表面の電位分布が（電界緩和層１３の不純物注入量を上記のようにしたことにより）初期状態で下に凸であっても、定常状態では強制的に線形に近づけられる。その結果、電界緩和層１３によって半導体基板１１の内部で適切に分散されていた電界集中点のバランスが崩れ、耐圧の低下となって現れることがある。
In the present embodiment, when the floating potential metal wiring group 22 does not exist, in other words, when the conventional semi-insulating film 23 is provided, the semi-insulating film 23 is linear with respect to the radial direction by charging the semi-insulating film 23. It has a potential distribution (see graph 26). Then, even if the potential distribution on the surface of the semiconductor substrate 11 including the electric field relaxation layer 13 is convex downward in the initial state (by making the impurity implantation amount of the electric field relaxation layer 13 as described above), it is forced in the steady state. To be linear. As a result, the balance of the electric field concentration points appropriately dispersed inside the semiconductor substrate 11 by the electric field relaxation layer 13 may be lost, and the breakdown voltage may appear.
これが、従来技術の従来知られていない課題である。
This is a problem that has not been known in the prior art.
しかし、本実施形態によれば、当該課題は解決される。つまり、半導体装置１のように、浮遊電位金属配線群２２を形成することによって、定常状態における半絶縁膜２３による電位分布を、初期状態における半導体基板１１の表面の電位分布に近づけておくことができる。そのため、半絶縁膜２３の充電によって半導体基板１１の表面の電位が半絶縁膜２３の電位に強制的に引き寄せられる場合でも、半絶縁膜２３の充電前後における半導体基板１１の表面の電位の変化は小さくなり、半導体基板１１の内部の電界集中点のバランスが崩れずに保たれる。よって、半導体装置１の経時的な耐圧低下を抑制、場合によっては、解消することができる。
However, according to this embodiment, the problem is solved. That is, by forming the floating potential metal wiring group 22 as in the semiconductor device 1, the potential distribution due to the semi-insulating film 23 in the steady state can be brought close to the potential distribution on the surface of the semiconductor substrate 11 in the initial state. it can. Therefore, even when the potential of the surface of the semiconductor substrate 11 is forcibly attracted to the potential of the semi-insulating film 23 by charging of the semi-insulating film 23, the change in the potential of the surface of the semiconductor substrate 11 before and after charging of the semi-insulating film 23 is Thus, the balance of the electric field concentration points inside the semiconductor substrate 11 is kept unchanged. Therefore, the withstand voltage drop over time of the semiconductor device 1 can be suppressed, and can be eliminated in some cases.
本実施形態で示された半導体装置１では、定常状態における半絶縁膜２３のスムージングされた電位分布が、初期状態における半導体基板１１の表面の電位分布と同じく径方向の距離に対して下に凸になっており、上記の効果を得ることができる。
In the semiconductor device 1 shown in the present embodiment, the smoothed potential distribution of the semi-insulating film 23 in the steady state protrudes downward with respect to the radial distance in the same manner as the potential distribution on the surface of the semiconductor substrate 11 in the initial state. The above effects can be obtained.
ただし、上記の効果を得るためには、浮遊電位金属配線群２２が電界緩和層１３の表面に接してはいけない。換言すれば、浮遊電位金属配線群２２と電界緩和層１３の表面とをコンタクトホールなどによって直接接続してはいけない。なぜなら、各金属配線３１～３５をコンタクトホールによって電界緩和層１３の表面に接続すると、各金属配線３１～３５の電位は、常時、コンタクトホールによって接続された電界緩和層１３の表面の電位と等しくなる。その結果、各金属配線３１～３５の電位は、それぞれが接続された電界緩和層１３の表面の初期状態の電位で固定される。
However, in order to obtain the above effect, the floating potential metal wiring group 22 should not be in contact with the surface of the electric field relaxation layer 13. In other words, the floating potential metal wiring group 22 and the surface of the electric field relaxation layer 13 should not be directly connected by a contact hole or the like. This is because when the metal wirings 31 to 35 are connected to the surface of the electric field relaxation layer 13 by contact holes, the potentials of the metal wirings 31 to 35 are always equal to the potential of the surface of the electric field relaxation layer 13 connected by the contact holes. Become. As a result, the potential of each of the metal wirings 31 to 35 is fixed at the initial potential on the surface of the electric field relaxation layer 13 to which each of the metal wirings 31 to 35 is connected.
すると、半絶縁膜２３の充電による耐圧の変動はほぼ解消されるが、浮遊電位金属配線群２２で短絡された半絶縁膜２３による抵抗性フィールドプレートの機能もほぼ失われる。具体的に言えば、半絶縁膜２３は、電界緩和層１３の表面の初期状態の電位で固定された各金属配線３１～３５の電位を、各金属配線３１～３５の間で線形に繋げるだけの機能しか供さなくなる。つまり、浮遊電位金属配線群２２で短絡された半絶縁膜２３が、全体としての抵抗性フィールドプレートの機能を持たなくなる。
Then, although the fluctuation of the breakdown voltage due to the charging of the semi-insulating film 23 is almost eliminated, the function of the resistive field plate by the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22 is almost lost. More specifically, the semi-insulating film 23 only connects the potentials of the metal wirings 31 to 35 fixed at the initial potential of the surface of the electric field relaxation layer 13 between the metal wirings 31 to 35 linearly. Only the function of will be provided. That is, the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22 does not have the function of the resistive field plate as a whole.
浮遊電位金属配線群２２で短絡された半絶縁膜２３が、全体としての抵抗性フィールドプレートの機能を持たなければ、浮遊電位金属配線群２２で短絡された半絶縁膜２３は半導体装置外部からの電界を遮蔽できない。なぜなら、半導体装置外部からの電界を遮蔽するには、定常状態において、浮遊電位金属配線群２２で短絡された半絶縁膜２３の電位が、電界緩和層１３を含む半導体基板１１とは独立に、決まる必要があるからである。
If the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22 does not have the function of a resistive field plate as a whole, the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22 is not supplied from the outside of the semiconductor device. The electric field cannot be shielded. This is because, in order to shield the electric field from the outside of the semiconductor device, in the steady state, the potential of the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22 is independent of the semiconductor substrate 11 including the electric field relaxation layer 13. It is necessary to be decided.
上記の理由から、浮遊電位金属配線群２２と電界緩和層１３の表面とをコンタクトホールなどによって直接接続した形態では、高い信頼性を得ることが困難になる。換言すれば、浮遊電位金属配線群２２と電界緩和層１３の表面とをコンタクトホールによって直接接続した形態では、小面積、高耐圧性は実現できても、高信頼性の実現が困難になる。
For the above reasons, it is difficult to obtain high reliability in the form in which the floating potential metal wiring group 22 and the surface of the electric field relaxation layer 13 are directly connected by a contact hole or the like. In other words, in the form in which the floating potential metal wiring group 22 and the surface of the electric field relaxation layer 13 are directly connected by the contact hole, it is difficult to realize high reliability even though a small area and high withstand voltage can be realized.
＜変形例＞
図４は、本実施形態の変形例に関する半導体装置２の終端構造を拡大して示す模式断面図である。 <Modification>
FIG. 4 is an enlarged schematic cross-sectional view showing the termination structure of thesemiconductor device 2 according to the modification of the present embodiment.
図４は、本実施形態の変形例に関する半導体装置２の終端構造を拡大して示す模式断面図である。 <Modification>
FIG. 4 is an enlarged schematic cross-sectional view showing the termination structure of the
この変形例においても、第１実施形態と同様に、半導体装置２をＰＩＮダイオードに適用した場合の構成について説明する。半導体装置２は、第１実施形態の半導体装置１と構成が類似しているので、同一の構成については同一の参照符号を付して、共通する説明を省略する。
In this modification as well, the configuration when the semiconductor device 2 is applied to a PIN diode will be described as in the first embodiment. Since the semiconductor device 2 is similar in configuration to the semiconductor device 1 of the first embodiment, the same configuration is denoted by the same reference numeral, and common description is omitted.
浮遊電位金属配線群４０は、複数の金属層である金属配線４１、金属配線４２、金属配線４３、金属配線４４及び金属配線４５を備える。複数の金属配線４１～４５は、それぞれ、半導体基板１１の厚み方向一方側から見て環状に形成され、互いに間隔をあけて径方向に並んで配置される。各金属配線４１～４５は、半導体基板１１の厚み方向一方側から見て、略正方形の環状、具体的には四隅部が９０°円弧形の曲線で構成される正方形の環状に形成される。アノード電極１５、金属配線４１～４５及びストッパ電極１６のうち、隣り合うもの同士の間隔は、アノード電極１５からストッパ電極１６に向かうにしたがって大きくなる。金属配線３１～３５の径方向の幅はアノード電極１５からの距離に関わらず同一である。このような構成でも、図５のように、定常状態における半絶縁膜２３の電位は、スムージングした状態で、下に凸の分布となる。
The floating potential metal wiring group 40 includes a metal wiring 41, a metal wiring 42, a metal wiring 43, a metal wiring 44, and a metal wiring 45, which are a plurality of metal layers. The plurality of metal wirings 41 to 45 are each formed in an annular shape when viewed from one side in the thickness direction of the semiconductor substrate 11, and are arranged side by side in the radial direction at intervals. Each of the metal wirings 41 to 45 is formed in a substantially square ring shape, specifically, a square ring shape having four corners formed by 90 ° arcuate curves as viewed from one side in the thickness direction of the semiconductor substrate 11. . Among the anode electrode 15, the metal wirings 41 to 45, and the stopper electrode 16, the distance between adjacent ones increases as the distance from the anode electrode 15 toward the stopper electrode 16 increases. The radial widths of the metal wirings 31 to 35 are the same regardless of the distance from the anode electrode 15. Even in such a configuration, as shown in FIG. 5, the potential of the semi-insulating film 23 in the steady state has a downward convex distribution in a smoothed state.
半導体装置１（若しくは半導体装置２）では、浮遊電位金属配線群２２（若しくは浮遊電位金属配線群４０）が含む金属配線３１～３５（若しくは金属配線４１～４５）の数は５個であるが、これは模式的に簡略化した構成である。実際は、耐圧又は第１絶縁膜の材料、第１絶縁膜の厚み及び半導体基板の材料に応じて、適切な金属配線の幅、間隔及び個数が存在する。
In the semiconductor device 1 (or the semiconductor device 2), the floating potential metal wiring group 22 (or the floating potential metal wiring group 40) includes five metal wirings 31 to 35 (or metal wirings 41 to 45). This is a simplified configuration. Actually, there are appropriate widths, intervals, and numbers of metal wirings depending on the breakdown voltage or the material of the first insulating film, the thickness of the first insulating film, and the material of the semiconductor substrate.
例えば、半導体装置２において、より高い耐圧に対応させる場合を考える。耐圧が高くするほど電界緩和層１３の幅を広くする必要がある。電界緩和層１３の幅を広くするとき、対応して設けられた金属配線４１～４５の幅と間隔とを広げるよりも、まずは金属配線の数を増やすことを検討すべきである。なぜなら、金属配線４１～４５の幅を広くしすぎると、金属配線４１～４５の端部の下にある第１絶縁膜１９及び半導体基板１１に強い電界が発生するからである。この電界が強すぎると、放電又は耐圧低下が発生することがある。したがって、金属配線４１～４５の端部の下に過度に強い電界が発生しない程度に金属配線４１～４５の幅は短くするべきである。
For example, let us consider a case where the semiconductor device 2 is adapted to a higher breakdown voltage. The higher the withstand voltage, the wider the electric field relaxation layer 13 needs to be. When the width of the electric field relaxation layer 13 is increased, it should be considered to increase the number of metal wirings first, rather than increasing the width and interval of the corresponding metal wirings 41 to 45. This is because if the width of the metal wirings 41 to 45 is too wide, a strong electric field is generated in the first insulating film 19 and the semiconductor substrate 11 below the ends of the metal wirings 41 to 45. If this electric field is too strong, discharge or breakdown voltage reduction may occur. Therefore, the width of the metal wirings 41 to 45 should be shortened to such an extent that an excessively strong electric field is not generated below the end portions of the metal wirings 41 to 45.
ただし、第１絶縁膜１９を比較的厚くすれば、金属配線４１～４５の幅は比較的広めにすることができる。例えば、第１絶縁膜１９の厚みが１～２μｍであれば、金属配線４１～４５の幅は２５～５０μｍ程度まで許容される。
However, if the first insulating film 19 is made relatively thick, the width of the metal wirings 41 to 45 can be made relatively wide. For example, if the thickness of the first insulating film 19 is 1 to 2 μm, the width of the metal wirings 41 to 45 is allowed to be about 25 to 50 μm.
また、半導体装置１（若しくは半導体装置２）では、浮遊電位金属配線群２２（若しくは浮遊電位金属配線群４０）を電界緩和層１３の外縁部の上部まで設けているが、図６に示された半導体装置１ａ及び図７に示された半導体装置２ａのように、電界緩和層１３の外縁の上部から中腹の上部まで、例えば、金属配線３４及び金属配線３５（若しくは金属配線４４及び金属配線４５）を省略した浮遊電位金属配線群２２ａ（若しくは浮遊電位金属配線群４０ａ）であっても、依然として、定常状態における半絶縁膜２３の電位は下に凸の分布であり、本発明の効果は得られる。初期状態における半導体基板１１の表面の電位分布によっては、このような形態の方が良好な効果を与えることもある。つまり、浮遊電位金属配線群２２の最外縁には適切な位置が存在する。
Further, in the semiconductor device 1 (or the semiconductor device 2), the floating potential metal wiring group 22 (or the floating potential metal wiring group 40) is provided up to the upper part of the outer edge portion of the electric field relaxation layer 13, as shown in FIG. As in the semiconductor device 1a and the semiconductor device 2a shown in FIG. 7, for example, the metal wiring 34 and the metal wiring 35 (or the metal wiring 44 and the metal wiring 45) from the upper part of the outer edge of the electric field relaxation layer 13 to the middle part. Even if the floating potential metal wiring group 22a (or the floating potential metal wiring group 40a) is omitted, the potential of the semi-insulating film 23 in the steady state still has a downwardly convex distribution, and the effect of the present invention can be obtained. . Depending on the potential distribution on the surface of the semiconductor substrate 11 in the initial state, such a configuration may give a better effect. That is, an appropriate position exists at the outermost edge of the floating potential metal wiring group 22.
一方で、例えば、半導体装置１において、最外の金属配線３５の最適な幅が、半導体装置１の製造工程で形成できる金属配線の幅の下限を下回る場合は、最外の金属配線３５は省略せざるを得ない。つまり、浮遊電位金属配線群２２の適切な形態は製造工程のルール（金属配線の幅又は間隔）によって制限されることがある。
On the other hand, for example, in the semiconductor device 1, when the optimum width of the outermost metal wiring 35 is below the lower limit of the width of the metal wiring that can be formed in the manufacturing process of the semiconductor device 1, the outermost metal wiring 35 is omitted. I have to. That is, an appropriate form of the floating potential metal wiring group 22 may be limited by a manufacturing process rule (width or interval of metal wiring).
とはいえ、アノードフィールドプレート２０の最外縁からストッパフィールドプレート２１の最内縁の間で半絶縁膜２３を短絡する浮遊電位金属配線群２２（若しくは浮遊電位金属配線群４０）の形成される面積の割合、換言すれば、“金属配線の幅”と“その金属配線の外縁端から、１つ内側にある金属配線の外縁端までの距離（外縁端間距離）”の比が、径方向の外側に向かって小さくなってさえすれば、定常状態における半絶縁膜２３のスムージングされた電位分布は下に凸となる。
However, the area of the floating potential metal wiring group 22 (or the floating potential metal wiring group 40) that short-circuits the semi-insulating film 23 between the outermost edge of the anode field plate 20 and the innermost edge of the stopper field plate 21 is formed. Ratio, in other words, the ratio of “the width of the metal wiring” and “the distance from the outer edge of the metal wiring to the outer edge of the inner metal wiring (the distance between the outer edges)” As long as it becomes smaller toward, the smoothed potential distribution of the semi-insulating film 23 in the steady state becomes convex downward.
すなわち、外縁端間距離が一定である場合に、金属配線の幅が、活性領域としてのベース層１２から離れるにつれて小さくなる構成であってもよいし、金属配線の幅が一定である場合に、外縁端間距離が、活性領域としてのベース層１２から離れるにつれて大きくなる構成であってもよい。また、電界緩和層１３の中腹の上部までは、外縁端間距離を一定にして、金属配線の幅を製造工程のルールで決まる最小の幅まで小さくしていき、それよりも外側では、金属配線の幅をその最小の幅で一定にして、外縁端間距離を大きくしていってもよい。
That is, when the distance between the outer edge ends is constant, the width of the metal wiring may be configured to decrease as the distance from the base layer 12 as the active region, or when the width of the metal wiring is constant, The configuration may be such that the distance between the outer edge ends increases with distance from the base layer 12 as the active region. In addition, the distance between the outer edge ends is made constant up to the middle part of the electric field relaxation layer 13, and the width of the metal wiring is reduced to the minimum width determined by the rules of the manufacturing process. The distance between the outer edges may be increased by making the width of the outer edge constant at the minimum width.
例えば、半導体装置１では、
［金属配線３１の幅］／［アノードフィールドプレート２０と金属配線３１の外縁端間距離］
＞［金属配線３２の幅］／［金属配線３１と金属配線３２の外縁端間距離］
＞［金属配線３３の幅］／［金属配線３２と金属配線３３の外縁端間距離］
＞［金属配線３４の幅］／［金属配線３３と金属配線３４の外縁端間距離］
＞［金属配線３５の幅］／［金属配線３４と金属配線３５の外縁端間距離］
となっており、
半導体装置２では、
［金属配線４１の幅］／［アノードフィールドプレート２０と金属配線４１の外縁端間距離］
＞［金属配線４２の幅］／［金属配線４１と金属配線４２の外縁端間距離］
＞［金属配線４３の幅］／［金属配線４２と金属配線４３の外縁端間距離］
＞［金属配線４４の幅］／［金属配線４３と金属配線４４の外縁端間距離］
＞［金属配線４５の幅］／［金属配線４４と金属配線４５の外縁端間距離］
となっている。 For example, in thesemiconductor device 1,
[Width of metal wiring 31] / [Distance between outer edge ends ofanode field plate 20 and metal wiring 31]
> [Width of metal wiring 32] / [Distance between outer edges ofmetal wiring 31 and metal wiring 32]
> [Width of metal wiring 33] / [Distance between outer edges ofmetal wiring 32 and metal wiring 33]
> [Width of metal wiring 34] / [Distance between outer edges ofmetal wiring 33 and metal wiring 34]
> [Width of metal wiring 35] / [Distance between outer edges ofmetal wiring 34 and metal wiring 35]
And
In thesemiconductor device 2,
[Width of metal wiring 41] / [Distance between outer edge ends ofanode field plate 20 and metal wiring 41]
> [Width of metal wiring 42] / [Distance between outer edges ofmetal wiring 41 and metal wiring 42]
> [Width of metal wiring 43] / [Distance between outer edges ofmetal wiring 42 and metal wiring 43]
> [Width of metal wiring 44] / [Distance between outer edges ofmetal wiring 43 and metal wiring 44]
> [Width of metal wiring 45] / [Distance between outer edges ofmetal wiring 44 and metal wiring 45]
It has become.
［金属配線３１の幅］／［アノードフィールドプレート２０と金属配線３１の外縁端間距離］
＞［金属配線３２の幅］／［金属配線３１と金属配線３２の外縁端間距離］
＞［金属配線３３の幅］／［金属配線３２と金属配線３３の外縁端間距離］
＞［金属配線３４の幅］／［金属配線３３と金属配線３４の外縁端間距離］
＞［金属配線３５の幅］／［金属配線３４と金属配線３５の外縁端間距離］
となっており、
半導体装置２では、
［金属配線４１の幅］／［アノードフィールドプレート２０と金属配線４１の外縁端間距離］
＞［金属配線４２の幅］／［金属配線４１と金属配線４２の外縁端間距離］
＞［金属配線４３の幅］／［金属配線４２と金属配線４３の外縁端間距離］
＞［金属配線４４の幅］／［金属配線４３と金属配線４４の外縁端間距離］
＞［金属配線４５の幅］／［金属配線４４と金属配線４５の外縁端間距離］
となっている。 For example, in the
[Width of metal wiring 31] / [Distance between outer edge ends of
> [Width of metal wiring 32] / [Distance between outer edges of
> [Width of metal wiring 33] / [Distance between outer edges of
> [Width of metal wiring 34] / [Distance between outer edges of
> [Width of metal wiring 35] / [Distance between outer edges of
And
In the
[Width of metal wiring 41] / [Distance between outer edge ends of
> [Width of metal wiring 42] / [Distance between outer edges of
> [Width of metal wiring 43] / [Distance between outer edges of
> [Width of metal wiring 44] / [Distance between outer edges of
> [Width of metal wiring 45] / [Distance between outer edges of
It has become.
また、半導体装置１では、
［金属配線３５の幅］／［金属配線３４と金属配線３５の外縁端間距離］
＞［金属配線３５の幅］／［金属配線３５の外縁端からストッパフィールドプレート２１の最内縁までの距離］
となっており、
半導体装置２では、
［金属配線４５の幅］／［金属配線４４と金属配線４５の外縁端間距離］
＞［金属配線４５の幅］／［金属配線４５の外縁端からストッパフィールドプレート２１の最内縁までの距離］
となっている。これらは換言すると、
［金属配線３４と金属配線３５との間隔］＞［金属配線３５とストッパフィールドプレート２１との間隔］
［金属配線４４と金属配線４５との間隔］＞［金属配線４５とストッパフィールドプレート２１との間隔］
ということになる。 In thesemiconductor device 1,
[Width of metal wiring 35] / [Distance between outer edges ofmetal wiring 34 and metal wiring 35]
> [Width of the metal wiring 35] / [Distance from the outer edge of themetal wiring 35 to the innermost edge of the stopper field plate 21]
And
In thesemiconductor device 2,
[Width of metal wiring 45] / [Distance between outer edges ofmetal wiring 44 and metal wiring 45]
> [Width of the metal wiring 45] / [Distance from the outer edge of themetal wiring 45 to the innermost edge of the stopper field plate 21]
It has become. In other words,
[Distance betweenMetal Wiring 34 and Metal Wiring 35]> [Distance Between Metal Wiring 35 and Stopper Field Plate 21]
[Distance betweenMetal Wiring 44 and Metal Wiring 45]> [Distance Between Metal Wiring 45 and Stopper Field Plate 21]
It turns out that.
［金属配線３５の幅］／［金属配線３４と金属配線３５の外縁端間距離］
＞［金属配線３５の幅］／［金属配線３５の外縁端からストッパフィールドプレート２１の最内縁までの距離］
となっており、
半導体装置２では、
［金属配線４５の幅］／［金属配線４４と金属配線４５の外縁端間距離］
＞［金属配線４５の幅］／［金属配線４５の外縁端からストッパフィールドプレート２１の最内縁までの距離］
となっている。これらは換言すると、
［金属配線３４と金属配線３５との間隔］＞［金属配線３５とストッパフィールドプレート２１との間隔］
［金属配線４４と金属配線４５との間隔］＞［金属配線４５とストッパフィールドプレート２１との間隔］
ということになる。 In the
[Width of metal wiring 35] / [Distance between outer edges of
> [Width of the metal wiring 35] / [Distance from the outer edge of the
And
In the
[Width of metal wiring 45] / [Distance between outer edges of
> [Width of the metal wiring 45] / [Distance from the outer edge of the
It has become. In other words,
[Distance between
[Distance between
It turns out that.
上記のように、最外の金属配線３５（若しくは金属配線４５）の内側と外側に位置する間隔は、内側の間隔が外側の間隔よりも小さい方が好ましい。しかし、場合によっては、この最外の金属配線３５（若しくは金属配線４５）の内側と外側の間隔に関する大小関係は逆転しても構わない。なぜなら、本発明においては、電界緩和層１３の内側寄りの部分の上部で、定常状態における半絶縁膜２３のスムージングされた電位分布が下に凸となることが最も重要であり、そこから最も離れたストッパフィールドプレート２１の近傍の影響は比較的受けにくいからである。
As described above, the distance between the inner and outer sides of the outermost metal wiring 35 (or metal wiring 45) is preferably such that the inner distance is smaller than the outer distance. However, in some cases, the magnitude relationship regarding the inner and outer intervals of the outermost metal wiring 35 (or metal wiring 45) may be reversed. This is because, in the present invention, it is most important that the smoothed potential distribution of the semi-insulating film 23 in the steady state is convex downward at the upper part of the electric field relaxation layer 13 closer to the inner side, and the farthest from there. This is because the influence of the vicinity of the stopper field plate 21 is relatively less susceptible.
また、図１６に示された半導体装置１ｂのように、電界緩和層１３の外縁の上部から中腹の上部までの金属配線、例えば、金属配線３４ｂの幅及び金属配線３５ｂの幅が金属配線３３の幅と等しい浮遊電位金属配線群２２ｂであっても、依然として、定常状態における半絶縁膜２３の電位は下に凸の分布であり、本発明の効果は得られる。
Further, as in the semiconductor device 1 b shown in FIG. 16, the metal wiring from the upper part of the outer edge of the electric field relaxation layer 13 to the upper part of the middle, for example, the width of the metal wiring 34 b and the width of the metal wiring 35 b is the same as that of the metal wiring 33. Even in the floating potential metal wiring group 22b having the same width, the potential of the semi-insulating film 23 in the steady state still has a downward convex distribution, and the effect of the present invention can be obtained.
若しくは、図１７に示された半導体装置２ｂのように、電界緩和層１３の外縁の上部から中腹の上部までの金属配線、例えば、［金属配線４３と金属配線４４ｂの外縁端間距離］及び［金属配線４４ｂと金属配線４５ｂの外縁端間距離］が［金属配線４２と金属配線４３の外縁端間距離］と等しい浮遊電位金属配線群４０ｂであっても、依然として、定常状態における半絶縁膜２３の電位は下に凸の分布であり、本発明の効果は得られる。
Alternatively, as in the semiconductor device 2b shown in FIG. 17, the metal wiring from the upper part of the outer edge of the electric field relaxation layer 13 to the upper part of the middle part, for example, [distance between the outer edges of the metal wiring 43 and the metal wiring 44b] and [ Even in the floating potential metal wiring group 40b in which the distance between the outer edges of the metal wiring 44b and the metal wiring 45b is equal to the [distance between the outer edges of the metal wiring 42 and the metal wiring 43], the semi-insulating film 23 is still in a steady state. This potential has a downward convex distribution, and the effect of the present invention can be obtained.
例えば、半導体装置１ｂでは、
［金属配線３１の幅］／［アノードフィールドプレート２０と金属配線３１の外縁端間距離］
＞［金属配線３２の幅］／［金属配線３１と金属配線３２の外縁端間距離］
＞［金属配線３３の幅］／［金属配線３２と金属配線３３の外縁端間距離］
＝［金属配線３４ｂの幅］／［金属配線３３と金属配線３４ｂの外縁端間距離］
＝［金属配線３５ｂの幅］／［金属配線３４ｂと金属配線３５ｂの外縁端間距離］
となっており、
半導体装置２ｂでは、
［金属配線４１の幅］／［アノードフィールドプレート２０と金属配線４１の外縁端間距離］
＞［金属配線４２の幅］／［金属配線４１と金属配線４２の外縁端間距離］
＞［金属配線４３の幅］／［金属配線４２と金属配線４３の外縁端間距離］
＝［金属配線４４ｂの幅］／［金属配線４３と金属配線４４ｂの外縁端間距離］
＝［金属配線４５ｂの幅］／［金属配線４４ｂと金属配線４５ｂの外縁端間距離］
となっている。 For example, in thesemiconductor device 1b,
[Width of metal wiring 31] / [Distance between outer edge ends ofanode field plate 20 and metal wiring 31]
> [Width of metal wiring 32] / [Distance between outer edges ofmetal wiring 31 and metal wiring 32]
> [Width of metal wiring 33] / [Distance between outer edges ofmetal wiring 32 and metal wiring 33]
= [Width ofmetal wiring 34b] / [distance between outer edges of metal wiring 33 and metal wiring 34b]
= [Width ofmetal wiring 35b] / [Distance between outer edges of metal wiring 34b and metal wiring 35b]
And
In thesemiconductor device 2b,
[Width of metal wiring 41] / [Distance between outer edge ends ofanode field plate 20 and metal wiring 41]
> [Width of metal wiring 42] / [Distance between outer edges ofmetal wiring 41 and metal wiring 42]
> [Width of metal wiring 43] / [Distance between outer edges ofmetal wiring 42 and metal wiring 43]
= [Width ofmetal wiring 44b] / [Distance between outer edges of metal wiring 43 and metal wiring 44b]
= [Width ofmetal wiring 45b] / [distance between outer edges of metal wiring 44b and metal wiring 45b]
It has become.
［金属配線３１の幅］／［アノードフィールドプレート２０と金属配線３１の外縁端間距離］
＞［金属配線３２の幅］／［金属配線３１と金属配線３２の外縁端間距離］
＞［金属配線３３の幅］／［金属配線３２と金属配線３３の外縁端間距離］
＝［金属配線３４ｂの幅］／［金属配線３３と金属配線３４ｂの外縁端間距離］
＝［金属配線３５ｂの幅］／［金属配線３４ｂと金属配線３５ｂの外縁端間距離］
となっており、
半導体装置２ｂでは、
［金属配線４１の幅］／［アノードフィールドプレート２０と金属配線４１の外縁端間距離］
＞［金属配線４２の幅］／［金属配線４１と金属配線４２の外縁端間距離］
＞［金属配線４３の幅］／［金属配線４２と金属配線４３の外縁端間距離］
＝［金属配線４４ｂの幅］／［金属配線４３と金属配線４４ｂの外縁端間距離］
＝［金属配線４５ｂの幅］／［金属配線４４ｂと金属配線４５ｂの外縁端間距離］
となっている。 For example, in the
[Width of metal wiring 31] / [Distance between outer edge ends of
> [Width of metal wiring 32] / [Distance between outer edges of
> [Width of metal wiring 33] / [Distance between outer edges of
= [Width of
= [Width of
And
In the
[Width of metal wiring 41] / [Distance between outer edge ends of
> [Width of metal wiring 42] / [Distance between outer edges of
> [Width of metal wiring 43] / [Distance between outer edges of
= [Width of
= [Width of
It has become.
半導体装置１ｂ及び半導体装置２ｂでは、半導体装置１ａ及び半導体装置２ａよりも、電界緩和層１３の外縁の上部から中腹の上部までの半絶縁膜２３の電位のばらつきが軽減される。なぜなら、金属配線３４ｂ及び金属配線３５ｂ（若しくは金属配線４４ｂ及び金属配線４５ｂ）が配置される箇所では、半絶縁膜２３の周方向の電位は等しくなるからである。その結果、半導体装置１ｂ及び半導体装置２ｂでは、半導体装置１ａ及び半導体装置２ａよりも、耐圧が安定する。
In the semiconductor device 1b and the semiconductor device 2b, the variation in potential of the semi-insulating film 23 from the upper part of the outer edge of the electric field relaxation layer 13 to the upper part of the middle is reduced as compared with the semiconductor device 1a and the semiconductor device 2a. This is because the potential in the circumferential direction of the semi-insulating film 23 is equal at a location where the metal wiring 34b and the metal wiring 35b (or the metal wiring 44b and the metal wiring 45b) are disposed. As a result, the breakdown voltage is more stable in the semiconductor device 1b and the semiconductor device 2b than in the semiconductor device 1a and the semiconductor device 2a.
＜効果＞
次に、本実施形態の半導体装置１及び半導体装置１ａを、６５００Ｖクラスの耐圧を有するＳｉの縦型ＰＩＮダイオードに適用した場合の効果について、図８及び図９に示されるシミュレーション結果を用いて説明する。 <Effect>
Next, the effect of applying thesemiconductor device 1 and the semiconductor device 1a of the present embodiment to a Si vertical PIN diode having a withstand voltage of 6500 V class will be described using simulation results shown in FIGS. To do.
次に、本実施形態の半導体装置１及び半導体装置１ａを、６５００Ｖクラスの耐圧を有するＳｉの縦型ＰＩＮダイオードに適用した場合の効果について、図８及び図９に示されるシミュレーション結果を用いて説明する。 <Effect>
Next, the effect of applying the
図８は、本実施形態の半導体装置１及び半導体装置１ａにおける耐圧に関するシミュレーション結果を示すグラフである。図８において、縦軸は、温度２９８Ｋにおける耐圧（Ｖ）を示し、横軸は、ＶＬＤ層１３の内縁部の注入量（ｃｍ－２）を示す。
FIG. 8 is a graph showing a simulation result regarding the breakdown voltage in the semiconductor device 1 and the semiconductor device 1a of the present embodiment. In FIG. 8, the vertical axis represents the breakdown voltage (V) at a temperature of 298 K, and the horizontal axis represents the implantation amount (cm −2 ) at the inner edge of the VLD layer 13.
図９は、本実施形態の半導体装置１及び半導体装置１ａにおける電界に関するシミュレーション結果を示すグラフである。図９において、縦軸は、逆方向バイアス６５００Ｖにおける半導体基板内部最大電界（Ｖ／ｃｍ）を示し、横軸は、ＶＬＤ層１３の内縁部の注入量（ｃｍ－２）を示す。
FIG. 9 is a graph showing simulation results regarding the electric field in the semiconductor device 1 and the semiconductor device 1a of the present embodiment. In FIG. 9, the vertical axis represents the maximum electric field (V / cm) inside the semiconductor substrate at a reverse bias of 6500 V, and the horizontal axis represents the implantation amount (cm −2 ) at the inner edge of the VLD layer 13.
図８及び図９ともに、ＶＬＤ層１３の外縁部の注入量は最内側の１／８である。半導体装置１の金属配線の数は４０個、最内の金属配線３１の幅は２５μｍ、最外の金属配線３５の幅は５μｍで、各金属配線３１～３５の幅は内側から外側に向かって線形に段階的に小さくなる。アノードフィールドプレート２０の幅は３０μｍである。半導体装置１ａは、半導体装置１の金属配線のうち、内側から数えて１５個目以降を省略したものである。
8 and 9, the injection amount of the outer edge of the VLD layer 13 is 1/8 of the innermost side. The number of metal wirings of the semiconductor device 1 is 40, the width of the innermost metal wiring 31 is 25 μm, the width of the outermost metal wiring 35 is 5 μm, and the width of each metal wiring 31 to 35 is from the inside to the outside. Decreases linearly in steps. The width of the anode field plate 20 is 30 μm. The semiconductor device 1a is obtained by omitting the fifteenth and subsequent pieces of metal wiring of the semiconductor device 1 counted from the inside.
図８及び図９では、半導体装置１からアノードフィールドプレート２０と浮遊電位金属配線群２２を省いたものの初期状態、半導体装置１からアノードフィールドプレート２０と浮遊電位金属配線群２２を省いたものの定常状態、半導体装置１から浮遊電位金属配線群２２を省いたものの定常状態、半導体装置１ａの定常状態、及び、半導体装置１の定常状態のシミュレーション結果を示している。半導体装置１からアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたもの以外の初期状態は、半導体装置１からアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの初期状態と概ね同じである。
8 and 9, the initial state of the semiconductor device 1 from which the anode field plate 20 and the floating potential metal wiring group 22 are omitted, and the steady state of the semiconductor device 1 from which the anode field plate 20 and the floating potential metal wiring group 22 are omitted. 7 shows simulation results of the steady state, the steady state of the semiconductor device 1a, and the steady state of the semiconductor device 1 with the floating potential metal wiring group 22 omitted from the semiconductor device 1. The initial state other than that in which the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 1 is almost the same as the initial state in which the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 1. The same.
図８では、半導体装置１からアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの初期状態を、参照符号「５１ａ」で示される細破線で示し、半導体装置１からアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの定常状態を、参照符号「５２ａ」で示される破線で示し、半導体装置１から浮遊電位金属配線群２２を省いたものの定常状態を、参照符号「５３ａ」で示される二点鎖線で示し、半導体装置１ａの定常状態を、参照符号「５４ａ」で示される一点鎖線で示し、半導体装置１の定常状態を、参照符号「５５ａ」で示される実線で示す。
In FIG. 8, the initial state of the semiconductor device 1 from which the anode field plate 20 and the floating potential metal wiring group 22 are omitted is indicated by a thin broken line indicated by reference numeral “51a”. The steady state without the floating potential metal wiring group 22 is indicated by a broken line indicated by reference numeral “52a”, and the steady state of the semiconductor device 1 without the floating potential metal wiring group 22 is indicated by reference numeral “53a”. The steady state of the semiconductor device 1a is indicated by a one-dot chain line indicated by reference numeral “54a”, and the steady state of the semiconductor device 1 is indicated by a solid line indicated by reference numeral “55a”.
図９では、半導体装置１からアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの初期状態を、参照符号「５１ｂ」で示される細破線で示し、半導体装置１からアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの定常状態を、参照符号「５２ｂ」で示される破線で示し、半導体装置１から浮遊電位金属配線群２２を省いたものの定常状態を、参照符号「５３ｂ」で示される二点鎖線で示し、半導体装置１ａの定常状態を、参照符号「５４ｂ」で示される一点鎖線で示し、半導体装置１の定常状態を、参照符号「５５ｂ」で示される実線で示す。
In FIG. 9, the initial state of the semiconductor device 1 from which the anode field plate 20 and the floating potential metal wiring group 22 are omitted is indicated by a thin broken line indicated by reference numeral “51 b”, and from the semiconductor device 1 to the anode field plate 20. The steady state without the floating potential metal wiring group 22 is indicated by a broken line indicated by reference numeral “52b”, and the steady state of the semiconductor device 1 without the floating potential metal wiring group 22 is indicated by reference numeral “53b”. The steady state of the semiconductor device 1a is indicated by a one-dot chain line indicated by reference numeral “54b”, and the steady state of the semiconductor device 1 is indicated by a solid line indicated by reference numeral “55b”.
図８において、初期状態で高耐圧が得られる注入量１．２～１．６×１０１２ｃｍ－２における、半導体装置１からアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの定常状態の耐圧、及び、半導体装置１から浮遊電位金属配線群２２を省いたものの定常状態の耐圧が、初期状態よりも低下している。換言すれば、逆方向バイアスした瞬間に保持できていた電圧が、連続的な逆方向バイアスにより半絶縁膜２３が充電されることで、保持できなくなってしまう。
In FIG. 8, the steady state is obtained by omitting the anode field plate 20 and the floating potential metal wiring group 22 from the semiconductor device 1 at an injection amount of 1.2 to 1.6 × 10 12 cm −2 at which a high breakdown voltage is obtained in the initial state. The breakdown voltage in the state and the breakdown voltage in the steady state after the floating potential metal wiring group 22 is omitted from the semiconductor device 1 are lower than in the initial state. In other words, the voltage that can be held at the moment of reverse bias cannot be held because the semi-insulating film 23 is charged by the continuous reverse bias.
定常状態に至るまでの時間の目安、すなわち、時定数は、第１絶縁膜１９の誘電率と厚さ、半絶縁膜２３の抵抗率と厚さ、及び、アノード電極１５の最外縁からストッパ電極１６の最内縁までの距離に依存する。
A measure of the time to reach a steady state, that is, the time constant, is the dielectric constant and thickness of the first insulating film 19, the resistivity and thickness of the semi-insulating film 23, and the stopper electrode from the outermost edge of the anode electrode 15. Depends on the distance to the 16 innermost edges.
一方で、図８において、半導体装置１ａの定常状態、及び、半導体装置１の定常状態では、初期状態よりも耐圧が上昇している。つまり、半絶縁膜２３の充電による経時的な耐圧の低下が解消されている。初期状態よりも耐圧が上昇しているのは、浮遊電位金属配線群２２で短絡された半絶縁膜２３の充電によって、半導体基板１１の内部の電界がより適切な分布に推移した結果である。
On the other hand, in FIG. 8, the breakdown voltage is higher in the steady state of the semiconductor device 1a and in the steady state of the semiconductor device 1 than in the initial state. That is, the decrease in breakdown voltage with time due to charging of the semi-insulating film 23 is eliminated. The breakdown voltage is higher than that in the initial state because the electric field inside the semiconductor substrate 11 has a more appropriate distribution due to the charging of the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22.
ところで、温度２９８Ｋにおける半絶縁膜２３の充電の時定数が１０秒である場合、耐圧測定に要する逆方向バイアスの印加時間が１秒であれば、初期状態に近い耐圧が得られる。しかし、アバランシェ降伏させた状態で逆方向バイアスを保持すると、耐圧が変動するクリープ現象が観測され、最終的に定常状態の耐圧に至る。
By the way, when the time constant for charging the semi-insulating film 23 at a temperature of 298 K is 10 seconds, the withstand voltage close to the initial state can be obtained if the reverse bias application time required for the withstand voltage measurement is 1 second. However, when the reverse bias is maintained in the avalanche breakdown state, a creep phenomenon in which the breakdown voltage fluctuates is observed, and finally a steady-state breakdown voltage is reached.
また、半絶縁膜２３は一般的にＰｏｏｌｅ－Ｆｒｅｎｋｅｌ伝導を示すため、半絶縁膜２３の抵抗率は温度上昇に伴って指数関数的に減少する。半絶縁膜２３の活性化エネルギーが０．５ｅＶであれば、温度３９８Ｋの半絶縁膜２３の抵抗率は温度２９８Ｋの１／１００になり、温度３９８Ｋにおける時定数は０．１秒になる。そのため、温度３９８Ｋで耐圧測定をすると、定常状態の耐圧が得られることになる。
Further, since the semi-insulating film 23 generally exhibits Poole-Frenkel conduction, the resistivity of the semi-insulating film 23 decreases exponentially with increasing temperature. If the activation energy of the semi-insulating film 23 is 0.5 eV, the resistivity of the semi-insulating film 23 at a temperature of 398K is 1/100 of the temperature 298K, and the time constant at the temperature 398K is 0.1 second. Therefore, when the pressure resistance is measured at a temperature of 398K, a steady-state pressure resistance can be obtained.
このように、実際の耐圧測定において得られる耐圧は、半絶縁膜２３の充電の時定数と逆方向バイアスが印加される時間の大小関係に大きく依存する。
Thus, the withstand voltage obtained in the actual withstand voltage measurement largely depends on the magnitude relationship between the charging time constant of the semi-insulating film 23 and the time during which the reverse bias is applied.
ｋＨｚオーダの周波数で動作するパワー半導体デバイスにおいて、初期状態の耐圧、すなわち、スイッチング時の瞬時の耐圧が高いこと必須である。したがって、定常状態の耐圧が高いからと言って、半導体装置１及び半導体装置１ａを注入量１．２～１．６×１０１２ｃｍ－２から外れた範囲で使用できるわけではない。
In a power semiconductor device operating at a frequency on the order of kHz, it is essential that the withstand voltage in the initial state, that is, the instantaneous withstand voltage during switching is high. Therefore, just because the steady-state breakdown voltage is high, the semiconductor device 1 and the semiconductor device 1a cannot be used in a range outside the injection amount of 1.2 to 1.6 × 10 12 cm −2 .
図９において、注入量１．２～１．６×１０１２ｃｍ－２における、半導体装置１ａの定常状態の半導体内部最大電界、及び、半導体装置１の定常状態の半導体内部最大電界は、初期状態と大きく変わらない。
In FIG. 9, the steady-state semiconductor internal maximum electric field of the semiconductor device 1a and the steady-state semiconductor internal maximum electric field of the semiconductor device 1 at an injection amount of 1.2 to 1.6 × 10 12 cm −2 are the initial state. And not much different.
一方で、図９において、半導体装置１からアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの定常状態の半導体内部最大電界、及び、半導体装置１から浮遊電位金属配線群２２を省いたものの定常状態の半導体内部最大電界は、初期状態よりもかなり大きい。これは、半導体基板１１の内部で適切に分散されていた電界集中点のバランスが崩れ、電界集中が１点に偏った結果である。
On the other hand, in FIG. 9, although the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 1, the semiconductor internal maximum electric field in the steady state and the floating potential metal wiring group 22 are omitted from the semiconductor device 1. However, the maximum electric field inside the semiconductor in the steady state is considerably larger than that in the initial state. This is a result of the electric field concentration points being appropriately dispersed inside the semiconductor substrate 11 being out of balance and the electric field concentration being biased to one point.
本実施形態によれば、半導体装置が、第１導電型（Ｎ型）の半導体基板１１と、半導体基板１１表面において部分的に形成された活性領域としてのベース層１２と、電界緩和層１３と、第１絶縁膜１９と、アノード電極１５と、複数の金属層としての金属配線３１～３５と、ストッパ電極１６と、半絶縁膜２３とを備える。
According to the present embodiment, the semiconductor device includes a first conductivity type (N-type) semiconductor substrate 11, a base layer 12 as an active region partially formed on the surface of the semiconductor substrate 11, an electric field relaxation layer 13, and the like. , A first insulating film 19, an anode electrode 15, metal wirings 31 to 35 as a plurality of metal layers, a stopper electrode 16, and a semi-insulating film 23.
電界緩和層１３は、半導体基板１１表面において、ベース層１２に接触し、かつ、ベース層１２を囲んで形成された第２導電型（Ｐ型）の不純物を含有する。第１絶縁膜１９は、ベース層１２の一部及び電界緩和層１３を覆って形成されている。アノード電極１５は、第１絶縁膜１９上の一部及びベース層１２上に跨がって形成されている。金属配線３１～３５は、電界緩和層１３が形成された位置の少なくとも一部に対応する第１絶縁膜１９上の位置において形成され、かつ、浮遊電位を有する。
The electric field relaxation layer 13 contains a second conductivity type (P-type) impurity formed in contact with the base layer 12 and surrounding the base layer 12 on the surface of the semiconductor substrate 11. The first insulating film 19 is formed so as to cover a part of the base layer 12 and the electric field relaxation layer 13. The anode electrode 15 is formed across a part of the first insulating film 19 and the base layer 12. The metal wirings 31 to 35 are formed at a position on the first insulating film 19 corresponding to at least a part of the position where the electric field relaxation layer 13 is formed, and have a floating potential.
金属配線３１～３５は、アノード電極１５から離れる方向において互いに離間し、かつ、それぞれがアノード電極１５を囲んで形成されている。ストッパ電極１６は、第１絶縁膜１９上及び半導体基板１１上に跨がって形成され、かつ、金属配線３１～３５を囲んで配置されている。半絶縁膜２３は、アノード電極１５からストッパ電極１６に亘る第１絶縁膜１９上に形成されている。
The metal wires 31 to 35 are separated from each other in a direction away from the anode electrode 15 and are formed so as to surround the anode electrode 15. The stopper electrode 16 is formed over the first insulating film 19 and the semiconductor substrate 11 and is disposed so as to surround the metal wirings 31 to 35. The semi-insulating film 23 is formed on the first insulating film 19 extending from the anode electrode 15 to the stopper electrode 16.
電界緩和層１３は、ベース層１２から離れる方向に延びて形成され、かつ、含有する第２導電型の不純物の濃度がベース層１２から離れるにつれて減少している。
The electric field relaxation layer 13 is formed extending in a direction away from the base layer 12, and the concentration of the second conductivity type impurity contained decreases as the distance from the base layer 12 increases.
各金属配線のアノード電極１５から離れる方向の幅をＷ、各金属配線のストッパ電極１６に近い側の端部である外縁端部と、アノード電極１５に近づく方向において当該金属配線と隣り合って配置されたアノード電極１５又は他の金属配線の外縁端部との間の距離をＤとした場合、各金属配線に関するＷ／Ｄが、アノード電極１５から離れるにつれて小さくなっている。
The width of each metal wiring in the direction away from the anode electrode 15 is W, the outer edge end that is the end of each metal wiring close to the stopper electrode 16, and the metal wiring in the direction approaching the anode electrode 15 are arranged adjacent to each other. Assuming that the distance between the anode electrode 15 and the outer edge of the other metal wiring is D, the W / D for each metal wiring decreases as the distance from the anode electrode 15 increases.
換言すれば、金属配線３１の幅ＷをＷ１、金属配線３２の幅ＷをＷ２、金属配線３３の幅ＷをＷ３、金属配線３４の幅ＷをＷ４、金属配線３５の幅ＷをＷ５とし、アノードフィールドプレート２０を含むアノード電極１５と金属配線３１との間隔ＤをＤ１、金属配線３１と金属配線３２との間隔ＤをＤ２、金属配線３２と金属配線３３との間隔ＤをＤ３、金属配線３３と金属配線３４との間隔ＤをＤ４、金属配線３４と金属配線３５との間隔ＤをＤ５とすると、
Ｗ１／Ｄ１＞Ｗ２／Ｄ２＞Ｗ３／Ｄ３＞Ｗ４／Ｄ４＞Ｗ５／Ｄ５
の関係を満たす。 In other words, the width W of themetal wiring 31 is W1, the width W of the metal wiring 32 is W2, the width W of the metal wiring 33 is W3, the width W of the metal wiring 34 is W4, and the width W of the metal wiring 35 is W5. The distance D between the anode electrode 15 including the anode field plate 20 and the metal wiring 31 is D1, the distance D between the metal wiring 31 and the metal wiring 32 is D2, and the distance D between the metal wiring 32 and the metal wiring 33 is D3. When the distance D between the metal wiring 34 and the metal wiring 34 is D4, and the distance D between the metal wiring 34 and the metal wiring 35 is D5,
W1 / D1> W2 / D2> W3 / D3> W4 / D4> W5 / D5
Satisfy the relationship.
Ｗ１／Ｄ１＞Ｗ２／Ｄ２＞Ｗ３／Ｄ３＞Ｗ４／Ｄ４＞Ｗ５／Ｄ５
の関係を満たす。 In other words, the width W of the
W1 / D1> W2 / D2> W3 / D3> W4 / D4> W5 / D5
Satisfy the relationship.
このような構成によれば、半絶縁膜２３を金属配線３１～３５によって短絡することにより、充電された後の半絶縁膜２３による半導体基板１１表面における電位分布が、電界緩和層１３による半導体基板１１表面における電位分布に近づく。その結果、半絶縁膜２３の充電前後で、半導体基板１１内部の電界集中点のバランスが保たれ、小面積、高耐圧性及び高信頼性を鼎立した半導体装置を実現することができる。
According to such a configuration, the semi-insulating film 23 is short-circuited by the metal wirings 31 to 35, so that the potential distribution on the surface of the semiconductor substrate 11 by the charged semi-insulating film 23 becomes the semiconductor substrate by the electric field relaxation layer 13. 11 approaches the potential distribution on the surface. As a result, the electric field concentration point in the semiconductor substrate 11 is kept balanced before and after the semi-insulating film 23 is charged, and a semiconductor device having a small area, high withstand voltage, and high reliability can be realized.
なお、アノードフィールドプレート２０を含むアノード電極１５を「第１電極」、ストッパフィールドプレート２１を含むストッパ電極１６を「第２電極」と呼ぶことがある。
The anode electrode 15 including the anode field plate 20 may be referred to as a “first electrode”, and the stopper electrode 16 including the stopper field plate 21 may be referred to as a “second electrode”.
なお、電界緩和層（ＶＬＤ層）１３の注入量は、内縁部と外縁部との間において径方向距離に対してシームレスかつ線形に漸減、あるいは、段階的かつ線形に漸減することが望ましいが、必ずしも線形でなくてもよい。言い換えれば、電界緩和層（ＶＬＤ層）１３の注入量は、内側から外側に向かって、上に凸に漸減しても、下に凸に漸減しても、本発明の効果は得られる。
The injection amount of the electric field relaxation layer (VLD layer) 13 is preferably seamlessly and linearly reduced with respect to the radial distance between the inner edge portion and the outer edge portion, or gradually and gradually reduced gradually. It does not necessarily have to be linear. In other words, the effect of the present invention can be obtained regardless of whether the injection amount of the electric field relaxation layer (VLD layer) 13 gradually decreases upward or downward from the inside to the outside.
なお、電界緩和層１３は、後述の電界緩和層５９、電界緩和層６６及び電界緩和層６９と入れ替えることもできる。
The electric field relaxation layer 13 can be replaced with an electric field relaxation layer 59, an electric field relaxation layer 66, and an electric field relaxation layer 69 which will be described later.
また、金属配線３１～３５は、金属配線４１～４５と入れ替えることもできる。
Further, the metal wirings 31 to 35 can be replaced with the metal wirings 41 to 45.
＜第２実施形態＞
＜構成＞
図１０は、本実施形態における半導体装置３の終端構造を拡大して示す模式断面図である。 Second Embodiment
<Configuration>
FIG. 10 is an enlarged schematic cross-sectional view showing the termination structure of the semiconductor device 3 in the present embodiment.
＜構成＞
図１０は、本実施形態における半導体装置３の終端構造を拡大して示す模式断面図である。 Second Embodiment
<Configuration>
FIG. 10 is an enlarged schematic cross-sectional view showing the termination structure of the semiconductor device 3 in the present embodiment.
本実施形態においても、第１実施形態と同様に、半導体装置３をＰＩＮダイオードに適用した場合の構成について説明する。半導体装置３は、第１実施形態の半導体装置１と構成が類似しているので、同一の構成については同一の参照符号を付して、共通する説明を省略する。
In this embodiment as well, as in the first embodiment, a configuration when the semiconductor device 3 is applied to a PIN diode will be described. Since the semiconductor device 3 is similar in configuration to the semiconductor device 1 of the first embodiment, the same configuration is denoted by the same reference numeral, and common description is omitted.
電界緩和層５９は、本実施形態では、複数の層構造としてのＰ型不純物層６０、Ｐ型不純物層６１、Ｐ型不純物層６２、Ｐ型不純物層６３、Ｐ型不純物層６４及びＰ型不純物層６５を備える。複数のＰ型不純物層６０～６５は、同じ注入量を有し、ベース層１２から離れる方向において互いに間隔をあけて形成されている。また、複数のＰ型不純物層６０～６５は、半導体基板１１の厚み方向一方側から見てベース層１２を囲繞するように形成される。Ｐ型不純物層６０～６５のうち電界緩和層５９の径方向において最も内側に形成されるＰ型不純物層６０は、ベース層１２に接して形成される。
In this embodiment, the electric field relaxation layer 59 includes a P-type impurity layer 60, a P-type impurity layer 61, a P-type impurity layer 62, a P-type impurity layer 63, a P-type impurity layer 64, and a P-type impurity having a plurality of layer structures. Layer 65 is provided. The plurality of P-type impurity layers 60 to 65 have the same implantation amount and are spaced apart from each other in the direction away from the base layer 12. The plurality of P-type impurity layers 60 to 65 are formed so as to surround the base layer 12 when viewed from one side in the thickness direction of the semiconductor substrate 11. Of the P-type impurity layers 60 to 65, the P-type impurity layer 60 formed on the innermost side in the radial direction of the electric field relaxation layer 59 is formed in contact with the base layer 12.
径方向において隣り合うＰ型不純物層同士の間隔は、径方向の内側から外側に向かうにしたがって線形に大きくなっている。最内のＰ型不純物層６０を除くＰ型不純物層６１～６５の幅は、径方向の内側から外側に向かうにしたがって線形に小さくなっている。隣り合うＰ型不純物層６０～６５同士の外縁端間距離は一定である。最内のＰ型不純物層６０の幅は、ベース層１２の濃度及び深さに基づいて別個に決定される。
The spacing between adjacent P-type impurity layers in the radial direction increases linearly from the inner side to the outer side in the radial direction. The widths of the P-type impurity layers 61 to 65 excluding the innermost P-type impurity layer 60 are linearly reduced from the inner side to the outer side in the radial direction. The distance between the outer edges of adjacent P-type impurity layers 60 to 65 is constant. The width of the innermost P-type impurity layer 60 is determined separately based on the concentration and depth of the base layer 12.
電界緩和層５９は、径方向に離散的なアクセプタイオンの分布を持つ。また、電界緩和層５９は、アクセプタイオンの空間電荷量の径方向における部分平均が、半導体装置の外側に向かって線形に段階的に漸減されている。電界緩和層５９は、ＬＮＦＬＲ（Ｌｉｎｅａｒｌｙ－Ｎａｒｒｏｗｅｄ Ｆｉｅｌｄ Ｌｉｍｉｔｉｎｇ Ｒｉｎｇ）と呼称されるものである（以下、電界緩和層５９をＬＮＦＬＲ５９と呼称することがある）。
The electric field relaxation layer 59 has a distribution of discrete acceptor ions in the radial direction. In the electric field relaxation layer 59, the partial average in the radial direction of the space charge amount of the acceptor ions is gradually decreased stepwise in a linear manner toward the outside of the semiconductor device. The electric field relaxation layer 59 is called LNFLR (Linearly-Narrowed Field Limiting Ring) (hereinafter, the electric field relaxation layer 59 may be called LNFLR 59).
＜作用＞
ＬＮＦＬＲ５９の注入量はリサーフ条件の２．５倍程度が最適である。ただし、注入量がリサーフ条件のおよそ１．５倍以上３．５倍以下の範囲であれば、十分に高い耐圧を得ることができる。 <Action>
The optimum injection amount ofLNFLR 59 is about 2.5 times the RESURF condition. However, if the injection amount is in the range of about 1.5 to 3.5 times the RESURF condition, a sufficiently high breakdown voltage can be obtained.
ＬＮＦＬＲ５９の注入量はリサーフ条件の２．５倍程度が最適である。ただし、注入量がリサーフ条件のおよそ１．５倍以上３．５倍以下の範囲であれば、十分に高い耐圧を得ることができる。 <Action>
The optimum injection amount of
アノードフィールドプレート２０と、浮遊電位金属配線群２２を構成する複数の金属配線３１～３５とは、それぞれ、Ｐ型不純物層６０～６５の上部に対応して設けられる。アノードフィールドプレート２０の幅及び金属配線３１～３５の幅は、それぞれ、Ｐ型不純物層６０～６５の幅とおおよそ等しい。
The anode field plate 20 and the plurality of metal wires 31 to 35 constituting the floating potential metal wire group 22 are provided corresponding to the upper portions of the P-type impurity layers 60 to 65, respectively. The width of the anode field plate 20 and the width of the metal wirings 31 to 35 are approximately equal to the widths of the P-type impurity layers 60 to 65, respectively.
半導体装置３においても、逆方向バイアス時におけるベース層１２の最外縁からストッパ層１４の最内縁までの半導体基板１１の表面の電位は、アノード電位からカソード電位まで、部分平均化（スムージング）した状態で、下に凸の変化で推移する。特に、ＬＮＦＬＲ５９においては、Ｐ型不純物層６０～６５の間隙領域が比較的低い逆方向バイアス電圧で最表面まで空乏化し、Ｐ型不純物層６０～６５の間隙領域に横方向電界、すなわち、電位の勾配が発生する。一方で、Ｐ型不純物層６０～６５の注入量が高いために、Ｐ型不純物層６０～６５の最表面は一部しか空乏化しない。その結果、初期状態における半導体基板１１の表面のスムージングされた電位は、下に凸の二次関数的な分布となる。
Also in the semiconductor device 3, the surface potential of the semiconductor substrate 11 from the outermost edge of the base layer 12 to the innermost edge of the stopper layer 14 during reverse bias is partially averaged (smoothed) from the anode potential to the cathode potential. Then, it changes with a convex change downward. In particular, in the LNFLR 59, the gap region of the P-type impurity layers 60 to 65 is depleted to the outermost surface with a relatively low reverse bias voltage, and a lateral electric field, that is, a potential is generated in the gap region of the P-type impurity layers 60 to 65. A gradient occurs. On the other hand, since the implantation amount of the P-type impurity layers 60 to 65 is high, only a part of the outermost surface of the P-type impurity layers 60 to 65 is depleted. As a result, the smoothed potential on the surface of the semiconductor substrate 11 in the initial state has a downwardly convex quadratic distribution.
浮遊電位金属配線群２２で短絡された半絶縁膜２３の定常状態におけるスムージングされた電位はそもそも下に凸の二次関数的な分布であるが、半導体装置３では、アノードフィールドプレート２０の位置及び幅と金属配線３１～３５の位置及び幅とを、それぞれＰ型不純物層６０～６５と合わせているため、定常状態における半導体基板１１の表面の電位分布が、初期状態における半導体基板１１の表面の電位分布にかなり近くなる。
The smoothed potential in the steady state of the semi-insulating film 23 short-circuited by the floating potential metal wiring group 22 has a quadratic distribution that is convex downward, but in the semiconductor device 3, the position of the anode field plate 20 and Since the width and the position and width of the metal wirings 31 to 35 are respectively matched with the P-type impurity layers 60 to 65, the potential distribution on the surface of the semiconductor substrate 11 in the steady state is the same as that of the surface of the semiconductor substrate 11 in the initial state. It becomes quite close to the potential distribution.
その結果、半導体基板１１の内部の電界が、充電後の半絶縁膜２３によって乱されにくくなる。すなわち、半絶縁膜２３の充電による耐圧の変動が生じにくい。
As a result, the electric field inside the semiconductor substrate 11 is not easily disturbed by the semi-insulating film 23 after charging. That is, fluctuations in breakdown voltage due to charging of the semi-insulating film 23 are unlikely to occur.
また、第１実施形態と同様に、図１１に示された半導体装置３ａのように、製造工程の制約によって、浮遊電位金属配線群２２のうち外側寄りのＰ型不純物層６４及びＰ型不純物層６５の上部に配置する金属配線３４及び金属配線３５が省略されても構わない。すなわち、ＬＮＦＬＲ５９のうちの少なくとも一部が形成された位置、つまり、Ｐ型不純物層６１、Ｐ型不純物層６２及びＰ型不純物層６３が形成された位置に対応する第１絶縁膜１９上の位置に、浮遊電位金属配線群２２ａが形成されていてもよい。
Similarly to the first embodiment, as in the semiconductor device 3a shown in FIG. 11, the P-type impurity layer 64 and the P-type impurity layer located on the outer side of the floating potential metal wiring group 22 due to manufacturing process restrictions. The metal wiring 34 and the metal wiring 35 arranged on the upper part of 65 may be omitted. That is, a position on the first insulating film 19 corresponding to a position where at least a part of the LNFLR 59 is formed, that is, a position where the P-type impurity layer 61, the P-type impurity layer 62, and the P-type impurity layer 63 are formed. In addition, the floating potential metal wiring group 22a may be formed.
なぜなら、本実施形態では、ＬＮＦＬＲ５９の内側寄りの部分において、初期状態における半導体基板１１の表面の電位分布が、定常状態における半絶縁膜２３の電位分布に近くなっていることが最も重要であり、ＬＮＦＬＲ５９の外側寄りの部分の影響は比較的受けにくいからである。
This is because, in this embodiment, in the portion closer to the inside of the LNFLR 59, it is most important that the potential distribution on the surface of the semiconductor substrate 11 in the initial state is close to the potential distribution of the semi-insulating film 23 in the steady state. This is because the influence of the portion closer to the outside of the LNFLR 59 is relatively difficult to receive.
また、第１実施形態と同様に、図１８に示された半導体装置３ｃのように、浮遊電位金属配線群２２ｂのうち外側寄りのＰ型不純物層６４及びＰ型不純物層６５の上部に配置する金属配線３４ｂ及び金属配線３５ｂの幅が、Ｐ型不純物層６３の上部に配置する金属配線３３の幅と等しくても構わない。
Similarly to the first embodiment, like the semiconductor device 3c shown in FIG. 18, the floating potential metal wiring group 22b is disposed on the outer side of the P-type impurity layer 64 and the P-type impurity layer 65. The widths of the metal wiring 34 b and the metal wiring 35 b may be equal to the width of the metal wiring 33 disposed on the P-type impurity layer 63.
また、図１９に示された半導体装置３ｄのように、金属配線３３と幅が等しい金属配線３４ｃがＰ型不純物層６４の全体の上部を覆い、金属配線３３と幅が等しい金属配線３５ｃがＰ型不純物層６５の全体の上部を覆っても構わない。
19, the metal wiring 34c having the same width as the metal wiring 33 covers the entire upper portion of the P-type impurity layer 64, and the metal wiring 35c having the same width as the metal wiring 33 is P. The entire upper portion of the type impurity layer 65 may be covered.
また、図２０に示された半導体装置３ｅのように、Ｐ型不純物層６４の上部に配置する金属配線を省略し、Ｐ型不純物層６５の上部に金属配線３３と幅が等しい金属配線３５ｃを配置しても構わない。
Also, as in the semiconductor device 3e shown in FIG. 20, the metal wiring disposed on the P-type impurity layer 64 is omitted, and the metal wiring 35c having the same width as the metal wiring 33 is formed on the P-type impurity layer 65. You may arrange.
上記では、簡単のために、Ｐ型不純物層６０～６５が互いに間隔を開けて形成されるものとしたが、図１２に示された半導体装置３ｂのように、比較的強い熱拡散によって広がる拡散層によって、Ｐ型不純物層６０～６５のうち、内側のいくつかが繋がった電界緩和層６６（ＬＮＦＬＲ６６）を形成しても良い。すなわち、ベース層１２に接するＰ型不純物層６０と、そのＰ型不純物層６０と隣り合って配置されたＰ型不純物層６１とが繋がって形成されていてもよい。このような形態でも、アクセプタイオンの空間電荷量の径方向における部分平均は、半導体装置の外側に向かって線形に段階的に漸減される。また、拡散層に相当する部分は、より低濃度のＰ型不純物領域であるので、比較的低い逆方向バイアス電圧で容易に空乏化する。したがって、半導体基板１１の表面に沿って径方向に広がった拡散層に相当する部分は、比較的低い逆方向バイアス電圧で最表面まで空乏化する。つまり、比較的強い熱拡散によって拡散層を広げた形態でも、初期状態における半導体基板１１の表面の電位は、スムージングされた状態で、下に凸の二次関数的な分布となる。
In the above, for the sake of simplicity, the P-type impurity layers 60 to 65 are formed to be spaced apart from each other. However, as in the semiconductor device 3b shown in FIG. Depending on the layer, an electric field relaxation layer 66 (LNFLR 66) in which some of the P-type impurity layers 60 to 65 are connected to each other inside may be formed. That is, the P-type impurity layer 60 in contact with the base layer 12 and the P-type impurity layer 61 disposed adjacent to the P-type impurity layer 60 may be connected to each other. Even in such a form, the partial average in the radial direction of the space charge amount of the acceptor ions is gradually reduced stepwise linearly toward the outside of the semiconductor device. Further, since the portion corresponding to the diffusion layer is a lower concentration P-type impurity region, it is easily depleted with a relatively low reverse bias voltage. Therefore, the portion corresponding to the diffusion layer extending in the radial direction along the surface of the semiconductor substrate 11 is depleted to the outermost surface with a relatively low reverse bias voltage. That is, even in a form in which the diffusion layer is expanded by relatively strong thermal diffusion, the potential of the surface of the semiconductor substrate 11 in the initial state has a downward convex quadratic function distribution in a smoothed state.
さらに、比較的強い熱拡散によって拡散層を広げれば、半導体基板１１の内部の電界集中が抑制され、より高い耐圧を得ることができる。
Furthermore, if the diffusion layer is widened by relatively strong thermal diffusion, electric field concentration inside the semiconductor substrate 11 can be suppressed, and higher breakdown voltage can be obtained.
半導体基板１１の材料がシリコンであり、かつ、Ｐ型不純物層６０～６５のアクセプタイオン種がボロンである場合、ボロンは比較的容易に熱拡散される。そのため、Ｐ型不純物層６０～６５のうち内側のいくつかが繋がった電界緩和層６６（ＬＮＦＬＲ６６）が形成される。
When the material of the semiconductor substrate 11 is silicon and the acceptor ion species of the P-type impurity layers 60 to 65 is boron, boron is thermally diffused relatively easily. Therefore, an electric field relaxation layer 66 (LNFLR 66) in which some of the P-type impurity layers 60 to 65 are connected to each other is formed.
ただし、電界緩和層６６（ＬＮＦＬＲ６６）を形成する場合、上記の「Ｐ型不純物層６０～６５の幅」は「Ｐ型不純物層６０～６５を形成するために不純物イオンが注入される領域（Ｐ型不純物層６０～６５の注入窓）の幅」と言い換えることになる。つまり、金属配線３１～３５の幅は、Ｐ型不純物層６０～６５の幅よりも小さくなる。
However, when the electric field relaxation layer 66 (LNFLR 66) is formed, the “width of the P-type impurity layers 60 to 65” described above is the “region into which impurity ions are implanted to form the P-type impurity layers 60 to 65 (P In other words, the width of the implantation windows of the type impurity layers 60 to 65). That is, the width of the metal wirings 31 to 35 is smaller than the width of the P-type impurity layers 60 to 65.
なお、電界緩和層５９及び６６は、隣り合うＰ型不純物層同士の間隔が内側から外側に向かって線形に大きくなり、Ｐ型不純物層６１～６５の幅が内側から外側に向かって線形に小さくなり、隣り合うＰ型不純物層６０～６５同士の外縁端間距離が一定であることが望ましいが、電界緩和層５９及び６６の部分平均の注入量が、内側から外側に向かって漸減していれば、必ずしもこのルールに従わなくてもよい。言い換えれば、電界緩和層５９及び６６の部分平均の注入量は、内側から外側に向かって、上に凸に漸減しても、下に凸に漸減しても、本発明の効果は得られる。
In the electric field relaxation layers 59 and 66, the interval between adjacent P-type impurity layers increases linearly from the inside to the outside, and the widths of the P-type impurity layers 61 to 65 decrease linearly from the inside to the outside. Therefore, it is desirable that the distance between the outer edges of the adjacent P-type impurity layers 60 to 65 is constant, but the partial average implantation amount of the electric field relaxation layers 59 and 66 may be gradually decreased from the inside toward the outside. For example, it is not always necessary to follow this rule. In other words, the effect of the present invention can be obtained regardless of whether the partial average injection amount of the electric field relaxation layers 59 and 66 gradually decreases upward or downward from the inside to the outside.
＜変形例＞
図１３は、本実施形態の変形例における半導体装置４の終端構造を拡大して示す模式断面図である。 <Modification>
FIG. 13 is an enlarged schematic cross-sectional view showing the termination structure of thesemiconductor device 4 in a modification of the present embodiment.
図１３は、本実施形態の変形例における半導体装置４の終端構造を拡大して示す模式断面図である。 <Modification>
FIG. 13 is an enlarged schematic cross-sectional view showing the termination structure of the
電界緩和層６９は、複数の層構造としてのＰ型不純物層７０、Ｐ型不純物層７１、Ｐ型不純物層７２、Ｐ型不純物層７３、Ｐ型不純物層７４及びＰ型不純物層７５を備える。複数のＰ型不純物層７０～７５は、互いに間隔を開けて形成される。また、複数のＰ型不純物層７０～７５は、半導体基板１１の厚み方向一方側から見て、ベース層１２を囲繞するように形成されている。Ｐ型不純物層７０～７５のうち、電界緩和層６９の径方向において最も内側に形成されるＰ型不純物層７０は、ベース層１２に接して形成される。
The electric field relaxation layer 69 includes a P-type impurity layer 70, a P-type impurity layer 71, a P-type impurity layer 72, a P-type impurity layer 73, a P-type impurity layer 74, and a P-type impurity layer 75 as a plurality of layer structures. The plurality of P-type impurity layers 70 to 75 are formed at intervals. The plurality of P-type impurity layers 70 to 75 are formed so as to surround the base layer 12 when viewed from one side in the thickness direction of the semiconductor substrate 11. Of the P-type impurity layers 70 to 75, the P-type impurity layer 70 formed on the innermost side in the radial direction of the electric field relaxation layer 69 is formed in contact with the base layer 12.
径方向において隣り合うＰ型不純物層７０～７５同士の間隔は、径方向の内側から外側に向かうにしたがって大きくなっている。Ｐ型不純物層７０～７５の幅は一定である。
The interval between the P-type impurity layers 70 to 75 adjacent in the radial direction increases from the inner side to the outer side in the radial direction. The widths of the P-type impurity layers 70 to 75 are constant.
この構成により、電界緩和層６９に含まれる空間電荷量（正確に言えば、空間電荷量の部分平均）は、半導体装置の外側に向かって段階的に漸減される。電界緩和層６９の注入量はリサーフ条件の２．５倍程度が最適である。ただし、注入量がリサーフ条件のおよそ１．５倍以上３．５倍以下の範囲であれば、比較的高い耐圧を得ることができる。
With this configuration, the amount of space charge contained in the electric field relaxation layer 69 (more precisely, the partial average of the amount of space charge) is gradually reduced toward the outside of the semiconductor device. The injection amount of the electric field relaxation layer 69 is optimally about 2.5 times the RESURF condition. However, if the injection amount is in the range of about 1.5 to 3.5 times the RESURF condition, a relatively high breakdown voltage can be obtained.
アノードフィールドプレート２０、及び、浮遊電位金属配線群４０を構成する複数の金属配線４１～４５は、それぞれＰ型不純物層７０～７５の上部に対応して設けられる。アノードフィールドプレート２０の幅及び金属配線４１～４５の幅は、それぞれＰ型不純物層７０～７５の幅とおおよそ等しい。
The anode field plate 20 and the plurality of metal wires 41 to 45 constituting the floating potential metal wire group 40 are provided corresponding to the upper portions of the P-type impurity layers 70 to 75, respectively. The width of the anode field plate 20 and the width of the metal wirings 41 to 45 are approximately equal to the widths of the P-type impurity layers 70 to 75, respectively.
半導体装置４の効果は半導体装置３と同様である。また、半導体装置４では、浮遊電位金属配線群４０の幅が一定であるため、製造工程の制約を受けにくい。しかし、半導体装置４の電界緩和層６９では、半導体装置３のＬＮＦＬＲ５９よりも半導体基板内部電界を低減しにくいため、半導体装置４の方が初期状態の耐圧が少し低い。
The effect of the semiconductor device 4 is the same as that of the semiconductor device 3. Further, in the semiconductor device 4, since the width of the floating potential metal wiring group 40 is constant, it is difficult to be restricted by the manufacturing process. However, since the electric field relaxation layer 69 of the semiconductor device 4 is more difficult to reduce the electric field inside the semiconductor substrate than the LNFLR 59 of the semiconductor device 3, the semiconductor device 4 has a slightly lower breakdown voltage in the initial state.
半導体装置４において、熱拡散によって拡散層を広げた形態については、第２実施形態の半導体装置３ｂと同様である。
In the semiconductor device 4, the form in which the diffusion layer is expanded by thermal diffusion is the same as that of the semiconductor device 3b of the second embodiment.
なお、第２実施形態において、Ｐ型不純物層６１～６５（若しくはＰ型不純物層７１～７５）と金属配線３１～３５（若しくは金属配線４１～４５）との配置位置を揃えたが、Ｐ型不純物層と金属配線とで、数、位置、さらには幅、間隔を独立に設定しても、第１実施形態に準ずる効果は得られる。ただし、Ｐ型不純物層と金属配線との位置関係によっては、半導体基板１１の内部の電界が局所的に高まり初期状態の耐圧が低下する場合がある。この点は第１実施形態と異なる。
In the second embodiment, the arrangement positions of the P-type impurity layers 61 to 65 (or P-type impurity layers 71 to 75) and the metal wirings 31 to 35 (or metal wirings 41 to 45) are aligned. Even if the number, position, width, and interval of the impurity layer and the metal wiring are set independently, the effect according to the first embodiment can be obtained. However, depending on the positional relationship between the P-type impurity layer and the metal wiring, the electric field inside the semiconductor substrate 11 may locally increase and the initial breakdown voltage may decrease. This point is different from the first embodiment.
＜効果＞
次に、本実施形態の半導体装置３ｂを、６５００Ｖクラスの耐圧を有するＳｉの縦型ＰＩＮダイオードに適用した場合の効果について、図１４及び図１５に示されるシミュレーション結果を用いて説明する。 <Effect>
Next, the effect when thesemiconductor device 3b of this embodiment is applied to a Si vertical PIN diode having a breakdown voltage of 6500 V class will be described using simulation results shown in FIGS.
次に、本実施形態の半導体装置３ｂを、６５００Ｖクラスの耐圧を有するＳｉの縦型ＰＩＮダイオードに適用した場合の効果について、図１４及び図１５に示されるシミュレーション結果を用いて説明する。 <Effect>
Next, the effect when the
図１４は、本実施形態の半導体装置３ｂにおける耐圧に関するシミュレーション結果を示すグラフである。図１４において、縦軸は、温度２９８Ｋにおける耐圧（Ｖ）を示し、横軸は、ＬＮＦＬＲ６６の注入量（ｃｍ－２）を示す。
FIG. 14 is a graph showing a simulation result regarding the breakdown voltage in the semiconductor device 3b of the present embodiment. In FIG. 14, the vertical axis represents the breakdown voltage (V) at a temperature of 298K, and the horizontal axis represents the injection amount (cm −2 ) of LNFLR 66.
図１５は、本実施形態の半導体装置３ｂにおける電界に関するシミュレーション結果を示すグラフである。図１５において、縦軸は、逆方向バイアス６５００Ｖにおける半導体基板内部最大電界（Ｖ／ｃｍ）を示し、横軸は、ＬＮＦＬＲ６６の注入量（ｃｍ－２）を示す。
FIG. 15 is a graph showing a simulation result regarding the electric field in the semiconductor device 3b of the present embodiment. In FIG. 15, the vertical axis represents the maximum electric field (V / cm) inside the semiconductor substrate at the reverse bias of 6500 V, and the horizontal axis represents the injection amount (cm −2 ) of LNFLR 66.
図１４及び図１５ともに、Ｐ型不純物層６０～６５の数は４１個、最内のＰ型不純物層６０の注入窓の幅は３０μｍ、最内から２個目のＰ型不純物層６１の注入窓の幅は２５μｍ、最外のＰ型不純物層６５の注入窓の幅は５μｍであり、最内のＰ型不純物層６０を除く各Ｐ型不純物層６１～６５の注入窓の幅は内側から外側に向かって線形に小さくなる。半導体装置３のアノードフィールドプレート２０及び４０個の金属配線３１～３５は、下部のＰ型不純物層６０～６５の注入窓の位置の上部に設けられる。
14 and 15, the number of P-type impurity layers 60 to 65 is 41, the width of the implantation window of the innermost P-type impurity layer 60 is 30 μm, and the implantation of the second P-type impurity layer 61 from the innermost is performed. The width of the window is 25 μm, the width of the implantation window of the outermost P-type impurity layer 65 is 5 μm, and the width of the implantation windows of the P-type impurity layers 61 to 65 excluding the innermost P-type impurity layer 60 is from the inside. Linearly decreases toward the outside. The anode field plate 20 and the 40 metal wirings 31 to 35 of the semiconductor device 3 are provided above the positions of the implantation windows of the lower P-type impurity layers 60 to 65.
図１４及び図１５では、半導体装置３ｂからアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの初期状態、半導体装置３ｂからアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの定常状態、半導体装置３ｂから浮遊電位金属配線群２２を省いたものの定常状態、半導体装置３ｂから内側から数えて１５個目以降の金属配線３４及び金属配線３５を省略したものの定常状態、及び、半導体装置３ｂの定常状態のシミュレーション結果を示している。半導体装置３ｂからアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたもの以外の初期状態は、半導体装置３ｂからアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの初期状態と概ね同じである。
14 and 15, the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 3b, but the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 3b. A steady state in which the floating potential metal wiring group 22 is omitted from the semiconductor device 3b, a steady state in which the fifteenth and subsequent metal wirings 34 and the metal wiring 35 are omitted from the semiconductor device 3b, and a semiconductor The simulation result of the steady state of the apparatus 3b is shown. The initial state other than that in which the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 3b is almost the same as the initial state in which the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 3b. The same.
図１４では、半導体装置３ｂからアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの初期状態を、参照符号「８１ａ」で示される点線で示し、半導体装置３ｂからアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの定常状態を、参照符号「８２ａ」で示される破線で示し、半導体装置３ｂから浮遊電位金属配線群２２を省いたものの定常状態を、参照符号「８３ａ」で示される二点鎖線で示し、半導体装置３ｂから内側から数えて１５個目以降の金属配線３４及び金属配線３５を省略したものの定常状態を、参照符号「８４ａ」で示される一点鎖線で示し、半導体装置３ｂの定常状態を、参照符号「８５ａ」で示される実線で示す。
In FIG. 14, the initial state of the semiconductor device 3b from which the anode field plate 20 and the floating potential metal wiring group 22 are omitted is indicated by a dotted line indicated by reference numeral “81a”. The steady state without the potential metal wiring group 22 is indicated by a broken line indicated by reference numeral “82a”, and the steady state when the floating potential metal wiring group 22 is omitted from the semiconductor device 3b is indicated by reference numeral “83a”. The steady state of the semiconductor device 3b from which the fifteenth and subsequent metal wirings 34 and metal wirings 35 are omitted is indicated by a one-dot chain line denoted by reference numeral "84a" The steady state of the device 3b is indicated by a solid line denoted by reference numeral “85a”.
図１５では、半導体装置３ｂからアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの初期状態を、参照符号「８１ｂ」で示される点線で示し、半導体装置３ｂからアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの定常状態を、参照符号「８２ｂ」で示される破線で示し、半導体装置３ｂから浮遊電位金属配線群２２を省いたものの定常状態を、参照符号「８３ｂ」で示される二点鎖線で示し、半導体装置３ｂから内側から数えて１５個目以降の金属配線３４及び金属配線３５を省略したものの定常状態を、参照符号「８４ｂ」で示される一点鎖線で示し、半導体装置３ｂの定常状態を、参照符号「８５ｂ」で示される実線で示す。
In FIG. 15, the initial state of the semiconductor device 3b from which the anode field plate 20 and the floating potential metal wiring group 22 are omitted is indicated by a dotted line indicated by reference numeral “81b”. The steady state without the potential metal wiring group 22 is indicated by a broken line indicated by reference numeral “82b”, and the steady state when the floating potential metal wiring group 22 is omitted from the semiconductor device 3b is indicated by reference numeral “83b”. The steady state of the semiconductor device 3b from which the fifteenth and subsequent metal wires 34 and metal wires 35 are omitted from the inside is indicated by a one-dot chain line indicated by reference numeral "84b" The steady state of the device 3b is indicated by a solid line indicated by reference numeral “85b”.
図１４において、初期状態で特に高耐圧が得られる注入量１．９～３．８×１０１２ｃｍ－２における、半導体装置３ｂからアノードフィールドプレート２０と浮遊電位金属配線群２２とを省いたものの定常状態の耐圧、及び、半導体装置３ｂから浮遊電位金属配線群２２を省いたものの定常状態の耐圧は、初期状態よりも大幅に低下している。
In FIG. 14, the anode field plate 20 and the floating potential metal wiring group 22 are omitted from the semiconductor device 3b at an injection amount of 1.9 to 3.8 × 10 12 cm −2 at which a particularly high breakdown voltage is obtained in the initial state. The steady-state withstand voltage and the steady-state withstand voltage of the semiconductor device 3b without the floating potential metal wiring group 22 are significantly lower than in the initial state.
一方で、図１４において、半導体装置３ｂから内側から数えて１５個目以降の金属配線３４及び金属配線３５を省略したものの定常状態、及び、半導体装置３ｂの定常状態では、初期状態に近い耐圧が得られている。特に、注入量２．５×１０１２ｃｍ－２では、半絶縁膜２３の充電の前後での耐圧の変化が小さい。
On the other hand, in FIG. 14, the breakdown voltage close to the initial state is obtained in the steady state and the steady state of the semiconductor device 3b although the fifteenth and subsequent metal wires 34 and metal wires 35 counted from the inside of the semiconductor device 3b are omitted. Has been obtained. In particular, when the injection amount is 2.5 × 10 12 cm −2 , the change in breakdown voltage before and after charging of the semi-insulating film 23 is small.
これが、半絶縁膜２３の定常状態における電位分布と初期状態における半導体基板１１の表面の電位が近くなるように、浮遊電位金属配線群２２を配置した効果である。半絶縁膜２３の充電による、半導体基板１１の表面の電位の変化を抑えることで、半導体基板１１の内部の電界のバランスを保持している。
This is the effect of arranging the floating potential metal wiring group 22 so that the potential distribution in the steady state of the semi-insulating film 23 is close to the potential of the surface of the semiconductor substrate 11 in the initial state. By suppressing the change in the potential of the surface of the semiconductor substrate 11 due to the charging of the semi-insulating film 23, the balance of the electric field inside the semiconductor substrate 11 is maintained.
図１５において、注入量２．５×１０１２ｃｍ－２における、半導体装置３ｂから浮遊電位金属配線群２２を省いたものの定常状態の半導体基板内部最大電界と、半導体装置３ｂの定常状態の半導体基板内部最大電界とは、大きく違わない。それにもかかわらず、耐圧に大きな差が生じている理由は、半導体装置３ｂから浮遊電位金属配線群２２を省いたものの定常状態では、ベース層１２の最外縁の１点に際立った電界集中が生じるのに対し、半導体装置３ｂの定常状態では、電界集中点が適切に分散された状態が保持されるためである。ベース層１２、すなわち、活性領域の最外縁に際立った電界集中が生じた場合、終端構造により電界集中点が適切に分散された場合に比べて、アバランシェ降伏が発生しやすい傾向がある。
In FIG. 15, the maximum electric field inside the semiconductor substrate in the steady state and the semiconductor substrate in the steady state of the semiconductor device 3 b with the floating amount metal wiring group 22 omitted from the semiconductor device 3 b at the injection amount of 2.5 × 10 12 cm −2 . This is not significantly different from the internal maximum electric field. Nevertheless, the reason for the large difference in the withstand voltage is that, although the floating potential metal wiring group 22 is omitted from the semiconductor device 3b, the electric field concentration is conspicuous at one point of the outermost edge of the base layer 12 in the steady state. On the other hand, in the steady state of the semiconductor device 3b, a state where the electric field concentration points are appropriately dispersed is maintained. When an electric field concentration is conspicuous at the outermost edge of the base layer 12, that is, the active region, avalanche breakdown tends to occur more easily than when the electric field concentration points are appropriately dispersed by the termination structure.
また、注入量３．８×１０１２ｃｍ－２では、半導体装置３ｂから内側から数えて１５個目以降の金属配線３４及び金属配線３５を省略したものの定常状態の半導体基板内部最大電界が、顕著に高くなっている。ここでは、強い電界集中はストッパフィールドプレート２１の最内縁の下部で生じている。ストッパフィールドプレートの最内縁の下部に際立った電界集中が生じた場合、高い耐圧が得られることがあるが、リーク電流の著しい増大や酸化膜のチャージアップによる特性変動を招いてしまう。したがって、注入量を必要以上に増やすことは、好ましくない。
In addition, when the injection amount is 3.8 × 10 12 cm −2 , the maximum electric field inside the semiconductor substrate in a steady state is remarkable although the fifteenth and subsequent metal wirings 34 and metal wirings 35 from the inside are omitted from the semiconductor device 3b. It is getting higher. Here, strong electric field concentration occurs in the lower part of the innermost edge of the stopper field plate 21. When a significant electric field concentration occurs in the lowermost portion of the innermost edge of the stopper field plate, a high breakdown voltage may be obtained, but a significant increase in leakage current and fluctuations in characteristics due to charge-up of the oxide film are caused. Therefore, it is not preferable to increase the injection amount more than necessary.
また、図１４及び図１５における、半導体装置３ｂから内側から数えて１５個目以降の金属配線３４及び金属配線３５を省略したものと、半導体装置３ｂとの比較から、ＬＮＦＬＲ６６の中腹から外側寄りの上部の金属配線を省略すると、定常状態の耐圧は少し増加するが、定常状態の半導体基板内部最大電界も少なからず増加していることが分かる。
14 and 15, the comparison between the semiconductor device 3b and the semiconductor device 3b in which the fifteenth metal wiring 34 and the metal wiring 35 are omitted from the semiconductor device 3b and the outer side of the LNFLR 66 is closer to the outer side. When the upper metal wiring is omitted, the withstand voltage in the steady state slightly increases, but the maximum electric field inside the semiconductor substrate in the steady state also increases.
一般的に、十分な高耐圧が得られるのであれば、半導体基板内部最大電界が低い方が終端構造として好ましい。しかし、実際には、設計面、製造面、コスト面など、様々な制約で理想的な終端構造を実現できないことがしばしばである。その場合は、実現しうる範囲内で、十分な高耐圧が得られ、できるだけ半導体基板内部最大電界が低い形態を選択すべきである。
Generally, if a sufficiently high breakdown voltage can be obtained, it is preferable as the termination structure that the semiconductor substrate internal maximum electric field is low. However, in practice, an ideal termination structure is often not realized due to various constraints such as design, manufacturing, and cost. In that case, it is necessary to select a configuration in which a sufficiently high breakdown voltage can be obtained and the maximum electric field inside the semiconductor substrate is as low as possible within a realizable range.
例えば、第１実施形態の半導体装置１と第２実施形態の半導体装置３ｂとを比較すると、半導体基板内部最大電界で見れば、ＶＬＤ層を含む半導体装置１の方が有利であるが、初期状態の耐圧、設計の容易さ、製造の容易さで見れば、ＬＮＦＬＲを含む半導体装置３ｂの方が有利である。このように、何を重視するかにより、最適な形態は異なってくる。
For example, when comparing the semiconductor device 1 of the first embodiment and the semiconductor device 3b of the second embodiment, the semiconductor device 1 including the VLD layer is more advantageous in terms of the maximum electric field inside the semiconductor substrate. The semiconductor device 3b including LNFLR is more advantageous in view of the withstand voltage, ease of design, and ease of manufacture. In this way, the optimum form varies depending on what is important.
＜第３実施形態＞
第１実施形態及び第２実施形態では、本発明を縦型デバイスに適用した形態について述べたが、本発明は基板表面に対して平行に電流を流す半導体装置、すなわち、横型デバイスにも適用できる。横型デバイスにおいても、３３００Ｖ以上の耐圧を実現するには、ＶＬＤ層のような電界緩和層が必要である。 <Third Embodiment>
In the first embodiment and the second embodiment, the embodiment in which the present invention is applied to a vertical device has been described. However, the present invention can also be applied to a semiconductor device in which a current flows parallel to the substrate surface, that is, a lateral device. . Even in a lateral device, an electric field relaxation layer such as a VLD layer is required to achieve a breakdown voltage of 3300 V or higher.
第１実施形態及び第２実施形態では、本発明を縦型デバイスに適用した形態について述べたが、本発明は基板表面に対して平行に電流を流す半導体装置、すなわち、横型デバイスにも適用できる。横型デバイスにおいても、３３００Ｖ以上の耐圧を実現するには、ＶＬＤ層のような電界緩和層が必要である。 <Third Embodiment>
In the first embodiment and the second embodiment, the embodiment in which the present invention is applied to a vertical device has been described. However, the present invention can also be applied to a semiconductor device in which a current flows parallel to the substrate surface, that is, a lateral device. . Even in a lateral device, an electric field relaxation layer such as a VLD layer is required to achieve a breakdown voltage of 3300 V or higher.
第１実施形態及び第２実施形態では、半絶縁膜が浮遊電位金属配線及び金属配線間の第１絶縁膜を覆う形態について述べたが、浮遊電位金属配線上の半絶縁膜は除去しても良い。また、半絶縁膜を第１絶縁膜の上面と金属配線の底面との間に配置、言い換えれば、半絶縁膜を第１絶縁膜の上部に形成してから半絶縁膜の上部に金属配線を形成しても良い。これらの形態でも、浮遊電位金属配線により半絶縁膜は短絡され、同様の効果が得られる。
In the first and second embodiments, the semi-insulating film covers the floating potential metal wiring and the first insulating film between the metal wirings. However, even if the semi-insulating film on the floating potential metal wiring is removed. good. Further, the semi-insulating film is disposed between the upper surface of the first insulating film and the bottom surface of the metal wiring. In other words, the semi-insulating film is formed on the first insulating film and then the metal wiring is formed on the semi-insulating film. It may be formed. Even in these forms, the semi-insulating film is short-circuited by the floating potential metal wiring, and the same effect can be obtained.
第１実施形態及び第２実施形態では、半導体基板及び各不純物層の導電型を、Ｐ型あるいはＮ型に特定した半導体装置について説明したが、これらの導電型がすべて逆であっても、同様の効果が得られる。
In the first and second embodiments, the semiconductor device in which the conductivity type of the semiconductor substrate and each impurity layer is specified as P-type or N-type has been described, but the same applies even if these conductivity types are all reversed. The effect is obtained.
また、以上で示した注入量及びアクセプタイオンの空間電荷量は、活性化率が１００％であり、かつ、イオン注入後の製造工程で消失しないことを前提にした値である。したがって、活性化率が低い場合や、熱酸化によってアクセプタイオンが吸い出される場合、又はエッチングによって表面が削られる場合などでは、最終的に半導体基板に存在する活性化したアクセプタイオン数に基づいて、注入量を調節すべきである。
Further, the implantation amount and the space charge amount of the acceptor ions shown above are values on the assumption that the activation rate is 100% and does not disappear in the manufacturing process after ion implantation. Therefore, when the activation rate is low, when acceptor ions are sucked out by thermal oxidation, or when the surface is shaved by etching, based on the number of activated acceptor ions finally existing in the semiconductor substrate, The injection volume should be adjusted.
また、半導体基板と絶縁膜との界面には、固定電荷、例えば界面電荷が存在する。この固定電荷が注入量に対して無視できない場合も注入量を調節すべきである。
Also, a fixed charge, for example, an interface charge exists at the interface between the semiconductor substrate and the insulating film. Even when this fixed charge cannot be ignored with respect to the injection amount, the injection amount should be adjusted.
また、第１実施形態及び第２実施形態では、ベース層が電界緩和層よりも深いものとして図示したが、ベース層は電界緩和層と同じ深さでも良いし、電界緩和層よりも浅くてもよい。また、ベース層は電界緩和層の最内側部と同一の深さ方向濃度プロファイルを持っても良い。
In the first and second embodiments, the base layer is illustrated as being deeper than the electric field relaxation layer, but the base layer may be the same depth as the electric field relaxation layer or shallower than the electric field relaxation layer. Good. The base layer may have the same depth direction concentration profile as the innermost portion of the electric field relaxation layer.
また、第１実施形態及び第２実施形態では、本発明を適用するデバイスをＰＩＮダイオードとしたが、本発明は、ショットキーバリアダイオード、ＪＢＳ（Ｊｕｎｃｔｉｏｎ Ｂａｒｒｉｅｒ Ｓｃｈｏｔｔｋｙ）ダイオード、ＭＰＳ（Ｍｅｒｇｅｄ ＰＩＮ Ｓｃｈｏｔｔｋｙ）ダイオードなどのダイオード、ＭＯＳＦＥＴ、ＩＧＢＴ、ＢＪＴ（Ｂｉｐｏｌａｒ Ｊｕｎｃｔｉｏｎ Ｔｒａｎｓｉｓｔｏｒ）などのトランジスタ、又はサイリスタといった、種々のデバイスの終端構造として適用しても、同様の効果が得られる。
In the first embodiment and the second embodiment, the device to which the present invention is applied is a PIN diode. However, the present invention is a Schottky barrier diode, a JBS (Junction Barrier Schottky) diode, and an MPS (Merged PIN Schottky) diode. The same effect can be obtained even when applied as a termination structure of various devices such as a diode such as a diode, a MOSFET, an IGBT, a transistor such as a BJT (Bipolar Junction Transistor), or a thyristor.
また、第１実施形態及び第２実施形態では、本発明を適用するデバイスをＰＩＮダイオードとし、活性領域の外縁部に配置される電極をベース層と同電位のアノード電極としたが、その他の電極であっても良い。例えば、デバイスをＩＧＢＴとしたときに、活性領域の外縁部に配置される電極をゲート電極にしても、同様の効果が得られる。ＩＧＢＴのオフ時にゲート―エミッタ間電圧が０であるとき、これは自明である。また、ＩＧＢＴのオフ時にゲートをエミッタに対して負バイアスにする場合でも、ゲート―エミッタ間電圧は高々－１５Ｖで、コレクタ―エミッタ間電圧に比べて無視できるレベルであり、実質的に問題にならない。
In the first and second embodiments, the device to which the present invention is applied is a PIN diode, and the electrode disposed at the outer edge of the active region is an anode electrode having the same potential as the base layer. It may be. For example, when the device is an IGBT, the same effect can be obtained even if the electrode disposed at the outer edge of the active region is a gate electrode. This is self-evident when the gate-emitter voltage is zero when the IGBT is off. Even when the gate is negatively biased with respect to the emitter when the IGBT is off, the gate-emitter voltage is at most -15 V, which is negligible compared to the collector-emitter voltage, and this is not substantially a problem. .
また、第１実施形態及び第２実施形態では、耐圧クラスを定格電圧で６５００Ｖとしたが、本発明は、どのような耐圧クラスに対しても適用できる。
In the first embodiment and the second embodiment, the withstand voltage class is set to 6500 V at the rated voltage, but the present invention can be applied to any withstand voltage class.
また、半導体基板１１の材料は、シリコンに限定されず、比較的広いバンドギャップを有するワイドバンドギャップ半導体であってもよい。ワイドバンドギャップ半導体としては、例えば、炭化珪素（ＳｉＣ）、窒化ガリウム（ＧａＮ）、酸化ガリウム（Ｇａ２Ｏ３）系材料、又はダイヤモンドを使用しても良い。
The material of the semiconductor substrate 11 is not limited to silicon, and may be a wide band gap semiconductor having a relatively wide band gap. As the wide band gap semiconductor, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ) -based material, or diamond may be used.
ワイドバンドギャップ半導体によって構成されるスイッチング素子及びダイオード素子は、高耐圧性を有し、許容電流密度も高いので、シリコンに比べて小型化が可能である。これら小型化されたスイッチングデバイス及び整流デバイスを用いることによって、これらのパワー半導体デバイスを組み込んだパワー半導体モジュールの小型化が可能となる。また、耐熱性も高いので、ヒートシンクの放熱フィンの小型化、及び水冷ではなく空冷による冷却も可能となり、パワー半導体モジュールの一層の小型化が可能となる。
Switching elements and diode elements composed of wide band gap semiconductors have a high withstand voltage and a high allowable current density, so that they can be made smaller than silicon. By using these miniaturized switching devices and rectifying devices, it is possible to reduce the size of power semiconductor modules incorporating these power semiconductor devices. In addition, since the heat resistance is high, it is possible to downsize the heat dissipating fins of the heat sink and to cool by air cooling instead of water cooling, and further reduce the size of the power semiconductor module.
また、注入に用いる不純物は、ホウ素（Ｂ）、窒素（Ｎ）、アルミニウム（Ａｌ）、リン（Ｐ）、ヒ素（Ａｓ）、インジウム（Ｉｎ）など、半導体材料の原子と置換して活性化するものであれば、どのようなものであっても良い。ただし、熱拡散を用いて電界緩和層を形成する場合は、拡散長が比較的大きく、かつ、拡散の制御性の高いものが望ましい。
Impurities used for implantation are activated by substituting atoms of a semiconductor material, such as boron (B), nitrogen (N), aluminum (Al), phosphorus (P), arsenic (As), and indium (In). Any thing can be used. However, when the electric field relaxation layer is formed using thermal diffusion, it is desirable that the diffusion length is relatively large and the diffusion controllability is high.
また、金属配線の材料は、アルミニウム、銅又は合金などの金属はもちろんのこと、不純物を多量に含んだポリシリコン又はインジウム酸化物に代表される酸化物半導体、その他の導電性セラミクス、又は、導電性ポリマーといった有機物など、半絶縁膜に比べて十分に高い導電性を持つものであればどのようなものであっても良い。
In addition, the material of the metal wiring is not only metals such as aluminum, copper or alloys, but also oxide semiconductors represented by polysilicon or indium oxide containing a large amount of impurities, other conductive ceramics, or conductive Any organic material such as a conductive polymer may be used as long as it has a sufficiently high conductivity compared to the semi-insulating film.
また、半絶縁膜の材料としては、半絶縁性ポリシリコン（ＳＩＰＯＳ）又は半絶縁性窒化シリコン（ＳｉｎＳｉＮ）のほか、キャリアの数を減らしたセラミクス又は有機ポリマーなど、半絶縁性を得られるものであればどのようなものでも良い。
In addition to semi-insulating polysilicon (SIPOS) or semi-insulating silicon nitride (SinSiN), the semi-insulating film material can be semi-insulating, such as ceramic or organic polymer with a reduced number of carriers. Anything is acceptable.
また、絶縁膜の材料としては、ＳｉＯ２（酸化シリコン）、Ｓｉ３Ｎ４（窒化シリコン）、ＴＥＯＳ（正珪酸四エチル）、低誘電率材料であるＳｉＯＦ（フッ素添加酸化シリコン）、又は、ＳｉＯＣ（炭素添加酸化シリコン）などのセラミックでも良いし、ポリイミドなどの樹脂又は有機ポリマーなど、絶縁性を得られるものであればどのようなものでも良い。
In addition, as a material of the insulating film, SiO 2 (silicon oxide), Si 3 N 4 (silicon nitride), TEOS (normal tetraethyl silicate), SiOF (fluorine-added silicon oxide) which is a low dielectric constant material, or SiOC A ceramic such as (carbon-added silicon oxide) may be used, or any resin such as a resin such as polyimide or an organic polymer may be used as long as the insulating property can be obtained.
上記実施形態では、各構成要素の材質、材料又は実施の条件などについても記載しているが、これらは例示であって記載したものに限られるものではない。
In the above embodiment, the material, material, or implementation condition of each component is also described, but these are examples and are not limited to those described.
なお、本発明は、その発明の範囲内において、各実施形態の自由な組合せ、又は各実施形態の任意の構成要素の変形、若しくは各実施形態において任意の構成要素の省略ができる。
In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or any component in each embodiment can be omitted.
１，１ａ，１ｂ，２，２ａ，２ｂ，３，３ａ，３ｂ，３ｃ，３ｄ，３ｅ，４ 半導体装置、１１ 半導体基板、１２ ベース層、１３，５９，６６，６９ 電界緩和層、１４ ストッパ層、１５ アノード電極、１６ ストッパ電極、１７ カソード層、１８ カソード電極、１９ 第１絶縁膜、２０ アノードフィールドプレート、２１ ストッパフィールドプレート、２２，２２ａ，２２ｂ，２２ｃ，２２ｄ，４０，４０ａ，４０ｂ 浮遊電位金属配線群、２３ 半絶縁膜、２４ 第２絶縁膜、３１～３５，３４ｂ，３４ｃ，３５ｂ，３５ｃ，４１～４５，４４ｂ，４５ｂ 金属配線、６０～６５，７０～７５ Ｐ型不純物層。
1, 1a, 1b, 2, 2a, 2b, 3, 3a, 3b, 3c, 3d, 3e, 4 semiconductor device, 11 semiconductor substrate, 12 base layer, 13, 59, 66, 69 electric field relaxation layer, 14 stopper layer , 15 anode electrode, 16 stopper electrode, 17 cathode layer, 18 cathode electrode, 19 first insulating film, 20 anode field plate, 21 stopper field plate, 22, 22a, 22b, 22c, 22d, 40, 40a, 40b floating potential Metal wiring group, 23 semi-insulating film, 24 second insulating film, 31-35, 34b, 34c, 35b, 35c, 41-45, 44b, 45b metal wiring, 60-65, 70-75 P-type impurity layer.
Claims (12)
- 第１導電型の半導体基板（１１）と、
前記半導体基板（１１）表面において部分的に形成された活性領域（１２）と、
前記半導体基板（１１）表面において、前記活性領域（１２）に接触し、かつ、前記活性領域（１２）を囲んで形成された第２導電型の不純物を含有する電界緩和層（１３）と、
前記活性領域（１２）の一部及び前記電界緩和層（１３）を覆って形成された絶縁膜（１９）と、
前記絶縁膜（１９）上の一部及び前記活性領域（１２）上に跨がって形成された第１電極（１５）と、
前記電界緩和層（１３）が形成された位置の少なくとも一部に対応する前記絶縁膜（１９）上の位置において形成され、かつ、浮遊電位を有する複数の金属層（３１～３５）とを備え、
複数の前記金属層（３１～３５）が、前記第１電極（１５）から離れる方向において互いに離間し、かつ、それぞれが前記第１電極（１５）を囲んで形成され、
前記絶縁膜（１９）上及び前記半導体基板（１１）上に跨がって形成され、かつ、複数の前記金属層（３１～３５）を囲んで配置された第２電極（１６）と、
前記第１電極（１５）から前記第２電極（１６）に亘る前記絶縁膜（１９）上に形成された半絶縁膜（２３）とを備え、
前記電界緩和層（１３）が、前記活性領域（１２）から離れる方向に延びて形成され、かつ、含有する第２導電型の不純物の空間電荷量が前記活性領域（１２）から離れるにつれて減少し、
各前記金属層（３１～３５）の前記第１電極（１５）から離れる方向の幅をＷ、
各前記金属層（３１～３５）の前記第２電極（１６）に近い側の端部である外縁端部と、前記第１電極（１５）に近づく方向において当該金属層（３１～３５）と隣り合って配置された前記第１電極（１５）又は他の前記金属層（３１～３５）の前記外縁端部との間の距離をＤとした場合、
各前記金属層（３１～３５）に関するＷ／Ｄが、前記第１電極（１５）から離れるにつれて小さくなる、
半導体装置。 A first conductivity type semiconductor substrate (11);
An active region (12) partially formed on the surface of the semiconductor substrate (11);
An electric field relaxation layer (13) containing an impurity of a second conductivity type formed on the surface of the semiconductor substrate (11) in contact with the active region (12) and surrounding the active region (12);
An insulating film (19) formed so as to cover a part of the active region (12) and the electric field relaxation layer (13);
A first electrode (15) formed across a part of the insulating film (19) and the active region (12);
A plurality of metal layers (31 to 35) formed at a position on the insulating film (19) corresponding to at least a part of the position where the electric field relaxation layer (13) is formed and having a floating potential. ,
A plurality of the metal layers (31 to 35) are separated from each other in a direction away from the first electrode (15), and each of the metal layers surrounds the first electrode (15);
A second electrode (16) formed over the insulating film (19) and the semiconductor substrate (11) and disposed so as to surround the plurality of metal layers (31 to 35);
A semi-insulating film (23) formed on the insulating film (19) from the first electrode (15) to the second electrode (16),
The electric field relaxation layer (13) is formed extending in a direction away from the active region (12), and the amount of space charge of the second conductivity type impurity contained decreases as the distance from the active region (12) increases. ,
The width of each of the metal layers (31 to 35) in the direction away from the first electrode (15) is W,
Each of the metal layers (31 to 35) has an outer edge that is an end closer to the second electrode (16), and the metal layers (31 to 35) in a direction approaching the first electrode (15). When the distance between the first electrode (15) arranged adjacent to each other and the outer edge end of the other metal layer (31 to 35) is D,
The W / D for each of the metal layers (31-35) decreases as the distance from the first electrode (15) increases.
Semiconductor device. - 各前記金属層（３１～３５）に関するＷが、前記第１電極（１５）から離れるにつれて小さくなる、
請求項１に記載の半導体装置。 W for each of the metal layers (31-35) decreases as the distance from the first electrode (15) increases.
The semiconductor device according to claim 1. - 各前記金属層（３１～３５）に関するＤが、前記第１電極（１５）からの距離に関わらず一定である、
請求項１又は請求項２に記載の半導体装置。 D for each of the metal layers (31-35) is constant regardless of the distance from the first electrode (15);
The semiconductor device according to claim 1 or 2. - 各前記金属層（３１～３５）に関するＤが、前記第１電極（１５）から離れるにつれて大きくなる、
請求項１又は請求項２に記載の半導体装置。 D for each of the metal layers (31-35) increases as the distance from the first electrode (15) increases.
The semiconductor device according to claim 1 or 2. - 各前記金属層（４１～４５）に関するＷが、前記第１電極（１５）からの距離に関わらず一定である、
請求項１に記載の半導体装置。 W for each of the metal layers (41 to 45) is constant regardless of the distance from the first electrode (15).
The semiconductor device according to claim 1. - 前記電界緩和層（５９、６６、６９）が、前記活性領域（１２）から離れる方向において互いに離間して形成された複数の層構造（６０～６５）からなる、
請求項１、請求項２及び請求項５のうちのいずれか１項に記載の半導体装置。 The electric field relaxation layer (59, 66, 69) is composed of a plurality of layer structures (60 to 65) formed apart from each other in a direction away from the active region (12).
The semiconductor device according to claim 1, claim 2, or claim 5. - 各前記金属層（３１～３５）が、各前記層構造（６１～６５）が形成された位置の少なくとも一部に対応する前記絶縁膜（１９）上の位置において形成されている、
請求項６に記載の半導体装置。 Each of the metal layers (31 to 35) is formed at a position on the insulating film (19) corresponding to at least a part of the position where each of the layer structures (61 to 65) is formed.
The semiconductor device according to claim 6. - 複数の前記層構造（６０～６５）のうち、最も前記活性領域（１２）に近い前記層構造（６０）が前記活性領域（１２）と接触して形成され、
当該層構造（６０）と、前記活性領域（１２）から離れる方向において当該層構造（６０）と隣り合って配置された他の前記層構造（６１）とが、繋がって形成されている、
請求項６に記載の半導体装置。 Among the plurality of layer structures (60 to 65), the layer structure (60) closest to the active region (12) is formed in contact with the active region (12),
The layer structure (60) and another layer structure (61) arranged adjacent to the layer structure (60) in a direction away from the active region (12) are connected to each other.
The semiconductor device according to claim 6. - 前記半導体基板（１１）が、ワイドバンドギャップ半導体からなる、
請求項１、請求項２及び請求項５のうちのいずれか１項に記載の半導体装置。 The semiconductor substrate (11) is made of a wide band gap semiconductor;
The semiconductor device according to claim 1, claim 2, or claim 5. - 前記電界緩和層（１３）の前記空間電荷量が、前記半導体基板（１１）の材料で決まるリサーフ条件の２倍以下である、
請求項１、請求項２及び請求項５のうちのいずれか１項に記載の半導体装置。 The space charge amount of the electric field relaxation layer (13) is not more than twice the resurf condition determined by the material of the semiconductor substrate (11).
The semiconductor device according to claim 1, claim 2, or claim 5. - 複数の前記層構造（６０～６５）の前記空間電荷量が、前記半導体基板（１１）の材料で決まるリサーフ条件の１．５倍以上３．５倍以下である、
請求項６に記載の半導体装置。 The space charge amount of the plurality of layer structures (60 to 65) is 1.5 to 3.5 times the resurf condition determined by the material of the semiconductor substrate (11).
The semiconductor device according to claim 6. - 各前記金属層（３１～３３、３４ｂ、３５ｂ）に関する前記Ｗ／Ｄのうち、前記第２電極（１６）に近い側の一部の各前記金属層（３４ｂ、３５ｂ）に関する前記Ｗ／Ｄが一定である、
請求項１、請求項２及び請求項５のうちのいずれか１項に記載の半導体装置。 Of the W / D for each of the metal layers (31 to 33, 34b, 35b), the W / D for a part of each of the metal layers (34b, 35b) on the side close to the second electrode (16) is Constant,
The semiconductor device according to claim 1, claim 2, or claim 5.
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| JP5921784B2 (en) | 2016-05-24 |
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