JP2013191597A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce ON-state current of an LDMOS transistor and improve ESD resistance of the LDMOS transistor.SOLUTION: A semiconductor device comprises: an N+ type embedded layer 2 formed on a surface of a P type semiconductor substrate 1; an N- type epitaxial layer 3 formed on the semiconductor substrate 1 including the N+ type embedded layer 2; a P type body layer 4 extending from a surface of the epitaxial layer 3 to the semiconductor substrate 1; an N type drift layer 5 formed on the surface of the epitaxial layer 3 in adjacent to the body layer 4; an N+ type source layer 6 and a P+ type contact layer 8 which are formed on a surface of the body layer 4; a gate electrode 9 which extends from an end of the source layer 5 to on the drift layer 5 via a gate insulation film and which is composed of polysilicon and the like; and an N+ type drain layer 7 formed on a surface of the drift layer at a distance from an end of the gate electrode 9. The embedded layer 2 extends from a region immediately below the drain layer 7 in a direction toward the body layer 4.

Description

  The present invention relates to a semiconductor device, and particularly relates to a semiconductor device including an LDMOS transistor having low on-resistance and excellent ESD resistance.

  Some semiconductor devices are composed of LDMOS transistors. DMOS is an abbreviation for Double-Diffused Metal Oxide Semiconductor. Of the DMOS transistors, the one in which the drain current flows laterally between the source and the drain on the surface of the semiconductor substrate is the LDMOS transistor. LD is an abbreviation for Laterally Diffused. LDMOS transistors are widely used in power supply circuits and driver circuits. Note that ESD is an abbreviation for Electro-Static Discharge.

  In a MOS transistor that forms a source layer and a drain layer containing a high-concentration impurity adjacent to the gate channel layer, a depletion layer from the drain layer to the lower semiconductor layer when a reverse bias is applied to the drain layer Increases depending on the impurity concentration of the semiconductor layer.

  However, the lateral depletion layer from the drain layer adjacent to the gate channel layer to the semiconductor layer serving as the gate channel layer cannot be sufficiently expanded due to the electric field of the gate electrode and the drain layer. Therefore, since the electric field strength in the lateral direction of the drain layer is much larger than that in the downward direction of the drain layer, dielectric breakdown occurs, and it is difficult to realize a high voltage MOS transistor.

  In order to solve such a problem, measures are taken to increase the thickness of the gate insulating film and weaken the electric field from the gate electrode. However, as the miniaturization progresses, the gate insulating film moves in the direction of thinning, and a so-called offset drain structure in which the high-concentration drain layer is separated from the gate has been adopted as a method for dealing with the demand for high breakdown voltage.

  The offset drain structure is a structure in which a high-concentration drain layer is separated from the gate channel layer. In this case, a so-called drift layer is formed between the gate channel layer and the high-concentration drain layer with impurities of the same type as the drain layer and having a lower concentration than the high-concentration drain layer, and the depletion layer extends laterally from the high-concentration drain layer. The electric field strength in the lateral direction is weakened to improve the breakdown voltage.

  FIG. 8 shows a cross-sectional structure of a conventional LDMOS transistor having an offset drain structure. An N− type epitaxial layer 53 is deposited on the P type semiconductor substrate 51 with an N + type buried layer 52 interposed therebetween. Alternatively, instead of depositing the N − type epitaxial layer 53, a deep N − type well layer may be formed from the surface of the P type semiconductor substrate 51.

On the surface of the N− type epitaxial layer 53, a P type body layer 54 and an N type drift layer 55 are formed adjacent to the P type body layer 54 in a predetermined region. N-type drift layer 55 functions as an electric field relaxation layer, usually the source of the LDMOS transistor - determines the drain breakdown voltage _{BV DS,} also constitute the main on-resistance when the LDMOS transistor is turned on.

  An N + type source layer 56 is formed on the surface of the P type body layer 54, and an N + type drain layer 57 is formed on the surface of the N type drift layer 55. A P + type contact layer 58 is formed on the surface of the P type body layer 54 in order to fix the potential of the P type body layer 54 to the potential of the source electrode S. Further, a gate electrode 59 made of polysilicon or the like extending from the end of the N + type source layer 54 to the P type body layer 54 and the N type drift layer 55 serving as a channel layer through a gate insulating film (not shown). Is formed.

  In addition, the source electrode S, N + type drain layer, which is made of aluminum (Al) or the like and is connected to the N + type source layer 56 through a contact hole formed in an interlayer insulating film (not shown) that covers the gate electrode 59 and the like. A drain electrode D connected to 57 and a gate electrode G connected to a gate electrode 59 made of polysilicon or the like are formed. Further, a multilayer wiring structure and a passivation film are formed thereon as necessary, thereby completing the LDMOS transistor.

  The breakdown voltage and the on-resistance of the LDMOS transistor having such an offset drain structure are in a trade-off relationship, and the impurity concentration of the N-type drift layer 55 is selected to an appropriate value to balance the breakdown voltage and the on-resistance. Patent Document 1 and Patent Document 2 describe methods for improving the on-resistance of an LDMOS transistor having an offset drain structure.

Japanese Patent Application Laid-Open No. 09-223793 JP-A-11-145462

  In Patent Document 1, in order to reduce the on-resistance, the impurity concentration of the impurity region serving as the drift layer is increased. In this case, in order to ensure a breakdown voltage, a channel forming impurity is formed so as to overlap with the channel region side of the impurity region serving as the drift layer, and the impurity concentration of the drift layer in that portion is lowered. Thereby, a breakdown voltage is ensured in the impurity region serving as the drift layer on the low concentration side, and a low on-resistance is realized in the high concentration impurity region on the opposite side.

  Patent Document 2 discloses a reduction in on-resistance of a P-type LDMOS transistor. The internal state of the device when the drain is grounded and a high voltage is applied to the source is examined by simulation to confirm that avalanche occurs on the surface of the P offset region. The content is that a field plate having the same potential as the source is formed in the P offset region in order to improve the breakdown voltage while maintaining the on-resistance while maintaining the impurity concentration in the P offset region.

  In either case, the on-resistance is reduced by increasing the impurity concentration of the drift layer to a required value. The resulting decrease in breakdown voltage reduces the impurity concentration on the channel region side of the impurity region serving as the drift layer, or arranges a high potential field plate above the P offset region to make the depletion layer easily spread in the P offset region. Equally solved.

  The challenge is to reduce the on-resistance, which is in a trade-off relationship with the breakdown voltage in relation to the impurity concentration of the drift layer, independently from the impurity concentration of the drift layer, and also to realize an LDMOS transistor with high ESD tolerance. .

  The semiconductor device of the present invention is a semiconductor device comprising an LDMOS transistor, and is formed on the semiconductor substrate including the second conductivity type buried layer formed on the surface of the first conductivity type semiconductor substrate and the buried layer. An epitaxial layer of the second conductivity type formed, a body layer of the first conductivity type formed extending from the surface of the epitaxial layer to the semiconductor substrate, and adjacent to the body layer on the surface of the epitaxial layer A formed second conductivity type drift layer, a second conductivity type source layer and a first conductivity type contact layer formed on the surface of the body layer, and an end portion of the source layer through a gate insulating film A drain electrode of a second conductivity type formed on the surface of the drift layer and spaced from the end of the gate electrode opposite to the source layer. Comprising a layer, wherein the buried layer is equal to or extending into the body layer direction from a region immediately below the drain layer.

  The semiconductor device according to the present invention is characterized in that the body layer extends to a region immediately below the source layer.

  The semiconductor device according to the present invention is characterized in that a breakdown voltage of a PN junction constituted by the body layer and the buried layer is lower than a breakdown voltage of a PN junction constituted by the body layer and the drift layer.

  The semiconductor device of the present invention is characterized in that the semiconductor device is a thermal head driver.

  According to the semiconductor device of the present invention, an LDMOS transistor having low on-resistance and excellent ESD resistance can be realized.

2A and 2B are a schematic plan view and a cross-sectional view illustrating a drain region and a source region of the LDMOS transistor according to the first embodiment of the present invention and a part of a region therebetween. FIG. 3 is a cross-sectional view showing an ON-current flow path in the operating state of the LDMOS transistor of the first embodiment of the present invention. It is sectional drawing which shows the flow path of the discharge current when the big positive surge voltage is applied to the drain electrode D of the LDMOS transistor of the 1st form of this invention. 4 is a graph comparing the drain-source breakdown voltage and the on-resistance of the first embodiment product and the conventional product. 5 is a cross-sectional view of an LDMOS transistor according to a second embodiment of the present invention, and a diagram showing a flow path of a discharge current when a large positive surge voltage is applied to a drain electrode D. FIG. It is sectional drawing which shows the flow path of the on-current in the operation state of the LDMOS transistor of the 2nd Embodiment of this invention. It is a graph which compares the snap back characteristic of the 2nd Embodiment product of this invention, and the conventional product, and the maximum temperature of a heat generation place. It is sectional drawing of the conventional LDMOS transistor, and a figure which shows the flow path of the ON current in the operation state. FIG. 6 is a cross-sectional view of a conventional LDMOS transistor and a flow path of a discharge current when a large positive surge voltage is applied to the drain electrode D.

[First embodiment]
The on-resistance of the LDMOS transistor of this embodiment will be described below based on FIGS. 1, 2, and 4 and compared with the conventional product shown in FIG. In the present invention, the vicinity of the N + -type drain layer 7 region, the vicinity of the N + -type source layer 6 region, and the region therebetween are constituent elements, so that only the relevant region is enlarged and displayed in each drawing.

FIG. 1A is a plan view showing a part of the N + type source layer 6 and the N + type drain layer 7 of the LDMOS transistor of this embodiment. The second embodiment, the conventional product, is a similar plan view.
FIG. 1B is a cross-sectional view taken along line AA in FIG. Each electrode made of aluminum (Al) or the like is displayed only as the source electrode S, the gate electrode G, and the drain electrode D in FIG. 1B, and the description is omitted in FIG. Description of a gate insulating film, an interlayer insulating film, and the like is also omitted.

  In the LDMOS transistor of this embodiment, as shown in FIG. 1B, the N + type buried layer 2 is formed on the surface of the P type semiconductor substrate 1 and the N− type is formed thereon as in the conventional product shown in FIG. Epitaxial layer 3 is deposited, and P-type body layer 4 is formed in a predetermined region on the surface of N − -type epitaxial layer 3, and N-type drift layer 5 is formed adjacent to P-type body layer 4.

  The surface of the N type drift layer 5 is spaced from an end portion of a gate electrode 9 to be described later, and an N + type drain layer 7 is formed on the surface of the P type body layer 4, and the N + type source layer 6 and the N + type source layer 4 and source A P + type contact layer 8 connected by the electrode S is formed. A gate electrode 9 made of polysilicon or the like extending on the channel region of the P-type body layer 4 and on the N-type drift layer 5 is formed from the end of the N + type source layer 6 through a gate insulating film (not shown). The

  In the configuration of the LDMOS transistor of this embodiment, the N− type epitaxial layer 3 is thinner than the configuration of the conventional product shown in FIG. 8, and the N + type buried layer 2 is formed in the N + type drain layer 7. The P-type body layer 4 is in contact with the P-type semiconductor substrate 1 and the P-type body layer 4 is in contact with the P-type semiconductor substrate 1. The film thickness of the N− type epitaxial layer 3 is 1 μm in the present embodiment and 3.5 μm in the conventional product.

FIG. 8 shows a case where the operating voltage v _P is applied to the drain electrode D of the conventional LDMOS transistor, the source electrode S and the P-type semiconductor substrate 1 are grounded, and a voltage higher than the threshold voltage is applied to the gate electrode G. The flow path of the on-current flowing through the LDMOS transistor is shown.

  Generally, depending on the manufacturing method, the N-type drift layer 5 has a high impurity concentration on the surface side. Therefore, the depletion layer 10 is difficult to expand on the surface side of the N-type drift layer 5, and the electric field strength on the surface side is larger than the inside. Therefore, in the conventional product in which the N− type epitaxial layer 3 is thick, the on-current (1) flowing through the surface region of the N-type drift layer 5 having a large electric field strength becomes the main current of the on-current as shown in FIG. Together with the on-current (2) flowing through the other N-type drift layer 5, most of the on-current is constituted.

  The on-current (3) flowing through the high-resistance N− type epitaxial layer 3 is small, and the on-current flowing through the low-resistance N + type buried layer 2 is also a thick N− type epitaxial layer having a high resistance. Since it is necessary to go through 3, it becomes very few.

2 shows an operation voltage + v _P applied to the drain electrode D of the LDMOS transistor of the present embodiment, the source electrode S and the P-type semiconductor substrate 1 are grounded, and a voltage higher than the threshold voltage is applied to the gate electrode G. The on-current flow path is shown. The electron current flowing from the source electrode S passes through the N-type inverted channel layer and is accelerated by the electric field of the depletion layer 10 extending between the P-type body layer 4 and the N-type drift layer 5 and passes through the N-type drift layer 4 in the N + type. It flows toward the drain layer 7.

  Unlike the conventional product shown in FIG. 8, in this embodiment, the N− type epitaxial layer 3 having a high resistance is thin. Further, the depletion layer 10 hardly spreads on the N + type buried layer 2 side in the vicinity of the interface between the N + type buried layer 2 and the N− type epitaxial layer 3 having a high impurity concentration, and the electric field strength in the same region is increased. Therefore, the on-current flowing into the N− type epitaxial layer 3 is attracted to a high electric field strength on the N + type buried layer 2 and easily flows into the low resistance N + type buried layer 2 to form the on current (4). .

  The on-current of the LDMOS transistor of the present embodiment has a low contribution rate due to the presence of the thick N− type epitaxial layer 3 between the conventional products, and the N + type drain layer 7 via the low resistance N + type buried layer 2. It is increased from the conventional product by an on-current (4) toward. Since the contribution of the on-current (4) is large, the total on-current greatly increases. That is, the greatest feature of the present embodiment is that the flow path of the discharge current can be expanded and the on-resistance can be reduced.

4, the on-resistance of the LDMOS transistor and a conventional LDMOS transistor of this embodiment drain - shown in relation to source breakdown voltage _{V DS.} Drain - regardless of the value of the source breakdown voltage V _DS, the on-resistance of the present embodiment can be observed that less than the on-resistance of the conventional product. It is also recognized that the difference tends to increase when the drain-source breakdown voltage _VDS is higher. Drain - that source breakdown voltage V _DS is high means that the low impurity concentration of the N-type drift layer 5, because the on-resistance becomes higher.

The LDMOS transistor of this embodiment is for a thermal head driver used in a thermal printer, and the maximum voltage of 12V is standard. The on-resistance of the conventional product at a voltage of 17 V in consideration of the withstand voltage margin is 17.8 mΩ · mm ² as shown in FIG. On the other hand, in this embodiment, it is 11.8 mΩ · mm ² .

Therefore, by adding the parallel resistance X to the conventional on-resistance of 17.8 mΩ · mm ² , the on-resistance of the present embodiment is reduced to 11.8 mΩ · mm ² . Since the parallel resistance X in this case can be calculated to be about 35 mΩ · mm ² , the flow path of the on-current (4) of the LDMOS transistor of this embodiment is formed with a resistance of about 35 mΩ · mm ^2. Become.

That is, the on-resistance of 35 mΩ · mm ² with respect to the on-current (4) flowing through the N− type epitaxial layer 3 → N + type buried layer 2 → N− type epitaxial layer 3 → N + type drain layer 7 is the conventional on-resistance 17. 8 mΩ · mm ² is connected in parallel, and the overall on-resistance is reduced to 11.8 mΩ · mm ² . This is a feature of the LDMOS transistor of this embodiment.

  As the distance from the end portion of the P-type body layer 4 to the end portion of the N + type buried layer 2 is shorter, the on-current (4) flowing into the N + type buried layer 2 increases, and the overall on-resistance can be reduced. Therefore, the distance from the end of the P-type body layer 4 to the end of the N + type buried layer 2 is preferably as short as the withstand voltage allows.

[Second Embodiment]
The ESD resistance of the LDMOS transistor of this embodiment will be described below with reference to FIGS. FIG. 5 is a cross-sectional view of the LDMOS transistor of this embodiment. The difference from the first embodiment is that the N + buried layer 2 extends from below the N + type drain layer 7 to the bottom surface of the P type body layer 4. Other configurations are the same as those of the first embodiment.

When a large positive charge voltage + _VP is applied to the drain electrode D of the LDMOS transistor, avalanche breakdown occurs at any of the reverse-biased PN junctions, and a large discharge current flows. The feature of this embodiment is that the discharge current flow path is different from the conventional product, so that the heat generation amount of the current flow path is small and the heat dissipation amount is large. That is.

This will be described with reference to FIG. First, a large positive surge voltage + _VP is applied to the drain electrode D of the LDMOS transistor. At this time, in the PN junction composed of the P-type body layer 4, the N-type drift layer 5, and the N − -type epitaxial layer 3, the direction mainly toward the N-type drift layer and the N − -type epitaxial layer 3 having a low impurity concentration. As a result, the depletion layer 10 expands.

  At the same time, in the PN junction composed of the N + type buried layer 2 and the P type body layer 4, the depletion layer 10 extends toward the P type body layer 4 in the low impurity concentration region. The electric field strength is maximized in the region where the expansion of the depletion layer 10 is the smallest, the PN junction in the region is avalanche breakdown, and the discharge current flows toward the ground line.

The withstand voltage of the PN junction constituted by the N + type buried layer 2 and the P type body layer 4 is set lower than the withstand voltage of the PN junction constituted by the P type body layer 4 and the N type drift layer 5, and a large positive charge voltage + V _P Is applied to the drain electrode D of the LDMOS transistor, the PN junction formed by the N + type buried layer 2 and the P type body layer 4 causes avalanche breakdown.

When a large positive charge voltage + V _P is applied to the drain electrode D of the LDMOS transistor, as shown in FIG. 5, formed at the very breakdown voltage and set N + -type buried layer 2 and the P-type body layer 4 lower PN junction causes avalanche breakdown to generate a large number of hole ○ + and electron ○ − pairs. As a result, electrons flow out from the positive high potential N + type drain layer 7 to the drain electrode via the N + buried layer 2, and holes flow out to the source electrode S through the P + type contact layer 8 at ground potential. .

  Further, the holes flow out from the P + type contact layer 8 having the ground potential to the source electrode S, and part of the holes terminate around the N + type source layer 6. The potential of the P-type body layer 4 rises due to the holes gathered near the N + -type source layer 6 or the holes flowing toward the P + -type contact layer 8, and is configured by the N + -type source layer 6 and the P-type body layer 4. The PN junction is biased forward.

As a result, the first parasitic NPN bipolar transistor having the N + type source layer 6 as an emitter, the P type body layer 4 as a base, and the N + type buried layer 2 as a collector is turned on, and a so-called snapback phenomenon occurs. As shown by the solid line in FIG. 7A, when the drain-source voltage V _DS rises to the snapback voltage V _S1 , the first parasitic NPN bipolar transistor is turned on to cause a snapback phenomenon.

When the snapback phenomenon occurs, the drain-source voltage _VDS suddenly decreases to the holding voltage _VH1 . The holding voltage V _H1 corresponds to the collector-emitter breakdown voltage V _CER of the first parasitic NPN bipolar transistor. Thereafter, the discharge current (1) shown in FIG. 5 increases with the slope shown in FIG. 7 (A), which is determined by the collector resistance and the like between the emitter and collector of the first parasitic NPN bipolar transistor.

As the discharge current (1) increases, the temperature of the discharge current path rises due to Joule heat, and as shown in the figure, the LDMOS transistor is thermally destroyed and the drain-source voltage _VDS decreases. The discharge current increases. In this embodiment, since the discharge current (1) flows through the low resistance N + type impurity layer 2, the amount of heat generated is small. Further, since the discharge current (1) flows through the N + type buried layer 2 adjacent to the P type semiconductor substrate 1 serving as a heat absorber, the Joule heat generated in the N + type buried layer 2 is applied to the P type semiconductor substrate 1. It is easy to dissipate heat.

  Therefore, the temperature rise region of the LDMOS transistor due to the Joule heat of the discharge current (1) is not spot-like but widens upward from the N + type buried layer 2. As a result, the temperature rise of the LDMOS transistor is kept low.

  In FIG. 5, in addition to the main discharge current (1), the discharge current (2), the discharge current (3), and the discharge current (4) are also displayed. This is because the potential of the P-type body layer 4 in the vicinity of the N + -type source layer 6 becomes higher, so that the N + -type source layer 6 serves as an emitter, the P-type body layer 4 serves as a base, and the N-type drift layer 5 serves as a collector. It shows that the parasitic NPN bipolar transistor is also turned on. However, since the resistance of the current flow path with respect to the discharge currents (2) to (4) is large, the contribution ratio to the total discharge current is smaller than that of the discharge current (1).

On the other hand, the flow path of the discharge current when a large positive surge voltage + _VP is applied to the drain electrode D of the conventional LDMOS transistor will be described with reference to FIG. When a large positive surge voltage + _VP is applied to the drain electrode, the depletion layer 100 is formed from the PN junction formed between the P-type body layer 54, the N-type drift layer 55, and the N-type epitaxial layer 53, It extends toward the N− type epitaxial layer 53.

  The impurity concentration of the N type drift layer 55 is higher than the impurity concentration of the N − type epitaxial layer 53, and as described above, it is particularly high in the surface region. Therefore, the width of the depletion layer 100 is narrowed in the surface region, and the electric field strength is also increased. Unlike the present embodiment, the P-type body layer 54 and the N + type buried layer 52 are not in direct contact with each other, and a thick, low-concentration N− type epitaxial layer 53 is interposed therebetween. Accordingly, the electric field strength at the bottom surface of the P-type body layer 54 does not become larger than the surface of the N-type drift layer 55.

  As a result, avalanche breakdown occurs near the surface of the N-type drift layer 55, and a large number of hole and electron pairs are generated. As described above, electrons flow toward the N + type drain layer 57 having a positive potential via the N type drift layer 55, and holes flow toward the N + type source layer 56 having a ground potential. Some holes flow out to the source electrode S at the ground potential via the P + type contact layer 58.

  The holes collected around the N + type source layer 56 or the holes flowing toward the P + type contact layer 58 cause the potential of the P type body layer 54 to be higher than the ground potential of the N + type source layer 56. A parasitic NPN bipolar transistor having the source layer 56 as an emitter, the P-type body layer 54 as a base, and the N-type drift layer 55 as a collector is turned on, and a discharge current (1) and a slight discharge current (2) are applied to the drain electrode D. leak.

  Since the N− type epitaxial layer 53 is thick, almost no discharge current flows through the N + type buried layer 52. Therefore, as compared with the LDMOS transistor of this embodiment, the discharge current flow path is narrow, the resistance to the discharge current is increased, and the heat generation amount is increased. In addition, since most of the components flowing through the surface region of the N-type drift layer 55 that is separated from the P-type semiconductor substrate 51 are present, the amount of heat released from the heat generating portion to the P-type semiconductor substrate 51 is small. Accordingly, since the heat generation region is also a spot-like narrow region in the surface region of the N-type drift layer 55, the temperature rise in that region also increases.

FIG. 7A shows a state of a discharge current when a large positive surge voltage + _VP is applied to the drain electrode D of the conventional LDMOS transistor by a dotted line. Since the drain-source breakdown voltage BV _{DS (} not shown) is high, the snapback voltage V _S2 is also high. The discharge current after V _DS snaps back to the holding voltage V _H2 increases with a gentler slope than the present embodiment with respect to the drain-source voltage V _DS . That is, the resistance of the discharge current channel is larger than that of the present embodiment.

FIG. 7B is a graph showing the relationship between the discharge current and the maximum temperature of the heat generating portion of the LDMOS transistor. In the entire discharge current region, the maximum temperature of the heat generating portion of this embodiment is lower than that of the conventional product. For example, the discharge current reaching a temperature of 1400 K, which is an indication of the thermal breakdown of the LDMOS transistor, is as small as 4.5 A in the LDMOS transistor of the present embodiment and 3.5 A in the conventional LDMOS transistor. That, LDMOS transistor of the present embodiment, since the conventional not thermally broken even if a large discharge current flows than, it is possible to discharge the static electricity due to a large surge voltage + V _P promptly ground line.

  This is because the resistance to the discharge current of this embodiment is smaller than the resistance to the discharge current of the conventional product, and the discharge current of this embodiment flows in a region close to the P-type semiconductor substrate 1 serving as a heat absorber. Thus, this coincides with the above-described result that the conventional product flows in the surface region of the N-type drift layer 5 spaced from the P-type semiconductor substrate 1.

In the present embodiment, the operating voltage + v _P is applied to the drain electrode D, the source electrode S and the P-type semiconductor substrate 1 are set to the ground potential, and a voltage higher than the threshold voltage is applied to the gate electrode G to perform the on operation. The on-resistance in this case can be made lower than that of the conventional product. As shown in FIG. 6, in the same manner as in the first embodiment, in addition to the discharge current (1) and the discharge current (2) flowing from the N + type source layer 6 into the N type drift layer 5 via the channel layer, This is because a discharge current (3) that flows into the N + type buried layer 2 through the thin N− type epitaxial layer 3 and flows out to the N + type drain layer 7 flows.

FIG. 3 shows a flow path of a discharge current when a large positive surge voltage + _VP is applied to the drain electrode D of the LDMOS transistor of the first embodiment. As in the case of the conventional product, an avalanche breakdown occurs in the surface region of the N-type drift layer 5, and a parasitic NPN bipolar transistor having the N + type source layer 6 as an emitter, the P-type body layer 4 as a base, and the N-type drift layer 5 as an emitter Turns on.

  However, when compared with the conventional product, the N− type epitaxial layer 3 is thin, and the P type body layer 4 side is located between the N− type epitaxial layer 3 below the N + type drain layer 7 and the P type semiconductor substrate 1. The difference is that a low-resistance N + -type buried layer 2 extending toward the surface exists. In addition, the electric field strength is increased in the N− type epitaxial layer 3 region in the vicinity of the interface with the N + type buried layer 2 as described above.

  Accordingly, in addition to the discharge current (1) and the discharge current (2) flowing in the N-type drift layer 5 and in the vicinity of the surface, the discharge current passes through the thin N− type epitaxial layer 3 and passes through the low resistance N + buried layer. A discharge current (3) flowing through the N + type drain layer 7 via 2 is applied. For this reason, the LDMOS transistor of the first embodiment also suppresses an increase in the temperature of the heat generating part as compared with the conventional product, and the ESD resistance is improved.

1 P-type semiconductor substrate 2 N + type buried layer 3 N− type epitaxial layer 4 P type body layer 5 N type drift layer 6 N + type source layer
7 N + type drain layer 8 P + type contact layer 9 Polysilicon gate electrode 10 Depletion layer S Source electrode G Gate electrode
D drain electrode 51 P type semiconductor substrate 52 N + type buried layer
53 N-type epitaxial layer 54 P-type body layer
55 N-type drift layer 56 N + type source layer 57 N + type drain layer
58 P + type contact layer 59 Polysilicon gate electrode 100 Depletion layer

Claims (4)

A semiconductor device comprising an LDMOS transistor,
A second conductivity type buried layer formed on the surface of the first conductivity type semiconductor substrate;
A second conductivity type epitaxial layer formed on the semiconductor substrate including the buried layer;
A body layer of a first conductivity type formed extending from the surface of the epitaxial layer to the semiconductor substrate;
A drift layer of a second conductivity type formed on the surface of the epitaxial layer adjacent to the body layer;
A second conductivity type source layer and a first conductivity type contact layer formed on the surface of the body layer;
A gate electrode extending from the end of the source layer to the drift layer through a gate insulating film;
A drain layer of a second conductivity type formed on the surface of the drift layer and spaced from the end of the gate electrode opposite to the source layer, wherein the buried layer is a region immediately below the drain layer Extending in the body layer direction.   The semiconductor device according to claim 1, wherein the body layer extends to a region immediately below the source layer.   The semiconductor device according to claim 2, wherein a breakdown voltage of a PN junction configured by the body layer and the buried layer is lower than a breakdown voltage of a PN junction configured by the body layer and the drift layer.   The semiconductor device according to claim 1, wherein the semiconductor device is a thermal head driver.

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