JP5567437B2 - Semiconductor device and integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor device that has improved resistance to electrostatic discharge (ESD) by preventing current concentration at the drain end, and an integrated circuit using the semiconductor device.

  Generally, a power IC is composed of both a low voltage device and a high withstand voltage device, and is widely used in the automobile industry, for example. The environment of an on-vehicle semiconductor device is harsh. This requires a relatively high level of protection against electrostatic discharge and other types of electrical transients. As one method for protecting a semiconductor element from electrostatic discharge, it is conceivable to insert a resistance element between the semiconductor element and the output pin and limit the current accompanying the electrostatic discharge with the resistance element. However, an LDMOS (Lateral Double Diffusion Metal-Oxide-Semiconductor) FET (for example, see Patent Document 1), which is a high breakdown voltage device, is required to have both low on-resistance and high breakdown voltage. Therefore, if a resistance element is inserted, the low on-resistance characteristic of the LDMOSFET viewed from the pad is impaired, which is not a good idea.

  When electrostatic discharge occurs in a conventional LDMOSFET, a strong electric field is applied to the drain end, avalanche breakdown occurs, and electrons and holes are generated. The hole current flows through the base of the parasitic bipolar transistor in the LDMOSFET and activates the parasitic hyperpolar transistor. At this time, the collector current is concentrated locally at the drain end, and thermal runaway occurs in that region, leading to breakdown, and there is a problem that sufficient electrostatic discharge resistance cannot be obtained. Even if the parasitic bipolar transistor remains inactive, the high avalanche current locally increases the electric field strength at the drain end, and thermal runaway occurs at that location.

JP 2001-352070 A

  As described above, in an LDMOSFET, when electrostatic discharge occurs, a strong electric field is applied to the drain end, avalanche breakdown occurs, a parasitic bipolar transistor is activated, local current concentration occurs at the drain end, and in that region Thermal runaway occurred and there was a problem that led to destruction.

  An object of the present invention is to provide a semiconductor device with improved resistance to electrostatic discharge by preventing local current concentration at the drain end and an integrated circuit using the same.

  In order to solve the above-described problem, a semiconductor device according to a first aspect of the present invention includes a first conductivity type low concentration region and a first conductivity type well region so that each of the first conductivity type high concentration buried region is in contact with the upper surface. Are disposed adjacent to each other, a second conductivity type low concentration region is disposed on an upper surface of the first conductivity type low concentration region, and a first first conductivity type high concentration region to which a drain electrode is connected is defined as the first conductivity type. A second first conductivity type high-concentration region, which is disposed on the upper surface of the conductivity type well region, and to which a source electrode is connected, is disposed on the upper surface of the second conductivity type low concentration region, and the first first conductivity type An element isolation region made of an insulating material is disposed from the high concentration region toward at least the upper surface of the second conductivity type low concentration region, and a gate oxide film is interposed on the upper surface of the portion located on the upper surface of the second conductivity type low concentration region. The gate electrode is disposed, and the second conductivity type low concentration region In a semiconductor device having a MOS structure in which a channel is formed below the gate electrode, the first conductivity type well region below the first first conductivity type high concentration region is formed by the first first well type region. A first conductivity type high concentration buried contact region connecting the first conductivity type high concentration region and the first conductivity type high concentration buried region is replaced with a part of the second first conductivity type high concentration region. The second conductive type high concentration region is connected to the source electrode, and the second first conductive type high concentration region and the second conductive type high concentration region are connected to the source electrode. The channels are arranged in the width direction of the channel.

  According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the second first-conductivity-type high-concentration regions and the second-conductivity-type high-concentration regions are alternately adjacent to each other and the width of the channel is plural. It is characterized by being aligned in the direction.

  According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the length of the second first conductive type high concentration region in the width direction of the channel is the second conductive type high concentration region. Longer than the length of the channel in the width direction.

  According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the distance in the length direction of the channel of the first conductive type well region is defined as the first conductive type low concentration. It is characterized by being larger than the depth of the region.

According to a fifth aspect of the present invention, there is provided an integrated circuit, wherein the semiconductor device according to any one of the first to third aspects is a first semiconductor device in which the source electrode is connected to the gate electrode, and the drain electrode and the An integrated circuit in which a source electrode is connected to a drain electrode and a source electrode of a second semiconductor device to be protected, the second semiconductor device including the first first conductivity of the first semiconductor device. The structure is the same as that of the first semiconductor device except that the lower portion of the high-concentration type region remains the first conductive type well region, and the second high-conductivity type high-concentration region has a width direction of the channel. The length is shorter than the length in the width direction of the channel of the second first conductivity type high concentration region of the first semiconductor device.

  According to the present invention, the first conductivity type well region below the first first conductivity type high concentration region is connected to the first conductivity type high concentration region and the first conductivity type high concentration buried region. The first conductivity type high concentration buried contact region is replaced, a part of the second first conductivity type high concentration region is replaced with the second conductivity type high concentration region, and the second conductivity type high concentration region is used as the source electrode. Since the second first-conductivity-type high-concentration region and the second-conductivity-type high-concentration region are arranged in the width direction of the channel, a high level due to electrostatic discharge is generated between the drain electrode and the source electrode. When a voltage is applied, the vertical transistor is activated in addition to the parasitic transistor, so that the current flowing through the parasitic transistor is suppressed, local current concentration at the drain end is prevented, and resistance to electrostatic discharge is improved. There are advantages to doing.

(A) is a top view of the semiconductor device of the Example of this invention, (b) is sectional drawing. (A) is a top view of a high voltage | pressure-resistant device, (b) is sectional drawing. It is a circuit diagram of the integrated circuit which connected the semiconductor device as a protection element in parallel to the high voltage | pressure-resistant device. It is a characteristic view of the turn-on voltage of the NPN transistor with respect to the change of length B1, B2 of the 2nd N type high concentration area | region in the channel width direction. It is a turn-on characteristic diagram of an NPN transistor of LDMOS.

  In the present embodiment, the first conductivity type is described as N-type and the second conductivity type is defined as P-type. However, the first conductivity type is defined as P-type and the second conductivity type is defined as N-type. Applicable. The “concentration” described below means the concentration of impurities. The semiconductor device of this embodiment will be described briefly. The width of the element isolation region, that is, the width of the N-type well region is set to be longer than the depth of the N-type low concentration region by epitaxial growth, and the second N type high concentration. The vertical NPN transistor Q1 is formed by the region (emitter), the P-type low concentration region (base), and the N-type high concentration buried region (collector), and the N-type high concentration buried region is an N-type high concentration contact region. To be connected to the first N-type high concentration region. Further, a plurality of second N-type high concentration regions and P-type high concentration regions connected to the source electrode are alternately arranged adjacent to each other in the channel width direction, and the hole current generated by the avalanche breakdown is generated in the P-type high concentration region. When flowing, it passes through the P-type low concentration region below the second N-type high concentration region. As a result, the internal base resistance of the vertical NPN transistor Q1 can be increased, and the turn-on voltage of the NPN transistor is lowered by turning on with a little current. Further, the internal base resistance can be adjusted by changing the length of the second N-type high concentration region in the channel width direction, and the turn-on voltage of the NPN transistor can be adjusted.

  A semiconductor device according to an embodiment of the present invention will be described below. The semiconductor device 100 of the present invention has a strong resistance to electrostatic discharge when used alone as a normal transistor, but when this is used as a protective element, as shown in FIG. A drain and a source are commonly connected to the device 200. At this time, the source electrode of the semiconductor device 100 is commonly connected to the gate electrode. In the integrated circuit of FIG. 3, when electrostatic discharge occurs, a high voltage is applied between the drain and source of the high voltage device 200. In this embodiment, a current due to this high voltage is applied between the drain and source of the semiconductor device 100. By flowing, the high voltage device 200 is protected. FIG. 1 is a sectional view of a semiconductor device 100 having an LDMOS structure, and FIG. 2 is a sectional view of a high breakdown voltage device 200 having a similar LDMOS structure.

1A is a plan view of the semiconductor device 100, and FIG. 1B is a bb cross-sectional view of FIG. The semiconductor device 100 includes a silicon P-type semiconductor substrate 101, an N-type high-concentration buried region 102 that functions as a collector, an N-type low-concentration region 103 grown epitaxially, and lateral diffusion in the N-type low-concentration region 103. An N-type well region 104 formed, an N-type high concentration buried contact region 105 formed by lateral diffusion in the N-type well region 104, and a P-type low concentration region 106 as a body (base) for forming a channel. A first N-type high concentration region 107 as a drain region disposed on the upper surface of the N-type high concentration buried contact region 105, and a second as a source region disposed on the upper surface of the P-type low concentration region 106. The N-type high-concentration region 108 and the second N-type high-concentration region 108 are at the same level, that is, the N-type From the first N-type high concentration region 107 and the P-type high concentration region 109, which are alternately arranged in the channel width direction (vertical direction in FIG. 1A) alternately with the concentration region 108 and are continuous with the P-type low concentration region 106. An element isolation region 110 extending in the direction of the second N-type high concentration region 108 and continuing to the gate insulating film on the upper surface (right end in FIG. 1) of the P-type high concentration region 106, a polysilicon gate electrode 111, and interlayer insulation A film 112, a drain electrode 113D connected to the first N-type high concentration region 107, a source electrode 113S connected to the second N-type high concentration region 108, and a protective film 114 covering the whole. The R 1 is an internal base resistance of the second N-type high concentration region 108. The channel of the MOS structure is formed at a position immediately below the gate electrode 111 in the P-type low concentration region 106.

  Further, a vertical NPN transistor Q1 having a P-type low concentration region 106 as a base, a second N-type high concentration region 108 as an emitter, and an N-type high concentration buried region 102 as a collector is included in a part of a device having a MOS structure. Then, a parasitic NPN transistor Q2 is formed which has the P-type low concentration region 106 as a base, the second N-type high concentration region 108 as an emitter, and the N-type high concentration buried contact region 105 as a collector.

The P-type semiconductor substrate 101 is a P-type (hole) conduction region formed by introducing a P-type impurity such as boron, and the substrate concentration is about 5.0 × 10 ¹⁴ / cm ⁻³ . The N-type high-concentration buried region 102 is an N-type (electron) conduction region formed by introducing an N-type impurity such as phosphorus, and has a concentration of 1.0 × 10 ¹⁶ / cm ^{−3 to} 7.0 × 10. It is about ¹⁸ / cm ⁻³ . The N-type low concentration region 103 is an N-type (electron) conduction region deposited by epitaxial growth, and the concentration is about 3.0 × 10 ¹⁵ / cm ⁻³ . The N-type well region 104 is an N-type (electron) conduction region formed by introducing an N-type impurity such as phosphorus, and the concentration is 5.0 × 10 ¹⁵ / cm ^{−3 to} 6.0 × 10 ¹⁶ /. It is about cm ⁻³ . The N-type high-concentration buried contact region 105 is an N-type (electron) conduction region formed by introducing an N-type impurity such as phosphorus, and has a concentration of 1.0 × 10 ¹⁸ / cm ^{−3 to} 1.5 ×. It is about 10 ¹⁹ / cm ⁻³ . The first and second N-type high concentration regions 107 and 108 are N-type (electron) conduction regions formed by introducing N-type impurities such as phosphorus, and the concentration is 5.0 × 10 ¹⁸ / cm ^−. It is about ^{3 to} 5.0 × 10 ¹⁹ / cm ⁻³ . The P-type low concentration region 106 is a P-type (hole) conduction region formed by introducing a P-type impurity such as boron, and has a concentration of 5.0 × 10 ¹⁶ / cm ^{−3 to} 2.0 × 10. It is about ¹⁷ / cm ⁻³ . The P-type high concentration region 109 is a P-type (hole) conductive region formed by introducing a P-type impurity such as boron, and the concentration is 5.0 × 10 ¹⁸ / cm ^{−3 to} 5.0 × 10. It is about ¹⁹ / cm ⁻³ . The N-type high concentration region 107 and the N-type high concentration buried region 102 are electrically connected through the N-type high concentration buried contact region 105.

Next, the operation of the semiconductor device 100 of FIG. 1 will be described. When electrostatic discharge occurs, a high voltage is applied between the drain and source. At this time, avalanche breakdown occurs at the drain end, that is, at the gate side (point X) of the element isolation region 110 of the drain. Holes generated by avalanche breakdown flow into the P-type high concentration region 109 through the P-type low concentration region 106. As a result, the vertical NPN transistor Q1 is turned on, and from the drain electrode 113D through the N-type high concentration region 107, the N-type high concentration buried contact region 105, and the N-type high concentration buried region 102, An electrostatic discharge current flows toward the source electrode 113S via Q1. The parasitic NPN transistor Q2 is also turned on, and the electrostatic discharge current is passed through the N-type high concentration region 107, the N-type well region 104, and the N-type high concentration buried region 102, and then through the parasitic NPN transistor Q2. It flows toward the source electrode 113S.

  As a result, when the vertical NPN transistor Q1 is turned on, a discharge current bypass path is formed, and local current concentration in the N-type high concentration region 107 is prevented compared to when only the parasitic NPN transistor Q2 is turned on. Thus, the resistance of the semiconductor device 100 itself to electrostatic discharge is improved.

2A is a plan view of the high voltage device 200, and FIG. 2B is a bb cross-sectional view of FIG. The high breakdown voltage device 200 includes a silicon P-type semiconductor substrate 201, an N-type high-concentration buried region 202 functioning as a collector, an N-type low-concentration region 203 grown epitaxially, and lateral diffusion in the N-type low-concentration region 203. The N-type well region 204 formed in step S1, the P-type low-concentration region 206 as a body (base) for forming a channel, and the first N-type high region as a drain region disposed on the N-type well region 204. Concentration region 207, second N-type high concentration region 208 as a source region disposed on the upper surface of P-type low concentration region 206, and the same level as second N-type high concentration region 208, that is, P-type On the upper surface of the low-concentration region 206, the N-type high-concentration region 208 is alternately arranged in the channel width direction (vertical direction in FIG. A concentration region 209 and an element extending in the direction from the first N-type high concentration region 207 to the second N-type high concentration region 208 and continuous with the gate insulating film on the upper surface (right end in FIG. 2) of the P-type high concentration region 206 The isolation region 210, the polysilicon gate electrode 211, the interlayer insulating film 212, the drain electrode 213D connected to the first N-type high concentration region 207, and the second N-type high concentration region 208 are connected. A source electrode 213S and a protective film 214 covering the whole are formed. R 2 is an internal base resistance of the second N-type high concentration region 208. The channel of the MOS structure is formed at a position immediately below the gate electrode 211 in the P-type low concentration region 206. Here, a parasitic NPN transistor Q3 having a P-type low concentration region 206 as a base, a second N-type high concentration region 208 as an emitter, and a second N-type high concentration region 207 as a collector is included in the MOS structure. Is formed.

The P-type semiconductor sealing plate 201 is a P-type (hole) conduction region formed by introducing a P-type impurity such as boron, and the substrate concentration is about 5.0 × 10 ¹⁴ / cm ⁻³ . The N-type high concentration buried region 202 is an N-type (electron) conduction region formed by introducing an N-type impurity such as phosphorus, and has a concentration of 1.0 × 10 ¹⁶ / cm ^{−3 to} 7.0 × 10. It is about ¹⁸ / cm ⁻³ . The N-type low concentration region 203 is an N-type (electron) conduction region deposited by epitaxial growth of silicon, and the concentration is about 3.0 × 10 ¹⁵ / cm ⁻³ . The N-type well region 204 is an N-type (electron) conduction region formed by introducing an N-type impurity such as phosphorus, and the passivity is 5.0 × 10 ¹⁵ / cm ⁻³ 3 to 6.0 × 10 It is about ¹⁶ / cm ⁻³ . The P-type low concentration region 206 is a P-type (hole) conduction region formed by introducing a P-type impurity such as boron, and the concentration is 5.0 × 10 ¹⁶ / cm ^{−3 to} 2.0 × 10. It is about ¹⁷ / cm ⁻³ . The first and second N-type high concentration regions 207 and 208 are N-type (electron) conductive regions formed by introducing N-type impurities such as phosphorus, and the concentration is 5.0 × 10 ¹⁸ / cm ^−. It is about ^{3 to} 5.0 × 10 ¹⁹ / cm ⁻³ . The P-type high concentration region 209 is a P-type (hole) conduction region formed by introducing a P-type impurity such as boron, and has a concentration of 5.0 × 10 ¹⁸ / cm ^{−3 to} 5.0 × 10. It is about ¹⁹ / cm ⁻³ .

The parasitic NPN transistor Q3 is an NPN transistor having the P-type low concentration region 206 as a base, the second N-type high concentration region 208 as an emitter, and the first N-type high concentration region 207 as a collector. This parasitic NPN transistor Q3 is turned on when electrostatic discharge occurs.

More specifically, when electrostatic discharge occurs in the high-voltage device 200, a strong electric field is applied to the drain end, that is, the gate side (point Y) of the drain element isolation region 210, avalanche breakdown occurs, and electrons and holes are generated. Occur. The holes generated by the avalanche breakdown flow into the P-type high concentration region 209 through the P-type low concentration region 206. As a result, the parasitic NPN transistor Q3 is turned on, local current concentration occurs in the first N-type high concentration region 207 on the drain side, and the high breakdown voltage device 200 is destroyed.

  Therefore, in this embodiment, the turn-on voltage Vt of the NPN transistors Q1 and Q2 of the semiconductor device 100 as a protection element connected in parallel to the high breakdown voltage device 200 is made lower than that of the NPN transistor Q3 of the high breakdown voltage device 200. Thus, it is ensured that the NPN transistors Q1 and Q2 of the semiconductor device 100 operate first at the time of electrostatic discharge. As can be seen from FIGS. 1 and 2, the element isolation regions 110 and 210 on the drain side have different channel length directions (lateral directions in FIGS. 1 and 2B), but the drain side of the semiconductor device 100 The structure is the same as the drain side structure of the high voltage device 200.

  Therefore, the length B1 in the channel width direction of the second N-type high concentration region 108 of the semiconductor device 100 is set longer than the length B2 in the channel width direction of the second N-type high concentration region 208 of the high breakdown voltage device 200. For example, during the electrostatic discharge, the NPN transistors Q1 and Q2 of the semiconductor device 100 can be turned on before the NPN transistor Q3 of the high breakdown voltage device 200. The reason is as follows.

  FIG. 4 is a graph showing the relationship between the lengths B1 and B2 in the channel width direction of the second N-type high concentration regions 108 and 208 and the turn-on voltage Vt of the NPN transistor. FIG. 5 is a turn-on characteristic diagram of the NPN transistor. In the semiconductor device 100 and the high breakdown voltage device 200 of this embodiment, the lengths A1 and A2 of the P-type high concentration regions 109 and 209 in the channel width direction are set to the lengths of the second N-type high concentration regions 108 and 208 in the channel width direction. By setting it shorter than the lengths B1 and B, the occupied area of the P-type high concentration regions 109 and 209 is reduced, and the second N-type high concentration regions 108 and 208 are alternately arranged with a predetermined width. The values of internal base resistors R1, R2 of NPN transistors Q1, Q2, Q3 are increased. The turn-on voltage Vt of NPN transistors Q1, Q2, Q3 decreases as the values of internal base resistors R1, R2 increase.

  Accordingly, the length B1 of the first N-type high concentration region 107 of the semiconductor device 100 in the channel width direction is longer than the length B2 of the first N-type high concentration region of the high breakdown voltage device 200 in the 207 channel width direction. By doing (B1> B2), the turn-on voltage Vt of the NPN transistors Q1 and Q2 of the semiconductor device 100 can be made lower than the turn-on voltage Vt of the NPN transistor Q3 of the high breakdown voltage device 200. The NPN transistors Q1 and Q2 are turned on before the NPN transistor Q3 of the high breakdown voltage device 200, and the breakdown of the high breakdown voltage device 200 can be prevented. At this time, since the vertical NPN transistor Q1 is also conductive in the semiconductor device 100, the current passing through the NPN transistor Q2 is reduced as compared with the case where only the NPN transistor Q2 is conductive, and the first NPN on the drain side is reduced. No local current concentration occurs in the mold high concentration region 107.

  In the embodiment described above, the P-type semiconductor substrates 101 and 201 can be replaced with an SOI (Silicon On Insulator) structure substrate in which an insulating film is formed on the upper surface of a P-type or N-type semiconductor substrate.

Claims (5)

The first conductivity type low concentration region and the first conductivity type well region are disposed adjacent to each other so as to be in contact with the upper surface of the first conductivity type high concentration buried region, and are disposed on the upper surface of the first conductivity type low concentration region. A second conductivity type low concentration region is disposed, a first first conductivity type high concentration region to which a drain electrode is connected is disposed on an upper surface of the first conductivity type well region, and a second electrode to which a source electrode is connected A first conductivity type high concentration region is disposed on an upper surface of the second conductivity type low concentration region and insulated from the first first conductivity type high concentration region to at least an upper surface of the second conductivity type low concentration region. An element isolation region made of a material is disposed, a gate electrode is disposed on an upper surface of a portion located on the upper surface of the second conductivity type low concentration region via a gate oxide film, and the element of the second conductivity type low concentration region is MOS in which a channel is formed below the gate electrode In the semiconductor device of the concrete,
The first conductivity type well region under the first first conductivity type high concentration region is connected to the first first conductivity type high concentration region and the first conductivity type high concentration buried region. A conductive type high concentration buried contact region is replaced, a part of the second first conductive type high concentration region is replaced with a second conductive type high concentration region, and the second conductive type high concentration region is the source electrode. To be connected to
The second first conductivity type high concentration region and the second conductivity type high concentration region are arranged in the width direction of the channel.
A semiconductor device. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the second first-conductivity-type high-concentration region and the second-conductivity-type high-concentration region are alternately adjacent and arranged in the width direction of the channel. The semiconductor device according to claim 1 or 2,
The length of the channel in the width direction of the second first conductivity type high concentration region is longer than the length of the second conductivity type high concentration region in the width direction of the channel. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device according to claim 1, wherein a distance of the first conductivity type well region in a length direction of the channel is made larger than a depth of the first conductivity type low concentration region. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a first semiconductor device in which the source electrode is connected to the gate electrode, and the drain electrode and the source electrode are protected as a second target. An integrated circuit connected to a drain electrode and a source electrode of a semiconductor device,
The second semiconductor device is the same as the first semiconductor device except that the lower portion of the first first conductivity type high concentration region of the first semiconductor device remains the first conductivity type well region. the structure, and said length second width direction of the channel of the first conductivity type high concentration region, the width direction of the channel of the said second of the first conductivity type high concentration region of the first semiconductor device Shorter than the length of
An integrated circuit characterized by that.

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