JP5339789B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having an insulated gate portion.

  A semiconductor device having an insulated gate portion is used, for example, in an in-vehicle power converter. A high ESD (Electro-Static Discharge) resistance is desired for the characteristics of this type of semiconductor device.

FIG. 17 schematically shows a cross-sectional view of a horizontal semiconductor device 400. The semiconductor device 400 includes a p-type body region 421, an n ⁺ -type source region 423, a p ⁺ -type body contact region 424, an n-type drift region 425, and an n ⁺ -type drain region 426. Yes. Each of these semiconductor regions 421, 423, 424, 425, 426 is provided in the surface layer portion of the semiconductor layer 420. The semiconductor region 427 is the remaining part of each of the semiconductor regions 421, 423, 424, 425, 426 in the semiconductor layer 420. The source region 423 and the body contact region 424 are electrically connected to the source electrode. The drain region 426 is electrically connected to the drain electrode.

  A broken line in FIG. 440 indicates a range where the trench type insulated gate portion exists in the depth direction of the drawing. The trench type insulated gate portion 440 extends from the surface of the semiconductor layer 420 toward the deep portion, and faces the body region 421 in the semiconductor layer 220. The reference numeral 434 is a field oxide film, and the reference numeral 432 is a field plate electrode.

JP 2004-214611 A

  In the semiconductor device 400, when a high surge voltage such as ESD is applied to the drain region 426, a depletion layer is formed in the drift region 425, an impact ionization phenomenon occurs, and electrons and holes are generated in the semiconductor layer 420. To do. The impact ionization phenomenon often occurs in the vicinity of the edge center 440a on the right side surface of the trench-type insulated gate portion 440. Electrons generated by the impact ionization phenomenon flow to the drain region 426 through the drift region 425. Holes generated by the impact ionization phenomenon flow to the body contact region 424 through the body region 421.

  When a hole current flows in the body region 421, a voltage drop is caused by the resistance component of the body region 421. When the potential at the source region end 423a rises due to this voltage drop and exceeds the forward voltage between the base and emitter of the parasitic npn transistor composed of the source region 423, the body region 421 and the drift region 425, the parasitic npn The transistor is turned on.

  When the parasitic npn transistor is turned on, electrons are injected from the source region 423. The injected electrons flow to the drain region 426 through the drift region 425. As a result, current concentrates locally, and a snapback phenomenon occurs in which the resistance changes from positive to negative in drain voltage-drain current characteristics. When the snapback phenomenon occurs, heat is generated locally and the semiconductor device 400 may be thermally destroyed.

The drain current value when the snapback phenomenon occurs is substantially proportional to the ESD tolerance. For this reason, in this type of semiconductor device, it is desired to increase the drain current value when the snapback phenomenon occurs. For example, in the semiconductor device 410 of Patent Document 1 shown in FIG. 18, the body contact region 424 is formed between the source region 423 and the drift region 425. In the semiconductor device 410, holes generated by the impact ionization phenomenon can flow directly to the body contact region 424. For this reason, the potential just below the source region 423 is unlikely to rise, and the parasitic npn transistor is difficult to turn on. Patent document 1 discloses one technique for improving ESD tolerance.
An object of the present invention is to provide a semiconductor device with improved ESD tolerance based on a technical idea different from the conventional one.

  The semiconductor device disclosed in this specification is characterized in that an insulating region is provided in part between a source region and a body region. When the insulating region is provided, the base-emitter junction area of the parasitic transistor is reduced, and the current value after the parasitic transistor is turned on can be reduced. Thereby, the drain current value when the snapback phenomenon occurs can be increased, and the ESD tolerance can be improved.

The technology disclosed in this specification can be applied to both a horizontal semiconductor device and a vertical semiconductor device. The semiconductor device disclosed in this specification includes a drain electrode, a drain region, a drift region, a body region, a source region, a body contact region, an insulating gate portion, and an insulating region. The drain region is in contact with the drain electrode and includes a first conductivity type impurity. The drift region is in contact with the drain region and includes a first conductivity type impurity. The impurity concentration in the drift region is lower than the impurity concentration in the drain region. The body region is in contact with the drift region, and is separated from the drain electrode by the drift region and the drain region. The body region includes a second conductivity type impurity. The source region is in contact with the body region and is separated from the drift region by the body region. The source region includes a first conductivity type impurity. The body contact region is in contact with the body region and includes a second conductivity type impurity. The impurity concentration in the body contact region is higher than the impurity concentration in the body region. The source electrode is in contact with the source region and the body contact region. The insulated gate portion faces the body region that separates the drift region and the source region. The insulated gate portion includes a trench type, a planar type, or other forms. The insulating region is provided in a part between the source region and the body region, and is in contact with both the source region and the body region . According to this embodiment, the junction area between the base and the emitter of the parasitic transistor is reduced. For this reason, the current value after the parasitic transistor is turned on becomes small. As a result, the drain current value when the snapback phenomenon occurs can be increased, and the ESD tolerance can be improved.

In the above semiconductor device, the source region and the body contact region are preferably adjacent to each other. The source region and the body region are preferably in contact with each other between the insulating region and the body contact region. In this case, the insulating region is provided on the side away from the body contact region between the source region and the body region.
According to this embodiment, it is possible to forcibly prevent the part where the most parasitic transistor is likely to operate. For this reason, it becomes difficult to turn on the parasitic transistor, and the drain current value when the snapback phenomenon occurs can be further increased.

The semiconductor device disclosed in this specification can be embodied as a horizontal semiconductor device. In this case, the drain region, the drift region, the body region, the source region, and the body contact region are provided in the surface layer portion of the semiconductor layer. The body contact region is preferably disposed between the drain region and the source region. The insulated gate part is preferably a trench type insulated gate part formed in the surface layer part of the semiconductor layer.
According to this configuration, holes generated by the impact ionization phenomenon near the center of the edge of the side surface of the trench type gate portion flow into the body region, but the insulating region is provided immediately below the source region away from the body contact region. Therefore, the parasitic transistor in this region does not turn on. The parasitic transistor is not turned on until the potential on the side surface of the source region where the insulating region is not provided exceeds the forward voltage between the base and the emitter of the parasitic transistor. As a result, the drain current value when the snapback phenomenon occurs can be further increased.

  According to the technique disclosed in this specification, by reducing the current value after the parasitic transistor is turned on, the drain current value when the snapback phenomenon occurs can be increased, and the ESD tolerance is improved. A semiconductor device can be provided.

  Hereinafter, embodiments will be described in detail with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected about the common component, The description is abbreviate | omitted. In the following embodiments, silicon is used as the semiconductor material, but other semiconductor materials may be used. For example, a semiconductor material such as silicon carbide, gallium arsenide, or gallium nitride may be used. The technology according to the following embodiments is also useful for other semiconductor materials. Even if the conductivity type (n-type, p-type) of each semiconductor region is reversed, the technology according to the following embodiments can be reproduced. The technology according to the following embodiments is also useful for semiconductor devices other than MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

  FIG. 1 schematically shows a main part plan view of a horizontal semiconductor device 10. FIG. 2 schematically shows a longitudinal sectional view corresponding to the line II-II in FIG. FIG. 3 schematically shows a longitudinal sectional view corresponding to the line III-III in FIG. 1, the field oxide film 34 and the field plate electrode 32 on the semiconductor layer 20 shown in FIGS. 2 and 3 are omitted for convenience.

  The semiconductor device 10 is formed using a silicon single crystal semiconductor layer 20. The semiconductor layer 20 is an active layer of an SOI substrate, for example. Therefore, in the cross-sectional views of FIGS. 2 and 3, only the semiconductor layer 20 is illustrated, and the other semiconductor substrate and the buried insulating layer constituting the SOI substrate are omitted.

The semiconductor device 10 includes a p-type body region 21, an n ⁺ -type source region 23, a p ⁺ -type body contact region 24, an n-type drift region 25, and an n ⁺ -type drain region 26. Yes. Each of these semiconductor regions 21, 23, 24, 25, 26 is provided in the surface layer portion of the semiconductor layer 20. The semiconductor region 27 is the remaining part of each of the semiconductor regions 21, 23, 24, 25, 26 in the semiconductor layer 20.

  The source region 23 and the body contact region 24 are adjacent to each other. Source region 23 is separated from drift region 25 by body region 21. The source region 23 is formed deeper than the body contact region 24. The body contact region 24 is provided between the source region 23 and the drain region 26. The body contact region 24 has a higher impurity concentration than the body region 21. The source region 23 and the body contact region 24 are in contact with the source electrode. The source region 23 and the body contact region 24 are formed in the surface layer portion of the semiconductor layer 20 using, for example, an ion implantation technique.

  The body region 21 and the drift region 25 are adjacent to each other. The body region 21 is separated from the drain electrode by the drift region 25 and the drain region 26. Body region 21 is formed shallower than drift region 25. The impurity concentration of the drift region 25 changes in the horizontal direction and increases from the body region 21 side toward the drain region 26 side. The body region 21 and the drift region 25 can be formed in the surface layer portion of the semiconductor layer 20 using, for example, an ion implantation technique.

  The drain region 26 is separated from the body region 21 by the drift region 25. The impurity concentration of the drain region 26 is higher than the impurity concentration of the drift region 25. The drain region 26 is formed deeper than the body region 21 and has substantially the same depth as the trench type insulated gate portion 40. The drain region 26 is in contact with the drain electrode. The drain region 26 can be formed by, for example, forming a deep trench and then introducing impurities into the inner wall of the trench. Alternatively, the drain region 26 can also be formed by filling a deep trench with doped polysilicon.

  The semiconductor device 10 further includes a trench type insulated gate portion 40. The trench type insulated gate portion 40 extends from the surface of the semiconductor layer 20 toward the deep portion, and is formed deeper than the body region 21. The trench-type insulated gate portion 40 includes a silicon oxide gate insulating film 44 and a polysilicon gate electrode 42 covered with the gate insulating film 44. In FIG. 2, a range where the trench type insulated gate portion 40 exists in the depth direction of the drawing is indicated by a broken line. As shown in FIG. 2, the trench type insulated gate portion 40 faces the body region 21 that separates the source region 23 and the drift region 25. 34 is a field oxide film, and 32 is a field plate electrode. The field plate electrode 32 is electrically connected to the gate electrode 42 of the trench type insulated gate portion 40.

  The semiconductor device 10 further includes an insulating region 22 of silicon oxide. The insulating region 22 is provided between the source region 23 and the body region 21 and is in contact with part of the bottom surface of the source region 23. The insulating region 22 is provided between the source region 23 and the body region 21 on the side away from the body contact region 24. Thereby, the source region 23 and the body region 21 are in contact with each other between the insulating region 22 and the body contact region 24.

  FIG. 4 shows the relationship between the drain voltage (VD) and the drain current (ID) of the semiconductor device 10. As a comparative example, the result when the insulating region 22 is not provided is also shown. As shown in FIG. 4, in the semiconductor device 10 of this embodiment, the drain current value when the snapback phenomenon occurs is 138A. On the other hand, in the comparative example in which the insulating region 22 is not provided, the drain current value when the snapback phenomenon occurs is 28A. By providing the insulating region 22, the drain current value when the snapback phenomenon occurs increases about five times.

  Here, the snapback phenomenon will be described. The snapback phenomenon refers to a phenomenon in which the drain voltage (VD) decreases when a drain current (ID) further flows after reaching a breakdown voltage in the source-drain breakdown voltage characteristics. That is, the snapback phenomenon refers to a phenomenon in which a point showing negative resistance appears. It is known that there is a substantially proportional relationship between the drain current value and the ESD tolerance when this snapback phenomenon occurs. Therefore, this semiconductor device with a high drain current value also has a high ESD tolerance. For this reason, it is estimated from the result of FIG. 4 that the ESD tolerance of the semiconductor device 10 of this embodiment is about five times that of the comparative example.

  Next, the function and effect of the semiconductor device 10 will be described with reference to FIG. FIG. 5A is a comparative example in which the insulating region 22 is not provided. FIG. 5B shows this embodiment in which an insulating region 22 is provided.

  In FIG. 5A, a voltage drop due to holes is large at a portion 23a immediately below the source region 23 farthest from the body contact region 24, and the parasitic npn transistor is easily turned on. Further, since the junction area of the body region 21 which is the base of the parasitic transistor and the source region 23 which is the emitter is large, a large current flows after the parasitic transistor is turned on. When the parasitic transistor is turned on, a current is concentrated locally and a negative resistance is generated. Therefore, as shown in FIG. 5A, in the case where the parasitic transistor is easily turned on, the drain current when the snapback phenomenon occurs becomes small.

  On the other hand, in the semiconductor device 10 of the present embodiment shown in FIG. 5B, the parasitic transistor does not operate at the portion 23a where the parasitic transistor is most likely to be turned on because the insulating region 22 is provided. Since the distance between the parasitic transistor at the first operating location 23b and the body contact region 24 is short, more hole current is required to turn on the parasitic transistor. Further, since the junction area between the parasitic transistor base and the emitter is small, the current value after turning on becomes small. As described above, since it becomes difficult for the parasitic transistor to be turned on, it becomes difficult for negative resistance to occur, and thus the drain current value when the snapback phenomenon occurs increases.

  FIG. 6 shows drain current (ID), hole current (ISh) of holes generated by the impact ionization phenomenon, and electrons injected from the source region 23 after the parasitic npn transistor is turned on in the semiconductor device 10 of this embodiment. The electron current (ITre) is shown. FIG. 7 shows the result of the comparative example.

  As shown in FIG. 6, in the semiconductor device 10 of the present embodiment, the hole current ISh when the electron current ITre starts flowing is 33A. On the other hand, as shown in FIG. 7, in the comparative example, the hole current ISh when the electron current ITre begins to flow is 20A. From this result, in the semiconductor device 10 of the present embodiment, since the insulating region 22 is provided, the distance between the parasitic npn transistor and the body contact region 24 is shortened, so that the parasitic transistor is turned on. It can be seen that a lot of hole current is required.

  FIG. 8 shows the relationship between the base voltage (VB) of the parasitic npn transistor and the collector current (IC). The collector current (IC) corresponds to the amount of electrons injected from the source region 23. FIG. 8 shows the results when 1 V is applied to the drain region 26, 0 V is applied to the source region 23, and 0 to 0.9 V is applied to the body contact region 24.

  As shown in FIG. 8, in the semiconductor device 10 of this embodiment, when the base voltage (VB) is 0.8 V, the collector current (IC) is reduced to 1/3 that of the comparative example. From this result, it can be seen that, in the semiconductor device 10 of this embodiment, the provision of the insulating region 22 reduces the amount of electrons injected from the source region 23 after the parasitic npn transistor is turned on.

  As described above, in the semiconductor device 10 of the present embodiment, (1) the position of the parasitic npn transistor is brought close to the body contact region 24 to make it difficult to turn on the parasitic npn transistor, and (2) the parasitic npn transistor. The extremely high ESD tolerance is realized by the two actions of reducing the junction area between the base and emitter of the transistor and reducing the electron current that flows after the transistor is turned on.

(Manufacturing method of the semiconductor device 10)
A method for manufacturing the semiconductor device 10 will be described with reference to FIGS. In addition, description is abbreviate | omitted regarding the process which can apply a prior art. Hereinafter, only the step of forming the insulating region 22 will be described.

First, as shown in FIG. 9, a body region 21, a body contact region 24, a drift region 25, and a drain region 26 are formed in the surface layer portion of the semiconductor layer 20 using an ion implantation technique.
Next, as shown in FIG. 10, a trench 52 is formed in the surface layer portion of the semiconductor layer 20 by using a lithography technique and an etching technique. The trench 52 is formed in the body region 21.
Next, as shown in FIG. 11, the insulating region 22 is formed on the bottom surface of the trench 52 using a thermal oxidation technique.
Next, as shown in FIG. 12, the source region 23 is formed by filling silicon by using an epitaxial growth technique.
Next, as shown in FIG. 13, the source region 23 is thermally diffused using a heat treatment technique.

(Modification)
14 to 16 illustrate other semiconductor devices using the technology disclosed in this specification. In addition, the same code | symbol is attached | subjected about the component which is common in the semiconductor device 10, and the description is abbreviate | omitted.

  The semiconductor device 100 illustrated in FIG. 14 is different from the semiconductor device 10 in that the insulating region 122 extends to the back surface of the semiconductor layer 20. For example, when a trench is formed from the surface of the semiconductor layer 20 and the trench is filled with an insulator, the semiconductor device 100 is obtained. The semiconductor device 100 realizes the technology disclosed in this specification by a different manufacturing method, and the operation and effect thereof are the same as those of the semiconductor device 10.

A semiconductor device 200 shown in FIG. 15 is different from the semiconductor device 10 in that the positions of the source region 223 and the body contact region 224 are reversed. The insulating region 222 is in contact with the side surface of the source region 223 on the drain region 26 side. Insulating region 222 is provided on the side away from body contact region 224, and source region 223 and body region 21 are in contact between insulating region 222 and body contact region 224.
Also in the semiconductor device 200 shown in FIG. 15, the parasitic npn transistor that is most easily turned on does not operate. Further, since the junction area between the base and the emitter of the parasitic transistor is reduced, the amount of electrons injected from the source region 223 after being turned on is reduced. As a result, the drain current value when the snapback phenomenon occurs can be increased.

  As shown in FIG. 16, the technique disclosed in this specification can also be applied to a vertical semiconductor device 300. The semiconductor device 300 is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a drain electrode, a drain region 326, a drift region 325, a body region 321, a source region 323, a body contact region 324, and a trench type insulated gate portion 340. It has. The trench type insulated gate part 340 includes a gate insulating film 344 and a trench gate electrode 342 covered with the gate insulating film 344. These structures are general vertical MOSFETs.

  The semiconductor device 300 further includes an insulating region 322. The insulating region 322 is in contact with part of the bottom surface of the source region 323. The insulating region 322 is separated from the side surface of the trench type insulated gate portion 340. Thus, a channel region connecting the source region 323 and the drift region 325 is secured in the body region 321.

  Also in the vertical semiconductor device 300 shown in FIG. 16, since the junction area between the base and the emitter of the parasitic npn transistor is reduced, the amount of electrons injected from the source region 323 after being turned on is reduced. Thereby, the drain current value when the snapback phenomenon occurs can be increased.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The principal part top view of the semiconductor device of this embodiment is shown typically. The longitudinal cross-sectional view corresponding to the II-II line of FIG. 1 is shown typically. FIG. 2 schematically shows a longitudinal sectional view corresponding to the line III-III in FIG. 1. The relationship between the drain voltage of this embodiment and a comparative example and drain current is shown. (A) The position of the parasitic npn transistor of the comparative example is shown. (B) The position of the parasitic npn transistor of this embodiment is shown. The relationship between the hole current and electron current of this embodiment and the drain voltage is shown. The relationship between the hole current and electron current of the comparative example and the drain voltage is shown. The relationship of the base voltage and collector current of this embodiment and a comparative example is shown. One process of the manufacturing method of the semiconductor device of this embodiment is shown. One process of the manufacturing method of the semiconductor device of this embodiment is shown. One process of the manufacturing method of the semiconductor device of this embodiment is shown. One process of the manufacturing method of the semiconductor device of this embodiment is shown. One process of the manufacturing method of the semiconductor device of this embodiment is shown. The principal part sectional view of the semiconductor device of the 1st modification is typically shown. The principal part sectional view of the semiconductor device of the 2nd modification is typically shown. The principal part sectional view of the semiconductor device of the 3rd modification is typically shown. The principal part sectional drawing of the conventional semiconductor device is shown typically. The principal part sectional drawing of the other conventional semiconductor device is typically shown.

Explanation of symbols

20, 220: Semiconductor layer 21: Body regions 22, 122, 222: Insulating region 23: Source region 24: Body contact region 25: Drift region 26: Drain region 40: Trench-type insulated gate portion

Claims (3)

A semiconductor device,
A drain electrode;
A drain region of a first conductivity type in contact with the drain electrode;
A first conductivity type drift region in contact with the drain region and having a lower impurity concentration than the drain region;
A body region of a second conductivity type in contact with the drift region and separated from the drain electrode by the drift region and the drain region;
A first conductivity type source region in contact with the body region and separated from the drift region by the body region;
A body contact region of a second conductivity type in contact with the body region and having a higher impurity concentration than the body region;
A source electrode in contact with the source region and the body contact region;
An insulated gate portion facing the body region separating the drift region and the source region;
A semiconductor device comprising: an insulating region provided in a part between a source region and a body region and in contact with both the source region and the body region . The source region and the body contact region are adjacent,
The semiconductor device according to claim 1, wherein the source region and the body region are in contact between the insulating region and the body contact region. The drain region, the drift region, the body region, the source region, and the body contact region are provided in the surface layer portion of the semiconductor layer,
The body contact region is disposed between the drain region and the source region,
The semiconductor device according to claim 1, wherein the insulated gate portion is a trench type insulated gate portion formed in a surface layer portion of the semiconductor layer.

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