CN203521427U - Channel voltage dividing field effect tube based on high-energy ion implantation mode - Google Patents

Channel voltage dividing field effect tube based on high-energy ion implantation mode Download PDF

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CN203521427U
CN203521427U CN201320612532.1U CN201320612532U CN203521427U CN 203521427 U CN203521427 U CN 203521427U CN 201320612532 U CN201320612532 U CN 201320612532U CN 203521427 U CN203521427 U CN 203521427U
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field effect
type
source region
good conductor
channel
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关仕汉
李勇昌
彭顺刚
邹锋
王常毅
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Strong Guilin Microelectronics Co Ltd
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Strong Guilin Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The utility model discloses a channel voltage dividing field effect tube based on a high-energy ion implantation mode. The channel voltage dividing field effect tube mainly comprises a drain electrode, a grid electrode, a source electrode, an N+ substrate, a P type epitaxial layer, an n+ type vertical channel, an n type transverse channel, a good conductor, a silicon dioxide oxidation layer, a body region P, a P+ layer, a metal plug, a source region N+, a boron-phosphorosilicate glass, and an aluminium layer. High-energy ion implantation equipment is used for carrying out gradual-deep implantation, a N type channel is manufactured through diffusion for connecting a groove channel and the drain electrode, a similar-to-T-shaped structure formed by the N type channel is of a 3D structure, a depletion zone formed between P and N is changed from a single vertical direction to a vertical direction and a horizontal direction, and accordingly the withstand voltage of the zone is greatly improved, the dosage concentration of the N channel can be increased, then the effect of lowering communicating resistance is achieved.

Description

Passage dividing potential drop field effect transistor based on energetic ion injection mode
Technical field
The utility model relates to a kind of power field effect pipe, is specifically related to a kind of passage dividing potential drop field effect transistor based on energetic ion injection mode.
Background technology
Power field effect (MOS) pipe is when back-pressure is higher, because epitaxial loayer is born back-pressure, the resistivity of its epitaxial loayer is large and thickness is thicker, and causes epilayer resistance to account for the ratio maximum of whole conducting resistance, therefore, by improving epilayer resistance, come the effect of bring to power metal-oxide-semiconductor performance the most obvious.At present, popular method is the 3D structure that adopts similar super junction Super Junction, and as shown in Figure 1, the 3D structure of similar Super Junction reduces epilayer resistance from two aspects.On the one hand, vertical and horizontal both direction is changed into from single vertical direction in the space charge region of bearing back-pressure, dwindle the thickness of epitaxial loayer; On the other hand, in the situation that guaranteeing that metal-oxide-semiconductor cut-off time space charged region majority carrier can exhaust, improve epitaxial loayer carrier concentration, the resistivity of epitaxial loayer is just tried one's best little during metal-oxide-semiconductor conducting as far as possible.Like this withstand voltage constant in the situation that epilayer resistance or whole conducting resistance just diminished, during power MOS pipe work, heating is just few.Yet what Super Junction and 3D structure all adopted mostly at present is single-layer type forming method, because production technology process difficulty is larger, therefore only rest in foreign brand name producer and domestic minority supplier hand.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of passage dividing potential drop field effect transistor based on energetic ion injection mode, and it can, when reaching Super Junction and 3D structure same function, reduce technology difficulty.
For addressing the above problem, the utility model is realized by following scheme:
Passage dividing potential drop field effect transistor based on energetic ion injection mode, is mainly comprised of drain electrode, grid, source electrode, N+ substrate, P type epitaxial loayer, n+ type vertical passage, N-shaped interconnection, good conductor, silicon dioxide oxide layer, tagma P, P+ layer, metal closures, source region N+, boron-phosphorosilicate glass and aluminium lamination; Wherein the lower surface of N+ substrate back of the body gold forms the drain electrode of power field effect pipe; P type epitaxial loayer is positioned at the upper surface of N+ substrate; N+ type vertical passage, in P type epitaxial loayer, and is divided into polylith by P type epitaxial loayer; The left and right sides of N-shaped interconnection is overlapped on the top of 2 P type epitaxial loayers; The top of n+ type vertical passage is connected with N-shaped interconnection, and the bottom of n+ type vertical passage is connected with N+ substrate; Directly over every P type epitaxial loayer, each vertical is provided with a cylindricality good conductor, the side of good conductor and the bottom surface oxide layer that is coated with silicon oxide, and good conductor is outwards drawn the grid that forms power field effect pipe; A plurality of tagma P lay respectively at the top of N-shaped interconnection and are filled in good conductor gap location that periphery stays; Tagma P is connected logical with P type epitaxial loayer by the contact hole being opened on N-shaped interconnection in periphery, functional areas; Each good conductor be each side provided with 1 source region N+ and the top of source region N+ in source region P; Space between the N+ of N+Yu source region, source region forms contact groove, and the bottom of each contact groove is equipped with P+ layer, and the inside of each contact groove is all filled with metal closures; The top of 2 source region N+ and folded good conductor is respectively coated with a boron-phosphorosilicate glass; Aluminium lamination is filled the upper surface that covers metal closures and boron-phosphorosilicate glass, and the source electrode of power field effect pipe is formed at the top of aluminium lamination.
Compared with prior art, the utility model utilizes energetic ion injection device gradually deeply to inject, by diffusion, make a N-type passage again and connect raceway groove (Chanel) and drain electrode (Drain), the formed class T shape of N-type passage structure is also 3D structure, between PN, form exhaustion region (depletion layer) and change into vertical and horizontal both direction from single vertical direction, can significantly improve the withstand voltage of this region like this, thereby can increase the doping content of N passage, and then play again the effect that reduces conducting resistance; , in said structure, between gate bottom and Drain, by P extension, intercepted, be zero thereby make the electric capacity between gate bottom and Drain meanwhile substantially; And the contact portion of passage and Chanel is less, can significantly eliminate the electric capacity between grid (Gate) and Drain, the improvement of comprehensive aforementioned two aspects, the charge and discharge time in the time of can significantly reducing Gate switch (Qgd can significantly reduce), thus improved the switching speed of metal-oxide-semiconductor.Accompanying drawing explanation
Fig. 1 is the three-dimensional structure schematic diagram of the power MOS pipe of similar Super Junction;
Fig. 2-Figure 17 (comprises that Fig. 3 is a) for each step gained crystal structure schematic diagram of production method of a kind of passage dividing potential drop field effect transistor based on energetic ion injection mode;
Figure 18 is a kind of structural representation of the passage dividing potential drop field effect transistor based on energetic ion injection mode.Number in the figure: 1, drain electrode; 2, grid; 3, source electrode; 4, N+ substrate; 5, P type epitaxial loayer; 6, n+ type vertical passage; 7, N-shaped interconnection; 8, good conductor; 9, silicon dioxide oxide layer; 10, tagma P; 11, P+ layer; 12, metal closures; 13, source region N+; 14, boron-phosphorosilicate glass; 15, aluminium lamination.
Embodiment
A production method for passage dividing potential drop field effect transistor based on energetic ion injection mode, is characterized in that comprising the steps:
(1) growing P-type epitaxial loayer 5 on N+ substrate 4; Referring to Fig. 2;
(2) P type epitaxial loayer 5 glazings in step (1) growth etch strip-shaped grooves; Referring to Fig. 3; Wherein photoetching flagpole pattern as shown in Figure 3 a;
(3) in the upper surface growth silicon dioxide oxide layer of the cell wall in step (2) gained strip-shaped grooves, bottom land and P type epitaxial loayer 5; Referring to Fig. 4;
(4) in step (3) gained strip-shaped grooves, plated metal or polysilicon, as good conductor 8, and connect together and form grid 2 outside functional areas; Referring to Fig. 5;
(5) from the surface of step (4) gained crystal, spread knot downwards and form n district, referring to Fig. 6;
(6) from the surface of step (5) gained crystal, spread knot downwards and form tagma P10, now n district forms N-shaped interconnection 7, offers contact hole so that tagma P10 is communicated with in periphery, functional areas with P type epitaxial loayer 5 on the N-shaped interconnection 7 forming; Referring to Fig. 7;
(7) from the surface of step (6) gained crystal, spread knot downwards and form source region N+13; Referring to Fig. 8;
(8) at the surface deposition boron-phosphorosilicate glass 14(BPSG of step (7) gained crystal) to protect grid 2(Gate); Referring to Fig. 9;
(9) surface light at step (8) gained crystal carves contact groove; Referring to Figure 10;
(10) use energetic ion injection device, high energy phosphonium ion is repeatedly injected by different-energy grade from step (9) gained contact groove passage, make it to form the phosphonium ion layer of different depth; Referring to Figure 11 and Figure 12;
(11) phosphonium ion diffusion knot step (10) being injected forms n+ type vertical passage 6, and this n+ type vertical passage 6 and step (6) gained N-shaped interconnection 7 form the N-shaped passage bonding pad of class T shape structures; Referring to Figure 13;
(12), after N-shaped passage bonding pad forms, in the bottom of step (9) gained contact groove, inject high dose boron ion and form P+ layer 11, and spread knot; Referring to Figure 14;
(13) in the top of step (12) gained P+ layer 11, fill metal and form metal closures 12; Referring to Figure 15;
(14) step (13) gained crystal is carried out to evaporation of aluminum operation, with the upper surface at this crystal, form source electrode 3(Source); Referring to Figure 16;
(15) the N+ substrate 4 of attenuate step (14) gained crystal, and at the golden drain electrode 1(Drain that forms power field effect pipes of the N+ of the attenuate substrate 4 lower surface back of the body); Referring to Figure 17.
A kind of passage dividing potential drop field effect transistor based on energetic ion injection mode that adopts aforementioned production method to prepare, as shown in figure 18, mainly by drain electrode 1, grid 2, source electrode 3, N+ substrate 4, P type epitaxial loayer 5, n+ type vertical passage 6, N-shaped interconnection 7, good conductor 8, silicon dioxide oxide layer 9, tagma P10, P+ layer 11, metal closures 12, source region N+13, boron-phosphorosilicate glass 14 and aluminium lamination 15, formed; Wherein the lower surface of N+ substrate 4 back of the body gold forms the drain electrode 1 of power field effect pipe; P type epitaxial loayer 5 is positioned at the upper surface of N+ substrate 4; N+ type vertical passage 6, in P type epitaxial loayer 5, and is divided into polylith by P type epitaxial loayer 5; The left and right sides of N-shaped interconnection 7 is overlapped on the top of 2 P type epitaxial loayers 5; The top of n+ type vertical passage 6 is connected with N-shaped interconnection 7, and the bottom of n+ type vertical passage 6 is connected with N+ substrate 4; Directly over every P type epitaxial loayer 5, each vertical is provided with a cylindricality good conductor 8, the side of good conductor 8 and the bottom surface oxide layer 9 that is coated with silicon oxide, and good conductor 8 is outwards drawn the grid 2 that forms power field effect pipe; A plurality of tagma P10 lay respectively at the top of N-shaped interconnection 7 and are filled in good conductor 8 gap locations that periphery stays; Tagma P10 is connected logical with P type epitaxial loayer 5 by the contact hole being opened on N-shaped interconnection 7 in periphery, functional areas; Each good conductor 8 be each side provided with 1 source region N+13 and the top of source region N+13 in source region P; Source region N+13 contacts groove with the space formation between the N+13 of source region, and bottom of each contact groove is equipped with P+ layer 11, and inside of each contact groove is all filled with metal closures 12; The top of 2 source region N+13 and folded good conductor 8 is respectively coated with a boron-phosphorosilicate glass 14; Aluminium lamination 15 is filled the upper surface that covers metal closures 12 and boron-phosphorosilicate glass 14, and the source electrode 3 of power field effect pipe is formed at the top of aluminium lamination 15.

Claims (1)

1. the passage dividing potential drop field effect transistor based on energetic ion injection mode, it is characterized in that, mainly by drain electrode (1), grid (2), source electrode (3), N+ substrate (4), P type epitaxial loayer (5), n+ type vertical passage (6), N-shaped interconnection (7), good conductor (8), silicon dioxide oxide layer (9), tagma P(10), P+ layer (11), metal closures (12), source region N+(13), boron-phosphorosilicate glass (14) and aluminium lamination (15) form; Wherein the lower surface of N+ substrate (4) back of the body gold forms the drain electrode (1) of power field effect pipe; P type epitaxial loayer (5) is positioned at the upper surface of N+ substrate (4); N+ type vertical passage (6), in P type epitaxial loayer (5), and is divided into polylith by P type epitaxial loayer (5); The left and right sides of N-shaped interconnection (7) is overlapped on the top of 2 P type epitaxial loayers (5); The top of n+ type vertical passage (6) is connected with N-shaped interconnection (7), and the bottom of n+ type vertical passage (6) is connected with N+ substrate (4); Each vertical cylindricality good conductor (8) that is provided with directly over every P type epitaxial loayer (5), the side of good conductor (8) and the bottom surface oxide layer (9) that is coated with silicon oxide, good conductor (8) is outwards drawn the grid (2) that forms power field effect pipe; A plurality of tagma P(10) lay respectively at the top of N-shaped interconnection (7) and be filled in good conductor (8) gap location that periphery stays; Tagma P(10) by the contact hole being opened on N-shaped interconnection (7), in periphery, functional areas, be connected logical with P type epitaxial loayer (5); Each good conductor (8) be each side provided with 1 source region N+(13), and source region N+(13) top in source region P; Source region N+(13) with source region N+(13) between space form and contact groove, bottom of each contact groove is equipped with P+ layer (11), each inside that contacts groove is all filled with metal closures (12); 2 source region N+(13) and the top of folded good conductor (8) be respectively coated with a boron-phosphorosilicate glass (14); Aluminium lamination (15) is filled the upper surface that covers metal closures (12) and boron-phosphorosilicate glass (14), and the source electrode (3) of power field effect pipe is formed at the top of aluminium lamination (15).
CN201320612532.1U 2013-09-30 2013-09-30 Channel voltage dividing field effect tube based on high-energy ion implantation mode Withdrawn - After Issue CN203521427U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515245A (en) * 2013-09-30 2014-01-15 桂林斯壮微电子有限责任公司 Channel voltage dividing field effect tube and production method based on high-energy ion implantation mode
CN111048587A (en) * 2018-10-15 2020-04-21 无锡华润上华科技有限公司 Groove gate depletion type VDMOS device and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103515245A (en) * 2013-09-30 2014-01-15 桂林斯壮微电子有限责任公司 Channel voltage dividing field effect tube and production method based on high-energy ion implantation mode
CN103515245B (en) * 2013-09-30 2015-12-02 桂林斯壮微电子有限责任公司 Based on multi-channel voltage divider field effect transistor and the production method of energetic ion injection mode
CN111048587A (en) * 2018-10-15 2020-04-21 无锡华润上华科技有限公司 Groove gate depletion type VDMOS device and manufacturing method thereof
WO2020078315A1 (en) * 2018-10-15 2020-04-23 无锡华润上华科技有限公司 Trench gate depletion-type vdmos device and manufacturing method therefor
CN111048587B (en) * 2018-10-15 2021-07-02 无锡华润上华科技有限公司 Groove gate depletion type VDMOS device and manufacturing method thereof
US11387349B2 (en) * 2018-10-15 2022-07-12 Csmc Technologies Fab2 Co., Ltd. Trench gate depletion mode VDMOS device and method for manufacturing the same

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