CN102437192A - N-type silicon-on-insulator transverse double-diffusion field effect transistor - Google Patents
N-type silicon-on-insulator transverse double-diffusion field effect transistor Download PDFInfo
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- CN102437192A CN102437192A CN2011104040273A CN201110404027A CN102437192A CN 102437192 A CN102437192 A CN 102437192A CN 2011104040273 A CN2011104040273 A CN 2011104040273A CN 201110404027 A CN201110404027 A CN 201110404027A CN 102437192 A CN102437192 A CN 102437192A
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Abstract
The invention relates to an N-type silicon-on-insulator transverse double-diffusion field effect transistor, which comprises an N underlay, wherein buried oxygen is arranged on the N-type underlay, an N-type extension layer is arranged on the buried oxygen, an N-type buffering well and a P-type body area are arranged inside the N-type extension layer, an N-type anode area is arranged inside the N-type buffering well, an N-type cathode area and a P-type body contact area are arranged inside the P-type body area, a grid oxidized layer and a field oxidized layer are arranged within a given range on the surface of the N-type extension layer, the upper surface of the grid oxidized layer is provided with a polysilicon grid, and a passivation layer and a metal layer are also arranged within a given range on the surface of the transistor. The N-type silicon-on-insulator transverse double-diffusion field effect transistor is characterized in that: the N-type extension layer is also provided with a P-type well area, the P-type well area and the P-type body area form staircase-shaped P-type doping, the doping concentration of the P-type well area is lower than the doping concentration of the P-type body area, one side of the P-type well area is tangential to the field oxidized layer, and the other side of the P-type well area is pushed against the P-type body area. By adopting the structure, the field density and the collision ionization rate at a beak position can be remarkably reduced, so the output characteristics can be effectively improved.
Description
Technical field
The present invention relates generally to field of high voltage power semiconductor devices, specifically, is a kind of N type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor, is applicable to chip for driving such as plasma flat-plate display device, half-bridge drive circuit and automobile production field.
Background technology
Improving constantly of Along with people's living standard, electronic product constantly proposes new requirement for aspects such as volume, performance, reliability and costs.Silicon-on-insulator (Silicon On Insulator under these circumstances; SOI) technology has been come out; Its unique insulating buried layer is isolated device and substrate fully, has alleviated the influence of substrate to device, has eliminated the risk of device generation latch-up (latch-up); Alleviate the ghost effect of silicon device to a great extent, improved the performance of device and circuit greatly.Therefore the circuit that adopts SOI technology to make has speed height, characteristic such as low in energy consumption, high temperature resistant.
Horizontal dual pervasion field effect transistor is because the influence of blemish and various surface states is lower than in the body critical electric field of Si, and there is the peak electric field in the curvature effect that bring because of planar technique on the surface.These two factors have determined the puncture of LDMOS class device to occur in the surface easily; And a large amount of electron-hole pairs that the existence of surperficial peak electric field produces in the time of can causing avalanche breakdown get into thin gate oxide, thereby influence the reliability of device.Just become the key of optimizing this type device so optimize surface field.For the LDMOS of SOI, the existence of insulating buried layer brings two problems to Devices Characteristics: the one, and oxygen buried layer makes the device self-heating effect increase; The 2nd, be the restriction of zero interface Gauss theorem owing to receive free charge, the voltage that bears in the oxygen buried layer is limited.So, utilize electric charge that the screen effect of local fields is come the high electric field in the shielding insulation medium, to break through conventional electric field relation, vertical puncture voltage is increased, just become a kind of effective ways of this type of design high tension apparatus.
As everyone knows; The semiconductor power device that constantly develops into of electronic technology has been opened up application fields; Power semiconductor is also being played the part of more and more important role in daily life; And weigh a kind of quality of power semiconductor, mainly comprise output, the transfer characteristic curve of device, and the degeneration of other various parameters aspect such as whether.Simultaneously, the output characteristic curve of high tension apparatus departs from the situation of ideal conditions more easily than low-voltage device.Therefore, how under the prerequisite that does not change other parameters of device, the better optimize output characteristic curve makes that the operating state of high tension apparatus is more stable, becomes an important topic of current power semiconductor device research.
The present invention is exactly to the problems referred to above, has proposed a kind of N type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor structure.The device of this structure can significantly reduce the electric field strength and the impact ionization rate at device beak place, thereby improves output characteristic curve effectively.
Summary of the invention
The present invention provides a kind of N type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor.
The present invention adopts following technical scheme: a kind of N type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor comprises: N type substrate is provided with on N type substrate and buries oxygen; Be provided with N type epitaxial loayer on the oxygen burying, be provided with N type buffering trap and P type tagma in the inside of N type epitaxial loayer, in the N type cushions trap, be provided with N type Yang Qu; In P type tagma, be provided with cloudy district of N type and P type body contact zone; Be provided with an end of gate oxide and field oxide and gate oxide and an end of field oxide on the surface of N type epitaxial loayer and offset, the other end of said gate oxide extends and terminates in N type the moon to N type the moon district to be distinguished, and the other end of said field oxide is to N type Yang Qu extension and terminate in N type Yang Qu; Be provided with the surface that polysilicon gate and polysilicon gate extend to field oxide on the surface of gate oxide; Surface at field oxide, P type body contact zone, the cloudy district of N type, polysilicon gate and N type Yang Qu is provided with passivation layer, is connected with the first metal layer on surface, N type sun district, is connected with second metal level in P type body contact zone and the cloudy district of N type; It is characterized in that; In N type epitaxial loayer and below gate oxide, be provided with P type well region, P type well region and P type tagma constitute stepped P type mixes, and the doping content of said P type well region is lower than P type tagma; And a side and the field oxide of P type well region are tangent, and opposite side and P type tagma offset.
Compared with prior art, the present invention has following advantage:
(1), device of the present invention also is provided with P type well region 15 on N type epitaxial loayer 3; And P type well region 15 constitutes stepped P type doping (participating in accompanying drawing 2) with P type tagma 14; So just make the radius of curvature at beak place obviously diminish, the electric field strength at this place also obviously reduces (referring to accompanying drawing 3).
When (2), benefit of the present invention is to reduce the electric field strength at field oxide beak place; Can also reduce the impact ionization rate at this place; Thereby reduced the risk that device generation hot carrier degradation lost efficacy; Also promote the ability of the anti-deviatoric stress of device high temperature resistance (HTRB), and then improved the reliability of device, prolonged the useful life of device.Accompanying drawing 4 shows that the beak place impact ionization rate behind the employing device architecture of the present invention obviously reduces.
(3), the output characteristic curve of device of the present invention had obvious improvement than general device, the curve of saturation region drain current becomes smooth, and is more approaching with theoretical situations.Main cause is that the impact ionization rate at beak place descends, and ion produces also still less, because of the influence of colliding the ion pair drain current that produces reduces.Accompanying drawing 5 show adopted device architecture of the present invention after, the output characteristic curve of device be improved significantly.
(4), device of the present invention adopts high pressure SOI technology, used high-voltage P-type MOS device includes the structure of similar P type well region 15 in this technology; Therefore, manufacture craft of the present invention can with existing CMOS process compatible, can not increase extra reticle and processing step, can not increase cost yet.
(5), device of the present invention can not only improve output characteristic curve effectively, also can other performance parameters of device not exerted an influence.For example,,, make that the variations in threshold voltage of device is very little, can ignore because the effect of boron row phosphorus is inhaled on the oxide layer surface though P type tagma 15 is tangent with field oxide 10.Accompanying drawing 6 shows that the threshold voltage variation behind the employing device architecture of the present invention is very little.In addition, the reverse breakdown voltage of device can not change because of adopting device architecture of the present invention yet, and the result is with reference to accompanying drawing 7.
Description of drawings
Fig. 1 is a profile, illustrates the device profile structure of general N type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor.
Fig. 2 is a profile, illustrates the device profile structure of the N type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor after the present invention improves.
Fig. 3 is that device of the present invention " beak " is located the comparison diagram that longitudinal electric field and general structure devices " beak " are located longitudinal electric field.Can find out that the longitudinal electric field of device of the present invention at this place has tangible reduction.
Fig. 4 is the comparison diagram of impact ionization rate under impact ionization rate and the general structure devices operating state under the device operating state of the present invention.Can find out that the impact ionization rate that device of the present invention is located at " beak " has tangible reduction.
Fig. 5 is the comparison diagram of device output characteristic curve of the present invention and general device output characteristic curve.The output characteristic curve that can find out device of the present invention is more excellent, and the trend of upwarping of saturation region has significantly and weakens.
Fig. 6 is the comparison diagram of device threshold voltage of the present invention and general device threshold voltage.The threshold voltage difference that can find out both is very little, approximate can ignoring.
Fig. 7 is the reverse breakdown voltage of device of the present invention and the reverse breakdown voltage comparison diagram of general device.Can find out that both almost do not have difference.Complex chart 6 and Fig. 7, i.e. the present invention are when having improved the device output characteristic curve, to the almost not influence of other performance parameters of device.
Embodiment
Below in conjunction with accompanying drawing 2, the present invention is elaborated a kind of N type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor; Comprise: N type substrate 1, on N type substrate 1, be provided with and bury oxygen 2, be provided with N type epitaxial loayer 3 on the oxygen 2 burying; Be provided with N type buffering trap 4 and P type tagma 14 in the inside of N type epitaxial loayer 3; In N type buffering trap 4, be provided with the positive district 5 of N type, in P type tagma 14, be provided with cloudy district 13 of N type and P type body contact zone 12, be provided with gate oxide 10 and field oxide 8 and an end of gate oxide 10 and an end of field oxide 8 on the surface of N type epitaxial loayer 3 and offset; The other end of said gate oxide 10 extends and terminates in N type the moon to the cloudy district 13 of N type distinguishes 13; The other end of said field oxide 8 extends and terminates in N type sun to the positive district 5 of N type distinguishes 5, is provided with the surface that polysilicon gate 9 and polysilicon gate 9 extend to field oxide 8 on the surface of gate oxide 10, is provided with passivation layer 7 on the surface in field oxide 8, P type body contact zone 12, N type the moon district 13, polysilicon gate 9 and N type sun district 5; Be connected with the first metal layer 6 on 5 surfaces, N type sun district; 12 are connected with second metal level 11 with the cloudy district 13 of N type in P type body contact zone, it is characterized in that, in N type epitaxial loayer 3 and below gate oxide 10, are provided with P type well region 15; P type well region 15 constitutes stepped P type with P type tagma 14 and mixes; The P type doping content of said P type well region 15 is lower than P type tagma 14, and a side of P type well region 15 and field oxide 8 are tangent, and opposite side and P type tagma 14 offset.
Said structure is made a P type well region 15 that concentration is not high between P type tagma 14 and field oxide 8, can reduce the electric field strength at field oxide 8 beak places effectively.
Said structure is to reduce the electric field strength at field oxide 8 beak places, and the impact ionization rate of corresponding position also can descend, and the ion generation rate reduces.
The output characteristic curve of said structure upwarps obviously and weakens, because ionization by collision has obtained very big improvement to the influence that drain current produces.
Said structure is compared with general structure, and parameters such as the threshold voltage of device and reverse breakdown voltage change very little, can ignore.
The present invention adopts following method to prepare:
The first step, conventional soi layer is made, and wherein epitaxial loayer 3 adopts the N type to mix.
In second step, ensuing is the making of horizontal dual pervasion field effect transistor, is included on the N type extension 3 and forms N type resilient coating 4 through injecting phosphonium ion, injects the boron ion and forms P type tagma 14; Being that the boron ion injects formation doped with P type well region 15 then, secondly is the growth of field oxide 8, gate oxide 10, and the deposit polysilicon 9 afterwards, and etching forms grid, makes heavily doped sun 5 He Yin districts 13, district and P type body contact zone 12 again.Deposit silicon dioxide, depositing metal behind the etching electrode contact zone.Etching metal and extraction electrode carry out Passivation Treatment at last.
Claims (3)
1. N type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor; Comprise: N type substrate (1); On N type substrate (1), be provided with and bury oxygen (2); Be provided with N type epitaxial loayer (3) on the oxygen (2) burying, be provided with N type buffering trap (4) and P type tagma (14) in the inside of N type epitaxial loayer (3), in the N type cushions trap (4), be provided with N type Yang Qu (5); In P type tagma (14), be provided with the cloudy district of N type (13) and P type body contact zone (12); Be provided with an end of gate oxide (10) and field oxide (8) and gate oxide (10) and an end of field oxide (8) on the surface of N type epitaxial loayer (3) and offset, the other end of said gate oxide (10) extends and terminates in the cloudy district of N type (13) to the cloudy district of N type (13), and the other end of said field oxide (8) extends and terminates in N type Yang Qu (5) to N type Yang Qu (5); Be provided with the surface that polysilicon gate (9) and polysilicon gate (9) extend to field oxide (8) on the surface of gate oxide (10); Surface at field oxide (8), P type body contact zone (12), the cloudy district of N type (13), polysilicon gate (9) and N type Yang Qu (5) is provided with passivation layer (7), is connected with the first metal layer (6) on N type Yang Qu (5) surface, is connected with second metal level (11) in P type body contact zone (12) and the cloudy district of N type (13); It is characterized in that; In N type epitaxial loayer (3) and in the below of gate oxide (10), be provided with P type well region (15), P type well region (15) and P type tagma (14) constitute stepped P type mixes, and the P type doping content of said P type well region (15) is lower than P type tagma (14); And a side of P type well region (15) and field oxide (8) are tangent, and opposite side and P type tagma (14) offset.
2. N type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor according to claim 1, the doping content that it is characterized in that P type well region (15) are 1/10th to 1/5th of P type tagma (14) doping contents.
3. N type silicon-on-insulator lateral bilateral diffusion field-effect tranisistor according to claim 1, the junction depth that it is characterized in that P type well region (15) are 1/3rd to 1/2nd of P type tagma (14) junction depths.
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| CN201110404027.3A CN102437192B (en) | 2011-12-08 | 2011-12-08 | N-type silicon-on-insulator transverse double-diffusion field effect transistor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769038A (en) * | 2012-06-30 | 2012-11-07 | 东南大学 | Latch-up resisting N-type SOI laterally diffused metal oxide semiconductor |
| CN103280460A (en) * | 2013-05-22 | 2013-09-04 | 矽力杰半导体技术(杭州)有限公司 | High-voltage PMOS (p-channel metal oxide semiconductor) transistor with injection molded superimposed drift region and manufacturing method thereof |
| CN103456784A (en) * | 2012-05-30 | 2013-12-18 | 上海华虹Nec电子有限公司 | High-voltage P-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method |
Citations (3)
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| US5977569A (en) * | 1996-09-24 | 1999-11-02 | Allen-Bradley Company, Llc | Bidirectional lateral insulated gate bipolar transistor having increased voltage blocking capability |
| US20050056906A1 (en) * | 2003-07-25 | 2005-03-17 | Shinichi Jimbo | Semiconductor device |
| CN202394983U (en) * | 2011-12-08 | 2012-08-22 | 东南大学 | N type silicon on insulator transversal double diffusion field effect transistor |
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2011
- 2011-12-08 CN CN201110404027.3A patent/CN102437192B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5977569A (en) * | 1996-09-24 | 1999-11-02 | Allen-Bradley Company, Llc | Bidirectional lateral insulated gate bipolar transistor having increased voltage blocking capability |
| US20050056906A1 (en) * | 2003-07-25 | 2005-03-17 | Shinichi Jimbo | Semiconductor device |
| CN202394983U (en) * | 2011-12-08 | 2012-08-22 | 东南大学 | N type silicon on insulator transversal double diffusion field effect transistor |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456784A (en) * | 2012-05-30 | 2013-12-18 | 上海华虹Nec电子有限公司 | High-voltage P-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method |
| CN103456784B (en) * | 2012-05-30 | 2017-02-15 | 上海华虹宏力半导体制造有限公司 | High-voltage P-type LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method |
| CN102769038A (en) * | 2012-06-30 | 2012-11-07 | 东南大学 | Latch-up resisting N-type SOI laterally diffused metal oxide semiconductor |
| CN102769038B (en) * | 2012-06-30 | 2014-12-10 | 东南大学 | Latch-up resisting N-type SOI laterally diffused metal oxide semiconductor |
| CN103280460A (en) * | 2013-05-22 | 2013-09-04 | 矽力杰半导体技术(杭州)有限公司 | High-voltage PMOS (p-channel metal oxide semiconductor) transistor with injection molded superimposed drift region and manufacturing method thereof |
| US11133413B2 (en) | 2013-05-22 | 2021-09-28 | Silergy Semiconductor Technology (Hangzhou) Ltd | High voltage PMOS (HVPMOS) transistor with a composite drift region and manufacture method thereof |
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Granted publication date: 20140416 Termination date: 20211208 |