CN105514166A - NLDMOS device and manufacture method thereof - Google Patents
NLDMOS device and manufacture method thereof Download PDFInfo
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- CN105514166A CN105514166A CN201510971911.3A CN201510971911A CN105514166A CN 105514166 A CN105514166 A CN 105514166A CN 201510971911 A CN201510971911 A CN 201510971911A CN 105514166 A CN105514166 A CN 105514166A
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 238000005468 ion implantation Methods 0.000 claims abstract description 26
- 230000005684 electric field Effects 0.000 claims abstract description 24
- 230000000903 blocking effect Effects 0.000 claims abstract description 20
- 229910052760 oxygen Inorganic materials 0.000 claims description 186
- 239000001301 oxygen Substances 0.000 claims description 186
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 179
- 239000000758 substrate Substances 0.000 claims description 88
- 239000010410 layer Substances 0.000 claims description 63
- 229920005591 polysilicon Polymers 0.000 claims description 54
- 239000011229 interlayer Substances 0.000 claims description 33
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 150000002926 oxygen Chemical class 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 2
- 150000004706 metal oxides Chemical class 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 239000000428 dust Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses an N-type Laterally Diffused Metal Oxide Semiconductor (NLDMOS) device including the following steps that: a field oxide is formed above a drift region, a second side of the drift region field oxide is in lateral contact with a drain region; a first side of the drift region field oxide is arranged at the bottom of a polycrystalline silicon gate, and the first side of the drift region field oxide and a P well are separated by a distance; part of the field oxide at a top region of the first side of the drift region field oxide is removed, and the region where the field oxide is removed is filled with a substitute dielectric layer which has a character that the capacity for blocking ion implantation of the substitute dielectric layer is larger than that of the field oxide or a relative dielectric constant of the substitute dielectric layer is larger than that of the field oxide; and by using the character of the large capacity for blocking the ion implantation, the substitute dielectric layer makes a doping concentration of the drift region at the bottom of the first side of the drift region field oxide lower, thereby improving a breakdown voltage of the NLDMOS device, and by using the character of the large relative dielectric constant, the substitute dielectric layer makes the electric field strength at the bottom of the first side of the drift region field oxide reduce, thereby improving the breakdown voltage of the NLDMOS device. The invention also discloses a manufacture method of the NLDMOS device.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of N-type Laterally Diffused Metal Oxide Semiconductor (NLDMOS) device; The invention still further relates to a kind of manufacture method of NLDMOS device.
Background technology
In LDMOS device, conducting resistance is an important index.In order to make high performance LDMOS, usual needs increase by one extra N-type injection in the drift region of device, make device have lower conducting resistance, and adopt the puncture voltage that can reduce device in this way.For the technique platform of below 180nm size, the isolation structure of LDMOS is shallow trench field oxygen (STI) isolation, when puncturing generation, STI corner is ionization by collision point of maximum intensity, electric field strength is herein the highest, for improving device electric breakdown strength, need to reduce drift doping concentration herein, optimize Electric Field Distribution simultaneously.As shown in Figure 1, be the ionization by collision analogous diagram of existing NLDMOS device; Bottom the shallow trench field oxygen being positioned at bottom polysilicon gate in drift region also i.e. position shown in dotted line circle 201 shallow trench field oxygen bottom the ionization by collision point of maximum intensity of drift region, electric field strength is herein the highest, for improving device electric breakdown strength, need to reduce drift doping concentration herein, optimize Electric Field Distribution simultaneously.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of NLDMOS device, can improve the puncture voltage of device.This, the present invention also provides a kind of manufacture method of NLDMOS device.
For solving the problems of the technologies described above, NLDMOS device provided by the invention comprises:
The drift region of N-type doping, is formed in P type semiconductor substrate.
P trap, is formed in described P type semiconductor substrate, described P trap and described drift region contacts side surfaces or separated by a distance.
Be formed at the polysilicon gate of described semiconductor substrate, described polysilicon gate and the isolation of described semiconductor substrate surface have gate dielectric layer, described polysilicon gate extends to above described drift region from described P trap in the horizontal, and the described P trap covered by described polysilicon gate is for the formation of raceway groove; First side of described polysilicon gate is positioned at above described P trap, the second side is positioned at above described drift region.
The source region be made up of N+ district and drain region, described source region to be formed in described P trap and and the first side autoregistration of described polysilicon gate, described drain region is formed in described drift region.
The substrate draw-out area be made up of P+ district, described substrate draw-out area to be formed in described P trap and for being drawn by described P trap.
Be formed with a field oxygen above described drift region between described P trap and described drain region, make this oxygen be field, drift region oxygen, the second side of field, described drift region oxygen and described drain region lateral contact; Described polysilicon gate extends to above the oxygen of field, described drift region, the first side of field, described drift region oxygen be positioned at the bottom of described polysilicon gate and the first side of field, described drift region oxygen and described P trap are separated by a segment distance.
The part field oxygen of the top area of oxygen first side, field, described drift region is removed and field oxygen is removed area filling substitute medium layer, and described substitute medium layer has and is greater than the character of described field oxygen to the blocking capability of ion implantation or has the character that relative dielectric constant is greater than described field oxygen; Utilize and have the character blocking capability of ion implantation being greater than to described field oxygen, described substitute medium layer makes the doping content of the described drift region of the first side bottom being positioned at field, described drift region oxygen reduce, thus improves the puncture voltage of NLDMOS device; Utilize the character that there is relative dielectric constant and be greater than described field oxygen, described substitute medium layer makes the electric field strength of the described drift region of the first side bottom being positioned at field, described drift region oxygen reduce, increase the distributing homogeneity of drift region electric field strength, thus improves the puncture voltage of described NLDMOS device.
Further improvement is, is also formed with a described field oxygen between described substrate draw-out area and described source region, is also formed with a described field oxygen in the outside of described substrate draw-out area, and the outside in described drain region is also formed with a described field oxygen.
Further improvement is, described Semiconductor substrate is silicon substrate.
Further improvement is, described field oxygen is local field oxygen or shallow trench field oxygen, and the material of described field oxygen is silica, and the material of described substitute medium layer is silicon nitride.
Further improvement is, described gate dielectric layer is gate oxide.
Further improvement is, is formed with P type epitaxial loayer at described P type semiconductor substrate surface, bottom described P type epitaxial loayer, be formed with n type buried layer, and described drift region and described P trap are all formed in described P type epitaxial loayer.
Further improvement is, interlayer film is formed in described Semiconductor substrate front, the source electrode, the drain and gate that are formed by front metal layer is formed at the top of described interlayer film, described source electrode is contacted with described source region and described substrate draw-out area by the contact hole through described interlayer film, described drain electrode is by passing the contact hole of described interlayer film and described drain contact, and described grid is contacted with described polysilicon gate by the contact hole through described interlayer film;
Further improvement is, is also formed with a N trap in described drift region, and described drain region is formed in described N trap.
For solving the problems of the technologies described above, the manufacture method of NLDMOS device provided by the invention comprises the steps:
Step one, provide a P type semiconductor substrate, form field oxygen at described P type semiconductor substrate surface, described in one of them, field oxygen is positioned at above the drift region of follow-up formation, makes this oxygen be field, drift region oxygen.
Step 2, employing lithographic etch process remove the part field oxygen of the top area of oxygen first side, field, described drift region, second side of field, described drift region oxygen and the drain region lateral contact of follow-up formation, the first side of field, described drift region oxygen is positioned at the bottom of the polysilicon gate of follow-up formation.
The field oxygen of step 3, field, described drift region oxygen is removed area filling substitute medium layer, and described substitute medium layer has and is greater than the character of described field oxygen to the blocking capability of ion implantation or has the character that relative dielectric constant is greater than described field oxygen; Utilize and have the character blocking capability of ion implantation being greater than to described field oxygen, described substitute medium layer makes the doping content of the described drift region of the first side bottom being positioned at field, described drift region oxygen reduce, thus improves the puncture voltage of NLDMOS device; Utilize the character that there is relative dielectric constant and be greater than described field oxygen, described substitute medium layer makes the electric field strength of the described drift region of the first side bottom being positioned at field, described drift region oxygen reduce, increase the distributing homogeneity of drift region electric field strength, thus improves the puncture voltage of described NLDMOS device.
Step 4, the drift region of adulterating in P type semiconductor substrate formation N-type.
Step 5, photoetching are opened P trap injection region and are carried out P trap and be infused in described P type semiconductor substrate and form P trap, described P trap and described drift region contacts side surfaces or separated by a distance; First side of field, described drift region oxygen and described P trap are separated by a segment distance.
Step 6, formation gate dielectric layer and polysilicon gate, described polysilicon gate extends to above described drift region from described P trap in the horizontal, the described P trap covered by described polysilicon gate is for the formation of raceway groove, and the first side of described polysilicon gate is positioned at above described P trap, the second side is positioned at above the oxygen of field, described drift region.
Step 7, carry out N+ and inject and form source region and drain region, described source region to be formed in described P trap and and the first side autoregistration of described polysilicon gate, described drain region is formed in described drift region, the second side of described field oxygen and described drain region lateral contact.
Step 8, carry out P+ and inject and form substrate draw-out area, described substrate draw-out area to be formed in described P trap and for being drawn by described P trap.
Further improvement is, is also formed with a described field oxygen between described substrate draw-out area and described source region, is also formed with a described field oxygen in the outside of described substrate draw-out area, and the outside in described drain region is also formed with a described field oxygen.
Further improvement is, described Semiconductor substrate is silicon substrate.
Further improvement is, described field oxygen is local field oxygen or shallow trench field oxygen, and the material of described field oxygen is silica, and the material of described substitute medium layer is silicon nitride.
Further improvement is, described gate dielectric layer is gate oxide.
Further improvement is, is formed with P type epitaxial loayer at described P type semiconductor substrate surface, bottom described P type epitaxial loayer, be formed with n type buried layer, and described drift region and described P trap are all formed in described P type epitaxial loayer.
Further improvement is, is also formed with a N trap in described drift region, and described drain region is formed in described N trap, and described N trap adopts N-type ion implantation to be formed after step 4.
Further improvement also comprises the steps:
Step 9, form interlayer film in described Semiconductor substrate front.
Step 10, form contact hole through described interlayer film, described contact hole contacts with described substrate draw-out area, described drain region and described polysilicon gate with the described source region of bottom correspondence.
Step 11, form front metal layer at described interlayer film top and carry out chemical wet etching and form source electrode, drain and gate, described source electrode is contacted with described source region and described substrate draw-out area by the contact hole through described interlayer film, described drain electrode is by passing the contact hole of described interlayer film and described drain contact, and described grid is contacted with described polysilicon gate by the contact hole through described interlayer film.
The present invention is by carrying out particular design to the field oxygen in drift region and field, drift region oxygen, to be removed and field oxygen is removed area filling substitute medium layer near the part field oxygen of top area of the first side of P trap by the oxygen of field, drift region, and substitute medium layer is selected to have and is greater than the character of an oxygen to the blocking capability of ion implantation or has the material that relative dielectric constant is greater than the character of an oxygen.
Wherein, utilize and there is the character blocking capability of ion implantation being greater than to an oxygen, substitute medium layer can make the doping content of the drift region of the first side bottom being positioned at field, drift region oxygen reduce, and under the ion implanting conditions of identical drift region, the doping content of the drift region of the first side bottom of field, drift region oxygen can lower than the doping content bottom the drift region of other position; And in existing structure identical drift region ion implantation condition under the doping content everywhere of field, drift region oxygen identical, and when bottom the oxygen of field, drift region, doping content is everywhere identical, because the bottom of oxygen first side, field, drift region has stronger electric field strength due to the existence of corner, thus easily breakdown; And the present invention is by reducing the doping content of the drift region of field, drift region oxygen first side bottom, the electric field strength at this place can be reduced, thus the puncture voltage of device can be improved.
In addition, utilize and there is the character that relative dielectric constant is greater than an oxygen, because relative dielectric constant is larger, stronger to the weakening ability of electric field strength, so employing has relative dielectric constant when being greater than the material of the character of an oxygen
Thus improve the puncture voltage of NLDMOS device; Substitute medium layer adopts has relative dielectric constant when being greater than the material of the character of described field oxygen, the same electric field strength of the drift region of the first side bottom of field, drift region oxygen that can make reduces, thus the Electric Field Distribution uniformity optimized bottom the oxygen of field, whole drift region, thus improve the puncture voltage of described NLDMOS device.
In the present invention, when Semiconductor substrate is silicon substrate, the material of field oxygen is silica, at this moment substitute medium layer adopts silicon nitride, relative to silica, silicon nitride has the stronger blocking capability to ion implantation and larger relative dielectric constant simultaneously, so can be good at the electric field strength reducing field, drift region oxygen first side bottom, improves the puncture voltage of device.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail:
Fig. 1 is the ionization by collision analogous diagram of existing NLDMOS device;
The structural representation of Fig. 2 embodiment of the present invention NLDMOS device;
Fig. 3 A-Fig. 3 H is the device architecture schematic diagram in each step of embodiment of the present invention method.
Embodiment
As shown in Figure 2, be the structural representation of embodiment of the present invention NLDMOS device; Embodiment of the present invention NLDMOS device comprises:
The drift region 108 of N-type doping, is formed in P type semiconductor substrate 101.Be preferably, described Semiconductor substrate 101 is silicon substrate.Be formed with P type epitaxial loayer 103 on described P type semiconductor substrate 101 surface, bottom described P type epitaxial loayer 103, be formed with n type buried layer 102, described drift region 108 and follow-up P trap 107 are all formed in described P type epitaxial loayer 103.
P trap 107, is formed in described P type semiconductor substrate 101, described P trap 107 and described drift region 108 contacts side surfaces or separated by a distance.
Be formed at the polysilicon gate 110 above described Semiconductor substrate 101, described polysilicon gate 110 and the isolation of described Semiconductor substrate 101 surface have gate dielectric layer as gate oxide 109, described polysilicon gate 110 extends to above described drift region 108 from described P trap 107 in the horizontal, and the described P trap 107 covered by described polysilicon gate 110 is for the formation of raceway groove; First side of described polysilicon gate 110 is positioned at above described P trap 107, the second side is positioned at above described drift region 108.In the embodiment of the present invention, be also formed with isolation side walls 111 in the side of described polysilicon gate 110.
The source region 112a be made up of N+ district and drain region 112b, described source region 112a to be formed in described P trap 107 and and the first side autoregistration of described polysilicon gate 110, described drain region 112b is formed in described drift region 108.In the embodiment of the present invention, be also formed with a N trap 106 in described drift region 108, described drain region 112b is formed in described N trap 106.
The substrate draw-out area 113 be made up of P+ district, described substrate draw-out area 113 to be formed in described P trap 107 and for being drawn by described P trap 107.
Multiple oxygen 104, in the embodiment of the present invention, described field oxygen 104 is shallow trench field oxygen 104, and described field oxygen 104 also can be local field oxygen in other embodiments.
Being formed with a field oxygen 104 above described drift region 108 between described P trap 107 and described drain region 112b, making this oxygen 104 be field, drift region oxygen 104a, is also that in Fig. 2, field, drift region oxygen marks with 14a separately.Between described substrate draw-out area 113 and described source region 112a, a described field oxygen 104 is also formed with in the embodiment of the present invention, also be formed with a described field oxygen 104 in the outside of described substrate draw-out area 113, the outside of described drain region 112b is also formed with a described field oxygen 104.The material of described field oxygen 104 is silica.
Second side of field, described drift region oxygen 104a and described drain region 112b lateral contact; Described polysilicon gate 110 extends to above the oxygen 104a of field, described drift region, first side of field, described drift region oxygen 104a be positioned at the bottom of described polysilicon gate 110 and first side of field, described drift region oxygen 104a and described P trap 107 are separated by a segment distance.
The part field oxygen 104 of the top area of oxygen 104a first side, field, described drift region is removed and field oxygen 104 is removed area filling substitute medium layer 105, and described substitute medium layer 105 has and is greater than the character of described field oxygen 104 to the blocking capability of ion implantation or has the character that relative dielectric constant is greater than described field oxygen 104; Utilize and there is the character blocking capability of ion implantation being greater than to described field oxygen 104, described substitute medium layer 105 makes the doping content of the described drift region 108 of the first side bottom being positioned at field, described drift region oxygen 104a reduce, thus improves the puncture voltage of NLDMOS device; Utilize the character that there is relative dielectric constant and be greater than described field oxygen 104, described substitute medium layer 105 makes the electric field strength of the described drift region 108 of the first side bottom being positioned at field, described drift region oxygen 104a reduce, increase the distributing homogeneity of drift region 108 electric field strength, thus improves the puncture voltage of described NLDMOS device.
The material of the described substitute medium layer 105 in the embodiment of the present invention is silicon nitride.Relative to silica, silicon nitride has the stronger blocking capability to ion implantation and larger relative dielectric constant simultaneously, so can be good at the electric field strength reducing field, drift region oxygen first side bottom, improves the puncture voltage of device.In other is implemented, described substitute medium layer 105 also can select other material, as long as this material has two kinds of character and namely has and be greater than the character of described field oxygen 104 to the blocking capability of ion implantation or have one that relative dielectric constant is greater than in the character of described field oxygen 104, a kind of puncture voltage that can improve device all respectively in two kinds of character is as then better to the improvement of puncture voltage in having two kinds of character simultaneously.
Interlayer film is formed in described Semiconductor substrate 101 front, the source electrode, the drain and gate that are formed by front metal layer 115 is formed at the top of described interlayer film, described source electrode is contacted with described source region 112a and described substrate draw-out area 113 by the contact hole 114 through described interlayer film, described drain electrode is contacted with described drain region 112b by the contact hole 114 through described interlayer film, and described grid is contacted with described polysilicon gate 110 by the contact hole 114 through described interlayer film.
As shown in Fig. 3 A to Fig. 3 H, it is the device architecture schematic diagram in each step of embodiment of the present invention method.The manufacture method of embodiment of the present invention NLDMOS device comprises the steps:
Step one, provide a P type semiconductor substrate 101.In embodiments of the present invention, described Semiconductor substrate 101 is silicon substrate.Be formed with P type epitaxial loayer 103 on described P type semiconductor substrate 101 surface, bottom described P type epitaxial loayer 103, be formed with n type buried layer 102, follow-up drift region 108 and P trap 107 are all formed in described P type epitaxial loayer 103.When employing has the structure of described P type epitaxial loayer 103 and n type buried layer 102, need to adopt following steps to be formed:
First, as shown in Figure 3A, n type buried layer 102 is formed by N-type ion implantation on P type semiconductor substrate 101 surface, in the embodiment of the present invention, P type semiconductor substrate 101 is the low resistivity substrate of resistivity at scope 0.007 Ω cm ~ 0.013 Ω cm, described n type buried layer 102 is formed for adopting N-type Doped ions to inject, and is N+ doping.
Afterwards, as shown in Figure 3 B, described P type epitaxial loayer 103 is formed at the surface deposition of described n type buried layer 102.
Afterwards, as shown in Figure 3 C, utilize active area photoetching, described P type epitaxial loayer 103 opens shallow trench area, afterwards the P type epitaxial loayer 103 of shallow trench area is etched, carry out deposit and grinding technics afterwards in shallow trench, to fill silica form field oxygen 104, namely the oxygen of field described in the embodiment of the present invention 104 is the shallow trench field oxygen 104 formed by shallow ditch groove separation process.Described field oxygen 104 also can be local field oxygen in other embodiments.
Form field oxygen 104 on described P type semiconductor substrate 101 surface, field oxygen 104 described in one of them is positioned at above the drift region 108 of follow-up formation, makes this oxygen 104 be field, drift region oxygen 104a.
The embodiment of the present invention comprises multiple oxygen 104, wherein, being formed with a field oxygen 104 above described drift region 108 between described P trap 107 and described drain region 112b, making this oxygen 104 be field, drift region oxygen 104a, is also that in Fig. 2, field, drift region oxygen marks with 14a separately.Between described substrate draw-out area 113 and described source region 112a, be also formed with a described field oxygen 104, be also formed with a described field oxygen 104 in the outside of described substrate draw-out area 113, the outside of described drain region 112b is also formed with a described field oxygen 104.
Step 2, as shown in Figure 3 D, lithographic etch process is adopted to remove the part field oxygen 104 of the top area of oxygen 104a first side, field, described drift region, second side of field, described drift region oxygen 104a and the drain region 112b lateral contact of follow-up formation, first side of field, described drift region oxygen 104a is positioned at the bottom of the polysilicon gate 110 of follow-up formation.
Step 3, as shown in Figure 3 D, the field oxygen 104 of field, described drift region oxygen 104a is removed area filling substitute medium layer 105, and described substitute medium layer 105 has and is greater than the character of described field oxygen 104 to the blocking capability of ion implantation or has the character that relative dielectric constant is greater than described field oxygen 104; Utilize and there is the character blocking capability of ion implantation being greater than to described field oxygen 104, described substitute medium layer 105 makes the doping content of the described drift region 108 of the first side bottom being positioned at field, described drift region oxygen 104a reduce, thus improves the puncture voltage of NLDMOS device; Utilize the character that there is relative dielectric constant and be greater than described field oxygen 104, described substitute medium layer 105 makes the electric field strength of the described drift region 108 of the first side bottom being positioned at field, described drift region oxygen 104a reduce, increase the distributing homogeneity of drift region 108 electric field strength, thus improves the puncture voltage of described NLDMOS device.
In the embodiment of the present invention, the material of described substitute medium layer 105 is silicon nitride.In other embodiments, other two character that at least have any also can be adopted namely to have and be greater than the character of described field oxygen 104 to the blocking capability of ion implantation or have the material that relative dielectric constant is greater than one of the character of described field oxygen 104.
Step 4, as shown in FIGURE 3 E, adopt photoetching to add N-type ion implantation technology forms N-type doping drift region 108 at P type semiconductor substrate 101.
Step 5, photoetching are opened P trap 107 injection region and are carried out P trap 107 and be infused in described P type semiconductor substrate 101 and form P trap 107, described P trap 107 and described drift region 108 contacts side surfaces or separated by a distance; First side of field, described drift region oxygen 104a and described P trap 107 are separated by a segment distance.
Be preferably, also comprise in the embodiment of the present invention and adopt photoetching to add the step that N-type ion implantation technology forms N trap 106 in described drift region 108, follow-up described drain region 112b can be formed in described N trap 106.
Step 6, as illustrated in Figure 3 F, form gate dielectric layer 109 and polysilicon gate 110, be preferably, described gate dielectric layer 109 is gate oxide.
Described polysilicon gate 110 extends to above described drift region 108 from described P trap 107 in the horizontal, the described P trap 107 covered by described polysilicon gate 110 is for the formation of raceway groove, and the first side of described polysilicon gate 110 is positioned at above described P trap 107, the second side is positioned at above the oxygen 104a of field, described drift region.
As shown in Figure 3 G, adopt deposit to add dry etch process and form isolation side walls 111 in the side of described polysilicon gate 110.In the embodiment of the present invention, the silicon dioxide of first deposit one deck 2500 dust ~ 3500 dust, then carries out dry etching and forms described isolation side walls 111.
Step 7, as illustrated in Figure 3 F, carry out N+ injection and source and drain injection formation source region 112a and drain region 112b, described source region 112a to be formed in described P trap 107 and and the first side autoregistration of described polysilicon gate 110, described drain region 112b is formed in described drift region 108, the second side of described field oxygen 104 and described drain region 112b lateral contact.
Step 8, as illustrated in Figure 3 F, carries out P+ and injects and form substrate draw-out area 113, and described substrate draw-out area 113 to be formed in described P trap 107 and for being drawn by described P trap 107.In the embodiment of the present invention, between described substrate draw-out area 113 and described source region 112a, include a field oxygen 104; In other embodiments, described substrate draw-out area 113 and described source region 112a also can be the structure of lateral contact.
Step 9, form interlayer film in described Semiconductor substrate 101 front.
Step 10, form contact hole 114 through described interlayer film, described contact hole 114 contacts with described substrate draw-out area 113, described drain region 112b and described polysilicon gate 110 with the described source region 112a of bottom correspondence.
Step 11, form front metal layer 115 at described interlayer film top and carry out chemical wet etching and form source electrode, drain and gate, described source electrode is contacted with described source region 112a and described substrate draw-out area 113 by the contact hole 114 through described interlayer film, described drain electrode is contacted with described drain region 112b by the contact hole 114 through described interlayer film, and described grid is contacted with described polysilicon gate 110 by the contact hole 114 through described interlayer film.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (16)
1. a NLDMOS device, is characterized in that, comprising:
The drift region of N-type doping, is formed in P type semiconductor substrate;
P trap, is formed in described P type semiconductor substrate, described P trap and described drift region contacts side surfaces or separated by a distance;
Be formed at the polysilicon gate of described semiconductor substrate, described polysilicon gate and the isolation of described semiconductor substrate surface have gate dielectric layer, described polysilicon gate extends to above described drift region from described P trap in the horizontal, and the described P trap covered by described polysilicon gate is for the formation of raceway groove; First side of described polysilicon gate is positioned at above described P trap, the second side is positioned at above described drift region;
The source region be made up of N+ district and drain region, described source region to be formed in described P trap and and the first side autoregistration of described polysilicon gate, described drain region is formed in described drift region;
The substrate draw-out area be made up of P+ district, described substrate draw-out area to be formed in described P trap and for being drawn by described P trap;
Be formed with a field oxygen above described drift region between described P trap and described drain region, make this oxygen be field, drift region oxygen, the second side of field, described drift region oxygen and described drain region lateral contact; Described polysilicon gate extends to above the oxygen of field, described drift region, the first side of field, described drift region oxygen be positioned at the bottom of described polysilicon gate and the first side of field, described drift region oxygen and described P trap are separated by a segment distance;
The part field oxygen of the top area of oxygen first side, field, described drift region is removed and field oxygen is removed area filling substitute medium layer, and described substitute medium layer has and is greater than the character of described field oxygen to the blocking capability of ion implantation or has the character that relative dielectric constant is greater than described field oxygen; Utilize and have the character blocking capability of ion implantation being greater than to described field oxygen, described substitute medium layer makes the doping content of the described drift region of the first side bottom being positioned at field, described drift region oxygen reduce, thus improves the puncture voltage of NLDMOS device; Utilize the character that there is relative dielectric constant and be greater than described field oxygen, described substitute medium layer makes the electric field strength of the described drift region of the first side bottom being positioned at field, described drift region oxygen reduce, increase the distributing homogeneity of drift region electric field strength, thus improves the puncture voltage of described NLDMOS device.
2. NLDMOS device as claimed in claim 1, it is characterized in that: between described substrate draw-out area and described source region, be also formed with a described field oxygen, also be formed with a described field oxygen in the outside of described substrate draw-out area, the outside in described drain region is also formed with a described field oxygen.
3. NLDMOS device as claimed in claim 1 or 2, is characterized in that: described Semiconductor substrate is silicon substrate.
4. NLDMOS device as claimed in claim 3, is characterized in that: described field oxygen is local field oxygen or shallow trench field oxygen, and the material of described field oxygen is silica, and the material of described substitute medium layer is silicon nitride.
5. NLDMOS device as claimed in claim 1, is characterized in that: described gate dielectric layer is gate oxide.
6. NLDMOS device as claimed in claim 1, it is characterized in that: be formed with P type epitaxial loayer at described P type semiconductor substrate surface, bottom described P type epitaxial loayer, be formed with n type buried layer, described drift region and described P trap are all formed in described P type epitaxial loayer.
7. NLDMOS device as claimed in claim 1, it is characterized in that: be formed with interlayer film in described Semiconductor substrate front, the source electrode, the drain and gate that are formed by front metal layer is formed at the top of described interlayer film, described source electrode is contacted with described source region and described substrate draw-out area by the contact hole through described interlayer film, described drain electrode is by passing the contact hole of described interlayer film and described drain contact, and described grid is contacted with described polysilicon gate by the contact hole through described interlayer film.
8. NLDMOS device as claimed in claim 1, it is characterized in that: be also formed with a N trap in described drift region, described drain region is formed in described N trap.
9. a manufacture method for NLDMOS device, is characterized in that, comprises the steps:
Step one, provide a P type semiconductor substrate, form field oxygen at described P type semiconductor substrate surface, described in one of them, field oxygen is positioned at above the drift region of follow-up formation, makes this oxygen be field, drift region oxygen;
Step 2, employing lithographic etch process remove the part field oxygen of the top area of oxygen first side, field, described drift region, second side of field, described drift region oxygen and the drain region lateral contact of follow-up formation, the first side of field, described drift region oxygen is positioned at the bottom of the polysilicon gate of follow-up formation;
The field oxygen of step 3, field, described drift region oxygen is removed area filling substitute medium layer, and described substitute medium layer has and is greater than the character of described field oxygen to the blocking capability of ion implantation or has the character that relative dielectric constant is greater than described field oxygen; Utilize and have the character blocking capability of ion implantation being greater than to described field oxygen, described substitute medium layer makes the doping content of the described drift region of the first side bottom being positioned at field, described drift region oxygen reduce, thus improves the puncture voltage of NLDMOS device; Utilize the character that there is relative dielectric constant and be greater than described field oxygen, described substitute medium layer makes the electric field strength of the described drift region of the first side bottom being positioned at field, described drift region oxygen reduce, increase the distributing homogeneity of drift region electric field strength, thus improves the puncture voltage of described NLDMOS device.
Step 4, the drift region of adulterating in P type semiconductor substrate formation N-type;
Step 5, photoetching are opened P trap injection region and are carried out P trap and be infused in described P type semiconductor substrate and form P trap, described P trap and described drift region contacts side surfaces or separated by a distance; First side of field, described drift region oxygen and described P trap are separated by a segment distance;
Step 6, formation gate dielectric layer and polysilicon gate, described polysilicon gate extends to above described drift region from described P trap in the horizontal, the described P trap covered by described polysilicon gate is for the formation of raceway groove, and the first side of described polysilicon gate is positioned at above described P trap, the second side is positioned at above the oxygen of field, described drift region;
Step 7, carry out N+ and inject and form source region and drain region, described source region to be formed in described P trap and and the first side autoregistration of described polysilicon gate, described drain region is formed in described drift region, the second side of described field oxygen and described drain region lateral contact;
Step 8, carry out P+ and inject and form substrate draw-out area, described substrate draw-out area to be formed in described P trap and for being drawn by described P trap.
10. the manufacture method of NLDMOS device as claimed in claim 9, it is characterized in that: between described substrate draw-out area and described source region, be also formed with a described field oxygen, also be formed with a described field oxygen in the outside of described substrate draw-out area, the outside in described drain region is also formed with a described field oxygen.
The manufacture method of 11. NLDMOS device as described in claim 9 or 10, is characterized in that: described Semiconductor substrate is silicon substrate.
The manufacture method of 12. NLDMOS device as claimed in claim 11, is characterized in that: described field oxygen is local field oxygen or shallow trench field oxygen, and the material of described field oxygen is silica, and the material of described substitute medium layer is silicon nitride.
The manufacture method of 13. NLDMOS device as claimed in claim 9, is characterized in that: described gate dielectric layer is gate oxide.
The manufacture method of 14. NLDMOS device as claimed in claim 9, it is characterized in that: be formed with P type epitaxial loayer at described P type semiconductor substrate surface, bottom described P type epitaxial loayer, be formed with n type buried layer, described drift region and described P trap are all formed in described P type epitaxial loayer.
The manufacture method of 15. NLDMOS device as claimed in claim 9, is characterized in that: be also formed with a N trap in described drift region, described drain region is formed in described N trap, and described N trap adopts N-type ion implantation to be formed after step 4.
The manufacture method of 16. NLDMOS device as claimed in claim 9, is characterized in that, also comprise the steps:
Step 9, form interlayer film in described Semiconductor substrate front;
Step 10, form contact hole through described interlayer film, described contact hole contacts with described substrate draw-out area, described drain region and described polysilicon gate with the described source region of bottom correspondence;
Step 11, form front metal layer at described interlayer film top and carry out chemical wet etching and form source electrode, drain and gate, described source electrode is contacted with described source region and described substrate draw-out area by the contact hole through described interlayer film, described drain electrode is by passing the contact hole of described interlayer film and described drain contact, and described grid is contacted with described polysilicon gate by the contact hole through described interlayer film.
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