CN105514166A - NLDMOS device and manufacture method thereof - Google Patents

Abstract

The invention discloses an NLDMOS device, comprising: a field oxygen is formed above the drift region, the second side of the field oxygen in the drift region is in lateral contact with the drain region; the first side of the field oxygen in the drift region is located at the bottom of the polysilicon gate and The P wells are separated by a certain distance; part of the field oxygen in the top region of the first side of the field oxygen in the drift region is removed, and the area where the field oxygen is removed is filled with a replacement dielectric layer, and the replacement dielectric layer has a property that the blocking ability of the ion implantation is greater than that of the field oxygen Or have the property that the relative permittivity is greater than that of field oxygen; the property of greater barrier ability to ion implantation can reduce the doping concentration of the drift region located at the bottom of the first side of the field oxygen in the drift region, and utilize a larger relative permittivity The nature of the electric constant can reduce the electric field intensity at the bottom of the first side of the field oxygen in the drift region, and both can increase the breakdown voltage respectively. The invention also discloses a manufacturing method of the NLDMOS device.

Description

NLDMOS device and its manufacturing method

technical field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an N-type laterally diffused metal oxide semiconductor (NLDMOS) device; the invention also relates to a manufacturing method of the NLDMOS device.

Background technique

In LDMOS devices, on-resistance is an important indicator. In order to make high-performance LDMOS, it is usually necessary to add an additional N-type implant in the drift region of the device to make the device have a lower on-resistance, and this method will reduce the breakdown voltage of the device. For process platforms with a size below 180nm, the isolation structure of LDMOS is shallow trench field oxygen (STI) isolation. When breakdown occurs, the corner of STI is the strongest point of impact ionization, where the electric field intensity is the highest. In order to improve the breakdown voltage of the device , it is necessary to reduce the doping concentration in the drift region and optimize the electric field distribution. As shown in FIG. 1 , it is an impact ionization simulation diagram of an existing NLDMOS device; in the drift region, the bottom of the shallow trench field oxygen at the bottom of the polysilicon gate, that is, the bottom of the shallow trench field oxygen at the position shown by the dotted circle 201 The strongest impact ionization point in the drift region has the highest electric field intensity. In order to increase the breakdown voltage of the device, it is necessary to reduce the doping concentration in the drift region and optimize the electric field distribution.

Contents of the invention

The technical problem to be solved by the present invention is to provide an NLDMOS device, which can improve the breakdown voltage of the device. Therefore, the present invention also provides a manufacturing method of the NLDMOS device.

In order to solve the above technical problems, the NLDMOS device provided by the present invention includes:

The N-type doped drift region is formed in the P-type semiconductor substrate.

A P well is formed in the P-type semiconductor substrate, and the P well is in contact with or separated from a side of the drift region by a certain distance.

A polysilicon gate formed above the semiconductor substrate, the polysilicon gate is isolated from the surface of the semiconductor substrate by a gate dielectric layer, and the polysilicon gate extends from the P well to above the drift region in the lateral direction, and is formed by The P well covered by the polysilicon gate is used to form a channel; the first side of the polysilicon gate is located above the P well, and the second side is located above the drift region.

A source region and a drain region composed of an N+ region, the source region is formed in the P well and self-aligned with the first side of the polysilicon gate, and the drain region is formed in the drift region.

A substrate lead-out region composed of a P+ region, the substrate lead-out region is formed in the P well and used to lead out the P well.

A field oxygen is formed above the drift region between the P well and the drain region, let the field oxygen be the drift region field oxygen, the second side of the drift region field oxygen and the lateral direction of the drain region contact; the polysilicon gate extends above the drift region field oxygen, the first side of the drift region field oxygen is located at the bottom of the polysilicon gate and the first side of the drift region field oxygen is separated from the P well some distance.

Part of the field oxygen in the top region of the first side of the field oxygen in the drift region is removed, and the region where the field oxygen is removed is filled with a replacement dielectric layer, and the replacement dielectric layer has a property that the blocking ability of ion implantation is greater than that of the field oxygen. Or have the property that the relative permittivity is greater than that of the field oxygen; by utilizing the property that the ion implantation blocking ability is greater than that of the field oxygen, the replacement dielectric layer makes all the parts located at the bottom of the first side of the field oxygen in the drift region The doping concentration of the drift region is reduced, thereby increasing the breakdown voltage of the NLDMOS device; using the property of having a relative permittivity greater than that of the field oxygen, the replacement dielectric layer makes the bottom of the first side of the field oxygen located in the drift region The electric field intensity in the drift region is reduced, and the distribution uniformity of the electric field intensity in the drift region is increased, thereby increasing the breakdown voltage of the NLDMOS device.

A further improvement is that one field oxygen is also formed between the substrate lead-out region and the source region, one field oxygen is also formed outside the substrate lead-out region, and the drain region The outer side is also formed with one of the field oxygen.

A further improvement is that the semiconductor substrate is a silicon substrate.

A further improvement is that the field oxygen is local field oxygen or shallow trench field oxygen, the material of the field oxygen is silicon oxide, and the material of the replacement dielectric layer is silicon nitride.

A further improvement is that the gate dielectric layer is a gate oxide layer.

A further improvement is that a P-type epitaxial layer is formed on the surface of the P-type semiconductor substrate, an N-type buried layer is formed at the bottom of the P-type epitaxial layer, and both the drift region and the P well are formed on the In the P-type epitaxial layer.

A further improvement is that an interlayer film is formed on the front surface of the semiconductor substrate, and a source, drain and gate formed by a front metal layer are formed on the top of the interlayer film, and the source electrode passes through The contact hole of the interlayer film is in contact with the source region and the substrate lead-out region, the drain is in contact with the drain region through the contact hole passing through the interlayer film, and the gate is in contact with the drain region through the contacting the polysilicon gate through the contact hole of the interlayer film;

A further improvement is that an N well is formed in the drift region, and the drain region is formed in the N well.

In order to solve the above-mentioned technical problems, the manufacturing method of the NLDMOS device provided by the present invention comprises the following steps:

Step 1. A P-type semiconductor substrate is provided, and field oxygen is formed on the surface of the P-type semiconductor substrate. One of the field oxygen is located above a subsequently formed drift region, and the field oxygen is the drift region field oxygen.

Step 2, using a photolithographic etching process to remove part of the field oxygen in the top region of the first side of the field oxygen in the drift region, the second side of the field oxygen in the drift region is in lateral contact with the subsequently formed drain region, and the drift region The first side of the field oxygen is located at the bottom of the subsequently formed polysilicon gate.

Step 3, the area where the field oxygen in the drift region is removed is filled with a substitute medium layer, and the substitute medium layer has a property of blocking ion implantation greater than that of the field oxygen or has a relative permittivity greater than that of the field oxygen properties; utilizing the property that the blocking ability to ion implantation is greater than that of the field oxygen, the substitution dielectric layer reduces the doping concentration of the drift region located at the bottom of the first side of the field oxygen in the drift region, thereby improving The breakdown voltage of the NLDMOS device; utilizing the property of having a relative permittivity greater than that of the field oxygen, the replacement dielectric layer reduces the electric field intensity in the drift region located at the bottom of the first side of the field oxygen in the drift region, The distribution uniformity of the electric field intensity in the drift region is increased, thereby improving the breakdown voltage of the NLDMOS device.

Step 4, forming an N-type doped drift region on the P-type semiconductor substrate.

Step 5, photolithographically open the P well implantation region and perform P well implantation to form a P well in the P-type semiconductor substrate, the P well is in contact with the side of the drift region or is separated by a certain distance; the drift region field oxygen There is a distance between the first side of the P-well and the P-well.

Step 6, forming a gate dielectric layer and a polysilicon gate, the polysilicon gate extends laterally from the P well to above the drift region, the P well covered by the polysilicon gate is used to form a channel, the The first side of the polysilicon gate is located above the P well, and the second side is located above the field oxygen of the drift region.

Step 7, perform N+ implantation to form a source region and a drain region, the source region is formed in the P well and self-aligned with the first side of the polysilicon gate, the drain region is formed in the drift region, The second side of the field oxygen is in lateral contact with the drain region.

Step 8: performing P+ implantation to form a substrate lead-out region, the substrate lead-out region is formed in the P well and used to lead out the P well.

A further improvement is that one field oxygen is also formed between the substrate lead-out region and the source region, one field oxygen is also formed outside the substrate lead-out region, and the drain region The outer side is also formed with one of the field oxygen.

A further improvement is that the semiconductor substrate is a silicon substrate.

A further improvement is that the field oxygen is local field oxygen or shallow trench field oxygen, the material of the field oxygen is silicon oxide, and the material of the replacement dielectric layer is silicon nitride.

A further improvement is that the gate dielectric layer is a gate oxide layer.

A further improvement is that a P-type epitaxial layer is formed on the surface of the P-type semiconductor substrate, an N-type buried layer is formed at the bottom of the P-type epitaxial layer, and both the drift region and the P well are formed on the In the P-type epitaxial layer.

A further improvement is that an N well is formed in the drift region, the drain region is formed in the N well, and the N well is formed by N-type ion implantation after step four.

A further improvement is to also include the following steps:

Step 9, forming an interlayer film on the front surface of the semiconductor substrate.

Step 10, forming a contact hole passing through the interlayer film, the contact hole and the bottom corresponding to the source region and the substrate lead-out region, the drain region and the polysilicon gate contact.

Step eleven, forming a front metal layer on the top of the interlayer film and performing photolithography to form a source, a drain and a gate, and the source passes through the contact hole passing through the interlayer film and the source region and the substrate lead-out region, the drain is in contact with the drain region through a contact hole passing through the interlayer film, and the gate is in contact with the drain region through a contact hole passing through the interlayer film. polysilicon gate contact.

The present invention specially designs the field oxygen in the drift region, that is, the field oxygen in the drift region, that is, part of the field oxygen in the top region near the first side of the P well in the field oxygen in the drift region is removed, and the removed region is filled with The dielectric layer is replaced, and the dielectric layer is selected to have a property of blocking ion implantation greater than that of field oxygen or a material with a relative permittivity greater than that of field oxygen.

Wherein, by utilizing the property that the blocking ability to ion implantation is greater than that of field oxygen, the substitute dielectric layer can reduce the doping concentration of the drift region located at the bottom of the first side of the field oxygen in the drift region, under the same ion implantation conditions of the drift region The doping concentration of the drift region at the bottom of the first side of the oxygen in the drift region will be lower than the doping concentration at the bottom of the drift region at other positions; and under the same ion implantation conditions in the drift region in the existing structure, each of the oxygen in the drift region The doping concentration at the position is the same, and when the doping concentration at the bottom of the field oxygen in the drift region is the same, since the bottom of the first side of the field oxygen in the drift region has a strong electric field strength due to the existence of the corner, it is easy to be broken down; However, in the present invention, by reducing the doping concentration of the drift region at the bottom of the first side of the oxygen field in the drift region, the electric field intensity there can be reduced, thereby improving the breakdown voltage of the device.

In addition, using the property that the relative permittivity is greater than field oxygen, the greater the relative permittivity, the stronger the ability to weaken the electric field strength, so when using a material with a relative permittivity greater than field oxygen

Thereby improving the breakdown voltage of NLDMOS device; When the substitute dielectric layer adopts the material with relative permittivity greater than the property of described field oxygen, can also make the electric field intensity of the drift region of the first side bottom of drift region field oxygen reduce, thereby The uniformity of electric field distribution at the bottom of the field oxygen in the entire drift region is optimized, thereby improving the breakdown voltage of the NLDMOS device.

In the present invention, when the semiconductor substrate is a silicon substrate, the material of the field oxygen is silicon oxide. At this time, silicon nitride is used as the substitute dielectric layer. Compared with silicon oxide, silicon nitride has a stronger barrier to ion implantation at the same time. ability and a larger relative permittivity, so it can well reduce the electric field intensity at the bottom of the first side of the drift region field oxygen, and improve the breakdown voltage of the device.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment, the utility model is described in further detail:

FIG. 1 is a simulation diagram of impact ionization of an existing NLDMOS device;

Fig. 2 is a schematic structural diagram of an NLDMOS device according to an embodiment of the present invention;

3A-3H are schematic diagrams of device structures in each step of the method of the embodiment of the present invention.

detailed description

As shown in Figure 2, it is a schematic structural diagram of an NLDMOS device according to an embodiment of the present invention; the NLDMOS device according to an embodiment of the present invention includes:

The N-type doped drift region 108 is formed in the P-type semiconductor substrate 101 . Preferably, the semiconductor substrate 101 is a silicon substrate. A P-type epitaxial layer 103 is formed on the surface of the P-type semiconductor substrate 101, an N-type buried layer 102 is formed at the bottom of the P-type epitaxial layer 103, and the drift region 108 and the subsequent P well 107 are all formed in the P-type epitaxial layer 103. In the P-type epitaxial layer 103.

The P-well 107 is formed in the P-type semiconductor substrate 101 , and the side of the P-well 107 and the drift region 108 are in contact or separated by a certain distance.

The polysilicon gate 110 formed above the semiconductor substrate 101, the polysilicon gate 110 is isolated from the surface of the semiconductor substrate 101 by a gate dielectric layer such as a gate oxide layer 109, and the polysilicon gate 110 is separated from the P The well 107 extends above the drift region 108, and the P well 107 covered by the polysilicon gate 110 is used to form a channel; the first side of the polysilicon gate 110 is located above the P well 107, and the second side is above the drift region 108 . In the embodiment of the present invention, an isolation spacer 111 is further formed on the side of the polysilicon gate 110 .

A source region 112a and a drain region 112b composed of an N+ region, the source region 112a is formed in the P well 107 and self-aligned with the first side of the polysilicon gate 110, and the drain region 112b is formed in the in the drift region 108 . In the embodiment of the present invention, an N well 106 is further formed in the drift region 108 , and the drain region 112 b is formed in the N well 106 .

A substrate lead-out region 113 composed of a P+ region, the substrate lead-out region 113 is formed in the P well 107 and used to lead the P well 107 out.

A plurality of field oxygen 104. In the embodiment of the present invention, the field oxygen 104 is a shallow trench field oxygen 104. In other embodiments, the field oxygen 104 can also be a local field oxygen.

A field oxygen 104 is formed above the drift region 108 between the P well 107 and the drain region 112b, and the field oxygen 104 is a drift region field oxygen 104a, that is, the drift region field oxygen is alone in FIG. 2 Marked with 14a. In the embodiment of the present invention, one field oxygen 104 is also formed between the substrate lead-out region 113 and the source region 112a, and one field oxygen 104 is also formed outside the substrate lead-out region 113 , a field oxygen 104 is also formed outside the drain region 112b. The material of the field oxygen 104 is silicon oxide.

The second side of the drift region field oxygen 104a is in lateral contact with the drain region 112b; the polysilicon gate 110 extends above the drift region field oxygen 104a, and the first side of the drift region field oxygen 104a is located on the The bottom of the polysilicon gate 110 and the first side of the drift region field oxygen 104 a are separated from the P well 107 by a certain distance.

Part of the field oxygen 104 in the top region of the first side of the field oxygen 104a in the drift region is removed, and the removed area of the field oxygen 104 is filled with a replacement dielectric layer 105, and the replacement dielectric layer 105 has a resistance to ion implantation greater than the specified The property of the field oxygen 104 or the property of having a relative permittivity greater than that of the field oxygen 104; utilizing the property of having an ion implantation resistance greater than that of the field oxygen 104, the replacement dielectric layer 105 is located in the drift region The doping concentration of the drift region 108 at the bottom of the first side of the field oxygen 104a is reduced, thereby increasing the breakdown voltage of the NLDMOS device; utilizing the property of having a relative permittivity greater than that of the field oxygen 104, the replacement dielectric layer 105 The electric field intensity in the drift region 108 located at the bottom of the first side of the drift region field oxygen 104a is reduced, and the distribution uniformity of the electric field intensity in the drift region 108 is increased, thereby increasing the breakdown voltage of the NLDMOS device.

The material of the replacement dielectric layer 105 in the embodiment of the present invention is silicon nitride. Compared with silicon oxide, silicon nitride has a stronger resistance to ion implantation and a larger relative permittivity, so it can well reduce the electric field intensity at the bottom of the first side of the drift region field oxygen, and improve the device's shock. wear voltage. In other implementations, the replacement dielectric layer 105 can also choose other materials, as long as this material has two properties, that is, it has a property of blocking ion implantation greater than that of the field oxygen 104 or has a relative permittivity greater than the One of the properties of the field oxygen 104 is sufficient, and one of the two properties can respectively increase the breakdown voltage of the device, and if both properties are present at the same time, the improvement of the breakdown voltage will be even better.

An interlayer film is formed on the front side of the semiconductor substrate 101, and a source, a drain, and a gate formed by a front metal layer 115 are formed on the top of the interlayer film, and the source electrode passes through the layer The contact hole 114 of the interlayer film is in contact with the source region 112a and the substrate lead-out region 113, the drain is in contact with the drain region 112b through the contact hole 114 passing through the interlayer film, and the gate The polysilicon gate 110 is in contact with the polysilicon gate 110 through the contact hole 114 passing through the interlayer film.

As shown in FIG. 3A to FIG. 3H , they are schematic diagrams of device structures in each step of the method of the embodiment of the present invention. The manufacturing method of the NLDMOS device of the embodiment of the present invention includes the following steps:

Step 1, providing a P-type semiconductor substrate 101 . In the embodiment of the present invention, the semiconductor substrate 101 is a silicon substrate. A P-type epitaxial layer 103 is formed on the surface of the P-type semiconductor substrate 101, an N-type buried layer 102 is formed at the bottom of the P-type epitaxial layer 103, and subsequent drift regions 108 and P wells 107 are formed in the P-type semiconductor substrate 101. type epitaxial layer 103 . When adopting the structure with the P-type epitaxial layer 103 and the N-type buried layer 102, it is necessary to adopt the following steps to form:

First, as shown in FIG. 3A, an N-type buried layer 102 is formed on the surface of the P-type semiconductor substrate 101 by N-type ion implantation. Ω·cm low-resistance substrate, the N-type buried layer 102 is formed by implanting N-type doped ions, that is, N+ doped.

After that, as shown in FIG. 3B , the P-type epitaxial layer 103 is formed by depositing on the surface of the N-type buried layer 102 .

Afterwards, as shown in FIG. 3C, the shallow trench region is opened on the P-type epitaxial layer 103 by using active region photolithography, and then the P-type epitaxial layer 103 in the shallow trench region is etched, and then deposited And the grinding process fills the shallow trench with silicon oxide to form the field oxygen 104, that is, the field oxygen 104 in the embodiment of the present invention is the shallow trench field oxygen 104 formed by the shallow trench isolation process. In other embodiments, the field oxygen 104 can also be local field oxygen.

Field oxygen 104 is formed on the surface of the P-type semiconductor substrate 101 , and one of the field oxygen 104 is located above the subsequently formed drift region 108 , so that the field oxygen 104 is the drift region field oxygen 104 a.

The embodiment of the present invention includes a plurality of field oxygen 104, wherein a field oxygen 104 is formed above the drift region 108 between the P well 107 and the drain region 112b, and the field oxygen 104 is a drift region The field oxygen 104a, that is, the field oxygen in the drift region in FIG. 2 is marked with 14a alone. A field oxygen 104 is also formed between the substrate lead-out region 113 and the source region 112a, and a field oxygen 104 is also formed outside the substrate lead-out region 113, and the drain region The field oxygen 104 is also formed on the outside of 112b.

Step 2. As shown in FIG. 3D, a photolithography process is used to remove part of the field oxygen 104 in the top region of the first side of the drift region field oxygen 104a, and the second side of the drift region field oxygen 104a and the subsequently formed The drain region 112b is laterally contacted, and the first side of the drift region field oxide 104a is located at the bottom of the subsequently formed polysilicon gate 110 .

Step 3, as shown in FIG. 3D , the area where the field oxygen 104 of the field oxygen 104a in the drift region is removed is filled with a replacement dielectric layer 105 , and the replacement dielectric layer 105 has a property of blocking ion implantation greater than that of the field oxygen 104 Or have the property that the relative permittivity is greater than that of the field oxygen 104; by utilizing the property that the barrier ability to ion implantation is greater than that of the field oxygen 104, the replacement dielectric layer 105 makes the first field oxygen 104a located in the drift region The doping concentration of the drift region 108 at the bottom of the side is reduced, thereby increasing the breakdown voltage of the NLDMOS device; utilizing the property of having a relative permittivity greater than that of the field oxygen 104, the replacement dielectric layer 105 is located in the drift region The electric field intensity in the drift region 108 at the bottom of the first side of the field oxygen 104a is reduced, and the distribution uniformity of the electric field intensity in the drift region 108 is increased, thereby increasing the breakdown voltage of the NLDMOS device.

In the embodiment of the present invention, the material of the replacement dielectric layer 105 is silicon nitride. In other embodiments, it is also possible to use any other at least one of two properties, that is, the property of having a barrier ability to ion implantation greater than that of the field oxygen 104 or the property of having a relative permittivity greater than that of the field oxygen 104. Material.

Step 4, as shown in FIG. 3E , an N-type doped drift region 108 is formed on the P-type semiconductor substrate 101 by photolithography plus N-type ion implantation process.

Step 5, open the P well 107 implantation region by photolithography and perform P well 107 implantation to form a P well 107 in the P-type semiconductor substrate 101, and the P well 107 and the drift region 108 are in side contact or are separated by a certain distance; The first side of the drift region field oxygen 104a is separated from the P-well 107 by a certain distance.

Preferably, the embodiment of the present invention also includes the step of forming the N well 106 in the drift region 108 by photolithography plus N-type ion implantation process, and the drain region 112b will be formed in the N well 106 later.

Step 6, as shown in FIG. 3F , forming a gate dielectric layer 109 and a polysilicon gate 110 , preferably, the gate dielectric layer 109 is a gate oxide layer.

The polysilicon gate 110 extends laterally from the P well 107 to above the drift region 108, the P well 107 covered by the polysilicon gate 110 is used to form a channel, and the first of the polysilicon gate 110 The side is located above the P-well 107 , and the second side is located above the field oxygen 104 a in the drift region.

As shown in FIG. 3G , an isolation spacer 111 is formed on the side of the polysilicon gate 110 by a deposition plus dry etching process. In the embodiment of the present invention, a layer of silicon dioxide with a thickness of 2500-3500 Angstroms is deposited first, and then dry etching is performed to form the isolation spacers 111 .

Step 7, as shown in FIG. 3F , perform N+ implantation, that is, source and drain implantation, to form a source region 112a and a drain region 112b. The source region 112a is formed in the P well 107 and is free from the first side surface of the polysilicon gate 110 Alignment, the drain region 112b is formed in the drift region 108, and the second side of the field oxide 104 is in lateral contact with the drain region 112b.

Step 8, as shown in FIG. 3F , perform P+ implantation to form a substrate lead-out region 113 , the substrate lead-out region 113 is formed in the P well 107 and is used to lead out the P well 107 . In the embodiment of the present invention, a field oxygen 104 is included between the substrate lead-out region 113 and the source region 112a; in other embodiments, the substrate lead-out region 113 and the source region 112a can also be The structure of lateral contact.

Step 9, forming an interlayer film on the front surface of the semiconductor substrate 101 .

Step ten, forming a contact hole 114 through the interlayer film, the contact hole 114 and the bottom corresponding to the source region 112a and the substrate lead-out region 113, the drain region 112b and the polysilicon gate 110 touch.

Step eleven, forming a front metal layer 115 on the top of the interlayer film and performing photolithography to form source, drain and gate, the source passes through the contact hole 114 passing through the interlayer film and the The source region 112a is in contact with the substrate lead-out region 113, the drain is in contact with the drain region 112b through a contact hole 114 passing through the interlayer film, and the gate electrode is in contact with the drain region 112b through a contact hole 114 passing through the interlayer film. The contact hole 114 is in contact with the polysilicon gate 110 .

The present invention has been described in detail through specific examples above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (16)

1. A kind of NLDMOS device, is characterized in that, comprises: An N-type doped drift region is formed in a P-type semiconductor substrate; A P well is formed in the P-type semiconductor substrate, and the P well is in contact with or separated from the side of the drift region by a certain distance; A polysilicon gate formed above the semiconductor substrate, the polysilicon gate is isolated from the surface of the semiconductor substrate by a gate dielectric layer, and the polysilicon gate extends from the P well to above the drift region in the lateral direction, and is formed by The P well covered by the polysilicon gate is used to form a channel; the first side of the polysilicon gate is located above the P well, and the second side is located above the drift region; a source region and a drain region consisting of an N+ region, the source region being formed in the P well and self-aligned with the first side of the polysilicon gate, the drain region being formed in the drift region; a substrate lead-out region consisting of a P+ region, the substrate lead-out region being formed in the P well and used to lead the P well out; A field oxygen is formed above the drift region between the P well and the drain region, let the field oxygen be the drift region field oxygen, the second side of the drift region field oxygen and the lateral direction of the drain region contact; the polysilicon gate extends above the drift region field oxygen, the first side of the drift region field oxygen is located at the bottom of the polysilicon gate and the first side of the drift region field oxygen is separated from the P well a distance; Part of the field oxygen in the top region of the first side of the field oxygen in the drift region is removed, and the region where the field oxygen is removed is filled with a replacement dielectric layer, and the replacement dielectric layer has a property that the blocking ability of ion implantation is greater than that of the field oxygen. Or have the property that the relative permittivity is greater than that of the field oxygen; by utilizing the property that the ion implantation blocking ability is greater than that of the field oxygen, the replacement dielectric layer makes all the parts located at the bottom of the first side of the field oxygen in the drift region The doping concentration of the drift region is reduced, thereby increasing the breakdown voltage of the NLDMOS device; using the property of having a relative permittivity greater than that of the field oxygen, the replacement dielectric layer makes the bottom of the first side of the field oxygen located in the drift region The electric field intensity in the drift region is reduced, and the distribution uniformity of the electric field intensity in the drift region is increased, thereby increasing the breakdown voltage of the NLDMOS device. 2. The NLDMOS device according to claim 1, characterized in that: a field oxygen is also formed between the substrate lead-out region and the source region, and is also formed outside the substrate lead-out region There is one field oxygen, and one field oxygen is also formed outside the drain region. 3. The NLDMOS device according to claim 1 or 2, wherein the semiconductor substrate is a silicon substrate. 4. The NLDMOS device according to claim 3, wherein the field oxygen is local field oxygen or shallow trench field oxygen, the material of the field oxygen is silicon oxide, and the material of the replacement dielectric layer is nitrogen Silicon. 5. The NLDMOS device according to claim 1, wherein the gate dielectric layer is a gate oxide layer. 6. The NLDMOS device according to claim 1, characterized in that: a P-type epitaxial layer is formed on the surface of the P-type semiconductor substrate, an N-type buried layer is formed at the bottom of the P-type epitaxial layer, and the drift region and the P-well are formed in the P-type epitaxial layer. 7. The NLDMOS device according to claim 1, characterized in that: an interlayer film is formed on the front side of the semiconductor substrate, and a source electrode and a drain electrode formed by a front metal layer are formed on the top of the interlayer film and the gate, the source is in contact with the source region and the substrate lead-out region through the contact hole passing through the interlayer film, and the drain is in contact with the source region and the substrate lead-out region through the contact hole passing through the interlayer film The drain region is in contact, and the gate is in contact with the polysilicon gate through a contact hole passing through the interlayer film. 8. The NLDMOS device according to claim 1, wherein an N well is formed in the drift region, and the drain region is formed in the N well. 9. A method for manufacturing an NLDMOS device, comprising the steps of: Step 1. A P-type semiconductor substrate is provided, and field oxygen is formed on the surface of the P-type semiconductor substrate, wherein one of the field oxygen is located above the subsequently formed drift region, so that the field oxygen is the drift region field oxygen; Step 2, using a photolithographic etching process to remove part of the field oxygen in the top region of the first side of the field oxygen in the drift region, the second side of the field oxygen in the drift region is in lateral contact with the subsequently formed drain region, and the drift region The first side of the field oxygen is located at the bottom of the subsequently formed polysilicon gate; Step 3, the area where the field oxygen in the drift region is removed is filled with a substitute medium layer, and the substitute medium layer has a property of blocking ion implantation greater than that of the field oxygen or has a relative permittivity greater than that of the field oxygen properties; utilizing the property that the blocking ability to ion implantation is greater than that of the field oxygen, the substitution dielectric layer reduces the doping concentration of the drift region located at the bottom of the first side of the field oxygen in the drift region, thereby improving The breakdown voltage of the NLDMOS device; utilizing the property of having a relative permittivity greater than that of the field oxygen, the replacement dielectric layer reduces the electric field intensity in the drift region located at the bottom of the first side of the field oxygen in the drift region, The distribution uniformity of the electric field intensity in the drift region is increased, thereby improving the breakdown voltage of the NLDMOS device. Step 4, forming an N-type doped drift region on the P-type semiconductor substrate; Step 5, photolithographically open the P well implantation region and perform P well implantation to form a P well in the P-type semiconductor substrate, the P well is in contact with the side of the drift region or is separated by a certain distance; the drift region field oxygen The first side of the P well is separated by a certain distance; Step 6, forming a gate dielectric layer and a polysilicon gate, the polysilicon gate extends laterally from the P well to above the drift region, the P well covered by the polysilicon gate is used to form a channel, the The first side of the polysilicon gate is located above the P well, and the second side is located above the field oxygen in the drift region; Step 7, perform N+ implantation to form a source region and a drain region, the source region is formed in the P well and self-aligned with the first side of the polysilicon gate, the drain region is formed in the drift region, The second side of the field oxygen is in lateral contact with the drain region; Step 8: performing P+ implantation to form a substrate lead-out region, the substrate lead-out region is formed in the P well and used to lead out the P well. 10. The method for manufacturing an NLDMOS device according to claim 9, characterized in that: a field oxygen is also formed between the substrate lead-out region and the source region, and in the substrate lead-out region One field oxygen is also formed outside, and one field oxygen is also formed outside the drain region. 11. The method for manufacturing an NLDMOS device according to claim 9 or 10, wherein the semiconductor substrate is a silicon substrate. 12. The method for manufacturing an NLDMOS device according to claim 11, wherein the field oxygen is local field oxygen or shallow trench field oxygen, the material of the field oxygen is silicon oxide, and the replacement medium layer The material is silicon nitride. 13. The method for manufacturing an NLDMOS device according to claim 9, wherein the gate dielectric layer is a gate oxide layer. 14. The method for manufacturing an NLDMOS device according to claim 9, wherein a P-type epitaxial layer is formed on the surface of the P-type semiconductor substrate, and an N-type buried layer is formed at the bottom of the P-type epitaxial layer, Both the drift region and the P-well are formed in the P-type epitaxial layer. 15. The method for manufacturing an NLDMOS device as claimed in claim 9, characterized in that: an N well is also formed in the drift region, the drain region is formed in the N well, and the N well is formed in step 4 Then it is formed by N-type ion implantation. 16. The manufacturing method of NLDMOS device as claimed in claim 9, is characterized in that, also comprises the steps: Step 9, forming an interlayer film on the front surface of the semiconductor substrate; Step 10, forming a contact hole through the interlayer film, the contact hole and the bottom corresponding to the source region and the substrate lead-out region, the drain region and the polysilicon gate contact; Step eleven, forming a front metal layer on the top of the interlayer film and performing photolithography to form a source, a drain and a gate, and the source passes through the contact hole passing through the interlayer film and the source region and the substrate lead-out region, the drain is in contact with the drain region through a contact hole passing through the interlayer film, and the gate is in contact with the drain region through a contact hole passing through the interlayer film. polysilicon gate contact.