CN105514166B - NLDMOS device and its manufacture method - Google Patents
NLDMOS device and its manufacture method Download PDFInfo
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- CN105514166B CN105514166B CN201510971911.3A CN201510971911A CN105514166B CN 105514166 B CN105514166 B CN 105514166B CN 201510971911 A CN201510971911 A CN 201510971911A CN 105514166 B CN105514166 B CN 105514166B
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 196
- 239000001301 oxygen Substances 0.000 claims abstract description 196
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 189
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 53
- 229920005591 polysilicon Polymers 0.000 claims abstract description 53
- 230000015556 catabolic process Effects 0.000 claims abstract description 25
- 230000005684 electric field Effects 0.000 claims abstract description 24
- 230000000903 blocking effect Effects 0.000 claims abstract description 19
- 238000011049 filling Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 87
- 239000000758 substrate Substances 0.000 claims description 86
- 239000004065 semiconductor Substances 0.000 claims description 47
- 239000011229 interlayer Substances 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 7
- 150000002926 oxygen Chemical class 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000006872 improvement Effects 0.000 description 16
- 238000010586 diagram Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of NLDMOS device, including：Laterally contacted formed with a field oxygen, the second side and drain region of drift region oxygen above drift region；First side of drift region oxygen be located at the bottom of polysilicon gate and with p-well at a distance；The part oxygen of the top area of drift region the first side of oxygen is removed and field oxygen is removed area filling and has substitute medium layer, and substitute medium layer is more than the property of field oxygen with the blocking capability to ion implanting or is more than the property of field oxygen with relative dielectric constant；The property larger to the blocking capability of ion implanting can reduce the doping concentration of the drift region of the first side bottom positioned at drift region oxygen, and utilize the property with larger relative dielectric constant, it can make the electric field strength of the first side bottom positioned at drift region oxygen reduce, the two breakdown voltage that can be respectively increased.The invention also discloses the manufacture method of NLDMOS device.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, more particularly to a kind of N-type lateral diffused metal oxide
Semiconductor (NLDMOS) device；The invention further relates to a kind of manufacture method of NLDMOS device.
Background technology
In LDMOS device, conducting resistance is an important index.In order to make high performance LDMOS, it usually needs
Increase by one of extra N-type injection in the drift region of device, device is had relatively low conducting resistance, and can drop in this way
The breakdown voltage of low device.For the technique platform of below 180nm sizes, the isolation structure of LDMOS is shallow trench field oxygen (STI)
Isolation, STI corners are ionization by collision point of maximum intensity when breakdown occurs, and electric field strength highest herein is electric to improve device breakdown
Pressure is, it is necessary to reduce drift doping concentration herein, while optimize electric field distribution.As shown in Figure 1, it is touching for existing NLDMOS device
Hit ionization analogous diagram；In drift region positioned at position shown in the shallow trench field oxygen bottom of polysilicon gate bottom namely dotted line circle 201
The ionization by collision point of maximum intensity of the drift region of the shallow trench field oxygen bottom at place is put, electric field strength highest herein, hits to improve device
Voltage is worn, it is necessary to reduce drift doping concentration herein, while optimizes electric field distribution.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of NLDMOS device, can improve the breakdown voltage of device.This,
The present invention also provides a kind of manufacture method of NLDMOS device.
In order to solve the above technical problems, NLDMOS device provided by the invention includes：
The drift region of n-type doping, is formed in P-type semiconductor substrate.
P-well, is formed in the P-type semiconductor substrate, the p-well and the drift region contacts side surfaces or is separated by a spacing
From.
Be formed at the polysilicon gate of the semiconductor substrate, the polysilicon gate and the semiconductor substrate surface every
From there is gate dielectric layer, the polysilicon gate is extended to above the drift region from the p-well in the horizontal, by the polysilicon gate
The p-well of covering is used to form raceway groove；The first side of the polysilicon gate is located above the p-well, second side is located at
Above the drift region.
By N+ district's groups into source region and drain region, the source region be formed in the p-well and and the polysilicon gate first
Side autoregistration, the drain region are formed in the drift region.
By P+ district's groups into substrate draw-out area, the substrate draw-out area is formed in the p-well and for the p-well to be drawn
Go out.
Formed with a field oxygen above the drift region between the p-well and the drain region, this oxygen is made as drift
Area oxygen, the second side and the drain region of the drift region oxygen laterally contact；The polysilicon gate extends to the drift region
Above the oxygen of field, the first side of the drift region oxygen is located at the bottom of the polysilicon gate and the first side of the drift region oxygen
With the p-well at a distance.
The part oxygen of the top area of drift region first side of oxygen is removed and field oxygen is removed area filling and has
Substitute medium layer, the substitute medium layer are more than the property of the field oxygen or with phase with the blocking capability to ion implanting
It is more than the property of the field oxygen to dielectric constant；Using with the property for being more than the field oxygen to the blocking capability of ion implanting,
The substitute medium layer reduces the doping concentration of the drift region of the first side bottom positioned at the drift region oxygen, so that
Improve the breakdown voltage of NLDMOS device；Utilize the property for being more than the field oxygen with relative dielectric constant, the substitute medium
Layer reduces the electric field strength in the drift region of the first side bottom of the drift region oxygen, increase drift region electric field
The distributing homogeneity of intensity, so as to improve the breakdown voltage of the NLDMOS device.
A further improvement is that the field oxygen is also formed between the substrate draw-out area and the source region,
The field oxygen is also formed with the outside of the substrate draw-out area, the field oxygen is also formed with the outside of the drain region.
A further improvement is that the Semiconductor substrate is silicon substrate.
A further improvement is that the field oxygen is local field oxygen or shallow trench field oxygen, the material of the field oxygen is silica,
The material of the substitute medium layer is silicon nitride.
A further improvement is that the gate dielectric layer is gate oxide.
A further improvement is that in the P-type semiconductor substrate surface formed with p-type epitaxial layer, in the p-type epitaxial layer
Bottom is formed in the p-type epitaxial layer formed with n type buried layer, the drift region and the p-well.
A further improvement is that in the Semiconductor substrate front formed with interlayer film, in the top shape of the interlayer film
Into having the source electrode formed by front metal layer, drain and gate, the source electrode passes through the contact hole through the interlayer film and institute
State source region and substrate draw-out area contact, the drain electrode are connect by the contact hole through the interlayer film and the drain region
Touch, the grid is contacted by the contact hole through the interlayer film and the polysilicon gate；
A further improvement is that being also formed with a N trap in the drift region, the drain region is formed in the N traps.
In order to solve the above technical problems, the manufacture method of NLDMOS device provided by the invention includes the following steps：
Step 1: providing a P-type semiconductor substrate, field oxygen, one of institute are formed in the P-type semiconductor substrate surface
State an oxygen to be located above the drift region being subsequently formed, make this oxygen as drift region oxygen.
Step 2: the part oxygen of the top area of drift region first side of oxygen is removed using lithographic etch process,
Second side of the drift region oxygen and the drain region being subsequently formed laterally contact, and the first side of the drift region oxygen is positioned at follow-up
The bottom of the polysilicon gate of formation.
Step 3: the field oxygen of the drift region oxygen is removed area filling substitute medium layer, the substitute medium layer tool
There is the property that the property of the field oxygen is more than to the blocking capability of ion implanting or is more than the field oxygen with relative dielectric constant
Matter；Using the property for being more than the field oxygen with the blocking capability to ion implanting, the substitute medium layer makes to be located at the drift
Moving the doping concentration of the drift region of the first side bottom of area oxygen reduces, so as to improve the breakdown voltage of NLDMOS device；
Using the property for being more than the field oxygen with relative dielectric constant, the substitute medium layer makes the positioned at the drift region oxygen
Electric field strength in the drift region of one side bottom reduces, the distributing homogeneity of increase drift region electric field strength, so as to improve
The breakdown voltage of the NLDMOS device.
Step 4: form the drift region of n-type doping in P-type semiconductor substrate.
Step 5: photoetching opens p-well injection region and carries out p-well and be infused in the P-type semiconductor substrate to form p-well, institute
State p-well and the drift region contacts side surfaces or separated by a distance；First side of the drift region oxygen and the p-well are separated by one
Segment distance.
Step 6: forming gate dielectric layer and polysilicon gate, the polysilicon gate extends to described from the p-well in the horizontal
Above drift region, the p-well covered by the polysilicon gate is used to form raceway groove, and the first side of the polysilicon gate is located at
The p-well top, second side are located above the oxygen of the drift region.
Inject to form source region and drain region Step 7: carrying out N+, the source region is formed in the p-well and and the polysilicon
The first side autoregistration of grid, the drain region are formed in the drift region, and the second side of the field oxygen and the drain region are horizontal
Contact.
Inject to form substrate draw-out area Step 8: carrying out P+, the substrate draw-out area is formed in the p-well and for inciting somebody to action
The p-well is drawn.
A further improvement is that the field oxygen is also formed between the substrate draw-out area and the source region,
The field oxygen is also formed with the outside of the substrate draw-out area, the field oxygen is also formed with the outside of the drain region.
A further improvement is that the Semiconductor substrate is silicon substrate.
A further improvement is that the field oxygen is local field oxygen or shallow trench field oxygen, the material of the field oxygen is silica,
The material of the substitute medium layer is silicon nitride.
A further improvement is that the gate dielectric layer is gate oxide.
A further improvement is that in the P-type semiconductor substrate surface formed with p-type epitaxial layer, in the p-type epitaxial layer
Bottom is formed in the p-type epitaxial layer formed with n type buried layer, the drift region and the p-well.
A further improvement is that being also formed with a N trap in the drift region, the drain region is formed in the N traps, institute
N traps are stated to be formed using N-type ion implanting after step 4.
A further improvement is that further include following steps：
Step 9: form interlayer film in Semiconductor substrate front.
Step 10: form the contact hole through the interlayer film, the corresponding source region of the contact hole and bottom and institute
State substrate draw-out area, the drain region and polysilicon gate contact.
Step 11: at the top of the interlayer film formed front metal layer and carry out chemical wet etching formed source electrode, drain electrode and
Grid, the source electrode is contacted by the contact hole through the interlayer film and the source region and the substrate draw-out area, described
Drain electrode passes through the contact through the interlayer film by the contact hole through the interlayer film and the drain contact, the grid
Hole and polysilicon gate contact.
The present invention will be leaned on by carrying out special designing to the field oxygen in drift region, that is, drift region oxygen in the oxygen of drift region
The part oxygen of the top area of first side of nearly p-well is removed and field oxygen is removed area filling and has substitute medium layer, and replaces
It is more than the property of field oxygen with the blocking capability to ion implanting for dielectric layer selection or is more than field with relative dielectric constant
The material of the property of oxygen.
Wherein, can be made positioned at drift using the property for being more than field oxygen with the blocking capability to ion implanting, substitute medium layer
Moving the doping concentration of the drift region of the first side bottom of area oxygen reduces, and drifts about under the ion implanting conditions of identical drift region
The doping concentration of the drift region of first side bottom of area oxygen can be less than the doping concentration of the drift region bottom at other positions；And
The doping concentration everywhere of drift region oxygen is identical under conditions of identical drift region ion implanting in existing structure, and in drift region
The doping concentration phase of field oxygen bottom everywhere is simultaneously as the bottom of drift region the first side of oxygen is stronger since the presence of corner has
Electric field strength so that easily it is breakdown；And the doping of the invention by reducing the drift region of drift region the first side bottom of oxygen
Concentration, can reduce the electric field strength at this, so as to improve the breakdown voltage of device.
In addition, using the property for being more than field oxygen with relative dielectric constant, since relative dielectric constant is bigger, to electric-field strength
The weakening ability of degree is stronger, so when using the material for the property for being more than field oxygen with relative dielectric constant
So as to improve the breakdown voltage of NLDMOS device；Substitute medium layer uses, and there is relative dielectric constant to be more than the field
During the material of the property of oxygen, it can equally make the electric field strength of the drift region of the first side bottom of drift region oxygen reduce, so that excellent
Change the electric field distributing homogeneity of whole drift region Chang Yang bottoms, so as to improve the breakdown voltage of the NLDMOS device.
In the present invention, when Semiconductor substrate is silicon substrate, the material of field oxygen is silica, and at this moment substitute medium layer uses
Silicon nitride, relative to silica, silicon nitride has opposite Jie of the stronger blocking capability to ion implanting and bigger at the same time
Electric constant, so can be good at reducing the electric field strength of drift region the first side bottom of oxygen, improves the breakdown voltage of device.
Brief description of the drawings
The utility model is described in further detail with reference to the accompanying drawings and detailed description：
Fig. 1 is the ionization by collision analogous diagram of existing NLDMOS device；
The structure diagram of Fig. 2 NLDMOS devices of the embodiment of the present invention；
Fig. 3 A- Fig. 3 H are the device architecture schematic diagrames in each step of present invention method.
Embodiment
As shown in Fig. 2, it is the structure diagram of NLDMOS device of the embodiment of the present invention；NLDMOS device of the embodiment of the present invention
Including：
The drift region 108 of n-type doping, is formed in P-type semiconductor substrate 101.Preferably, the Semiconductor substrate 101
For silicon substrate.On 101 surface of P-type semiconductor substrate formed with p-type epitaxial layer 103, in 103 bottom of p-type epitaxial layer
Formed with n type buried layer 102, the drift region 108 and follow-up p-well 107 are formed in the p-type epitaxial layer 103.
P-well 107, is formed in the P-type semiconductor substrate 101,108 contacts side surfaces of the p-well 107 and the drift region
It is or separated by a distance.
It is formed at the polysilicon gate 110 of the top of Semiconductor substrate 101, the polysilicon gate 110 and the semiconductor
The isolation of 101 surface of substrate has gate dielectric layer such as gate oxide 109, and the polysilicon gate 110 prolongs from the p-well 107 in the horizontal
The top of drift region 108 is reached, the p-well 107 covered by the polysilicon gate 110 is used to form raceway groove；The polycrystalline
The first side of Si-gate 110 is positioned at the top of p-well 107, second side positioned at the top of drift region 108.The present invention is implemented
In example, isolation side walls 111 are also formed with the side of the polysilicon gate 110.
By N+ district's groups into source region 112a and drain region 112b, the source region 112a be formed in the p-well 107 and and it is described
The first side autoregistration of polysilicon gate 110, the drain region 112b are formed in the drift region 108.In the embodiment of the present invention,
A N trap 106 is also formed with the drift region 108, the drain region 112b is formed in the N traps 106.
By P+ district's groups into substrate draw-out area 113, the substrate draw-out area 113 be formed in the p-well 107 and for will
The p-well 107 is drawn.
Multiple oxygen 104, in the embodiment of the present invention, the field oxygen 104 is shallow trench field oxygen 104, in other embodiments
The field oxygen 104 also can be local field oxygen.
Formed with a field oxygen 104, order above the drift region 108 between the p-well 107 and the drain region 112b
This oxygen 104 is drift region oxygen 104a, namely drift region oxygen is individually marked with 104a in Fig. 2.In the embodiment of the present invention
The field oxygen 104 is also formed between the substrate draw-out area 113 and the source region 112a, in the substrate draw-out area
113 outside is also formed with the field oxygen 104, and the field oxygen 104 is also formed with the outside of the drain region 112b.Institute
The material for stating an oxygen 104 is silica.
The second side of the drift region oxygen 104a and the drain region 112b are laterally contacted；The polysilicon gate 110 extends
To above the oxygen 104a of the drift region, the first side of the drift region oxygen 104a is located at the bottom of the polysilicon gate 110
And the first side of the drift region oxygen 104a and the p-well 107 are at a distance.
The part oxygen 104 of the top area of drift region first sides of oxygen 104a is removed and field oxygen 104 is removed
Area filling has substitute medium layer 105, and the substitute medium layer 105 has is more than the field oxygen to the blocking capability of ion implanting
104 property or the property for being more than the field oxygen 104 with relative dielectric constant；Using with the stop energy to ion implanting
Power is more than the property of the field oxygen 104, and the substitute medium layer 105 makes the first side bottom positioned at the drift region oxygen 104a
The drift region 108 doping concentration reduce, so as to improve the breakdown voltage of NLDMOS device；Using normal with opposite dielectric
Number is more than the property of the field oxygen 104, and the substitute medium layer 105 makes the first side bottom positioned at the drift region oxygen 104a
The drift region 108 in electric field strength reduce, increase by 108 electric field strength of drift region distributing homogeneity, so as to improve institute
State the breakdown voltage of NLDMOS device.
The material of the substitute medium layer 105 in the embodiment of the present invention is silicon nitride.It is same relative to silica, silicon nitride
When the relative dielectric constant with the stronger blocking capability to ion implanting and bigger, so can be good at reduce drift
The electric field strength of area the first side bottom of oxygen, improves the breakdown voltage of device.In other implementations, the substitute medium layer 105
Also other materials can be selected, as long as this material is more than the field with two kinds of properties with the blocking capability to ion implanting
The property of oxygen 104 or be more than with relative dielectric constant in the property of the field oxygen 104 one, one in two kinds of properties
Kind can all improve the breakdown voltage of device respectively, and the improvement to breakdown voltage if having two kinds of properties at the same time is better.
In the front of Semiconductor substrate 101 formed with interlayer film, at the top of the interlayer film formed with by positive gold
Belong to source electrode, the drain and gate that layer 115 is formed, the source electrode passes through the contact hole 114 through the interlayer film and the source region
112a and the substrate draw-out area 113 contact, and the drain electrode passes through the contact hole 114 through the interlayer film and the drain region
112b is contacted, and the grid is contacted by the contact hole 114 through the interlayer film and the polysilicon gate 110.
It is the device architecture schematic diagram in each step of present invention method as shown in Fig. 3 A to Fig. 3 H.It is of the invention real
The manufacture method for applying a NLDMOS device includes the following steps：
Step 1: provide a P-type semiconductor substrate 101.In embodiments of the present invention, the Semiconductor substrate 101 is silicon
Substrate.On 101 surface of P-type semiconductor substrate formed with p-type epitaxial layer 103, formed in 103 bottom of p-type epitaxial layer
There is n type buried layer 102, follow-up drift region 108 and p-well 107 are formed in the p-type epitaxial layer 103.Using with the P
, it is necessary to be formed using following steps during the structure of type epitaxial layer 103 and n type buried layer 102：
First, as shown in Figure 3A, n type buried layer 102 is formed by N-type ion implanting on 101 surface of P-type semiconductor substrate,
In the embodiment of the present invention P-type semiconductor substrate 101 for resistivity the Ω cm of 0.007 Ω cm of scope~0.013 low-resistance lining
Bottom, the n type buried layer 102 are N+ doping to be formed using n-type doping ion implanting.
Afterwards, as shown in Figure 3B, the p-type epitaxial layer 103 is formed in the surface deposition of the n type buried layer 102.
Afterwards, as shown in Figure 3 C, using active area photoetching, shallow trench area is opened on the p-type epitaxial layer 103, it
The p-type epitaxial layer 103 of shallow trench area is performed etching afterwards, is deposited afterwards and grinding technics fills oxygen in shallow trench
SiClx forms field oxygen 104, i.e., field oxygen 104 is the shallow trench field formed by shallow ditch groove separation process described in the embodiment of the present invention
Oxygen 104.The field oxygen 104 also can be local field oxygen in other embodiments.
Field oxygen 104 is formed on 101 surface of P-type semiconductor substrate, one of them described field oxygen 104, which is located at, to be subsequently formed
The top of drift region 108, make this oxygen 104 as drift region oxygen 104a.
The embodiment of the present invention includes multiple oxygen 104, wherein, the institute between the p-well 107 and the drain region 112b
The top of drift region 108 is stated formed with a field oxygen 104, makes this oxygen 104 as drift region oxygen 104a, namely drift region in Fig. 2
Field oxygen is individually marked with 104a.The field oxygen is also formed between the substrate draw-out area 113 and the source region 112a
104, the field oxygen 104 is also formed with the outside of the substrate draw-out area 113, the outside of the drain region 112b is also formed
There is the field oxygen 104.
Step 2: as shown in Figure 3D, the top of drift region first sides of oxygen 104a is removed using lithographic etch process
The part oxygen 104 in region, the second side of the drift region oxygen 104a and the drain region 112b being subsequently formed laterally are contacted, described
The first side of drift region oxygen 104a is located at the bottom for the polysilicon gate 110 being subsequently formed.
Step 3: as shown in Figure 3D, the field oxygen 104 of the drift region oxygen 104a is removed area filling substitute medium layer
105, the substitute medium layer 105 is more than the property of the field oxygen 104 or with phase with the blocking capability to ion implanting
It is more than the property of the field oxygen 104 to dielectric constant；It is more than the field oxygen 104 using with the blocking capability to ion implanting
Property, the substitute medium layer 105 make mixing for the drift region 108 of the first side bottom positioned at the drift region oxygen 104a
Miscellaneous concentration reduces, so as to improve the breakdown voltage of NLDMOS device；It is more than the field oxygen 104 using with relative dielectric constant
Property, the substitute medium layer 105 make in the drift region 108 of the first side bottom of the drift region oxygen 104a
Electric field strength reduces, the distributing homogeneity of increase by 108 electric field strength of drift region, so as to improve the breakdown potential of the NLDMOS device
Pressure.
In the embodiment of the present invention, the material of the substitute medium layer 105 is silicon nitride.In other embodiments, can also adopt
With it is any other at least with two attributes be with property of the blocking capability to ion implanting more than the field oxygen 104 or
Person has the material that relative dielectric constant is more than one of the property of the field oxygen 104.
Step 4: as shown in FIGURE 3 E, N-type is formed in P-type semiconductor substrate 101 using photoetching plus N-type ion implantation technology
The drift region 108 of doping.
Step 5: photoetching, which opens 107 injection region of p-well and carries out p-well 107, is infused in shape in the P-type semiconductor substrate 101
Into p-well 107, the p-well 107 and the drift region 108 contacts side surfaces or separated by a distance；The drift region oxygen 104a's
First side and the p-well 107 are at a distance.
Preferably, further included in the embodiment of the present invention and N-type ion implantation technology is added in the drift region 108 using photoetching
The step of forming N trap 106, the follow-up drain region 112b can be formed in the N traps 106.
Step 6: as illustrated in Figure 3 F, form gate dielectric layer 109 and polysilicon gate 110, preferably, the gate dielectric layer 109
For gate oxide.
The polysilicon gate 110 is extended to above the drift region 108 from the p-well 107 in the horizontal, by the polycrystalline
The p-well 107 that Si-gate 110 covers is used to form raceway groove, and the first side of the polysilicon gate 110 is located in the p-well 107
Side, second side are located above the oxygen 104a of the drift region.
As shown in Figure 3 G, isolation side walls are formed in the side of the polysilicon gate 110 using deposit plus dry etch process
111.In the embodiment of the present invention, one layer 2500 angstroms~3500 angstroms of silica is first deposited, dry etching is then carried out and forms institute
State isolation side walls 111.
Step 7: as illustrated in Figure 3 F, it is that source and drain is injected to form source region 112a and drain region 112b to carry out N+ injections, the source region
112a is formed in the p-well 107 and is formed at the first side autoregistration of the polysilicon gate 110, the drain region 112b
In the drift region 108, the second side of the field oxygen 104 and the drain region 112b are laterally contacted.
Step 8: as illustrated in Figure 3 F, carry out P+ and inject to form substrate draw-out area 113, the substrate draw-out area 113 is formed at
In the p-well 107 and for the p-well 107 to be drawn.In the embodiment of the present invention, the substrate draw-out area 113 and the source region
Include a field oxygen 104 between 112a；In other embodiments, the substrate draw-out area 113 and the source region 112a also can
For the structure laterally contacted.
Step 9: form interlayer film in the front of Semiconductor substrate 101.
Step 10: the contact hole 114 through the interlayer film is formed, the contact hole 114 source corresponding with bottom
The area 112a and substrate draw-out area 113, the drain region 112b and polysilicon gate 110 contact.
Source electrode, drain electrode are formed Step 11: forming front metal layer 115 at the top of the interlayer film and carrying out chemical wet etching
And grid, the source electrode pass through the contact hole 114 through the interlayer film and the source region 112a and the substrate draw-out area
113 contacts, the drain electrode are contacted by the contact hole 114 through the interlayer film and the drain region 112b, and the grid passes through
Contact hole 114 and the polysilicon gate 110 through the interlayer film contact.
The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these also should
It is considered as protection scope of the present invention.
Claims (16)
- A kind of 1. NLDMOS device, it is characterised in that including：The drift region of n-type doping, is formed in P-type semiconductor substrate；P-well, is formed in the P-type semiconductor substrate, the p-well and the drift region contacts side surfaces or separated by a distance；The polysilicon gate of the semiconductor substrate is formed at, the polysilicon gate and semiconductor substrate surface isolation have Gate dielectric layer, in the horizontal the polysilicon gate extended to from the p-well above the drift region, covered by the polysilicon gate The p-well be used for form raceway groove；The first side of the polysilicon gate is located above the p-well, second side is positioned at described Above drift region；By N+ district's groups into source region and drain region, the source region be formed in the p-well and and the polysilicon gate first side Autoregistration, the drain region are formed in the drift region；By P+ district's groups into substrate draw-out area, the substrate draw-out area is formed in the p-well and for the p-well to be drawn；Formed with a field oxygen above the drift region between the p-well and the drain region, this oxygen is made as drift region Oxygen, the second side and the drain region of the drift region oxygen laterally contact；The polysilicon gate extends to the drift region oxygen Top, the first side of the drift region oxygen are located at the bottom of the polysilicon gate and the first side and the institute of the drift region oxygen State p-well at a distance；The part oxygen of the top area of drift region first side of oxygen is removed and field oxygen is removed area filling and has replacement Dielectric layer, the substitute medium layer are more than the property of the field oxygen with the blocking capability to ion implanting or are situated between with opposite Electric constant is more than the property of the field oxygen；It is described using the property for being more than the field oxygen with the blocking capability to ion implanting Substitute medium layer reduces the doping concentration of the drift region of the first side bottom positioned at the drift region oxygen, so as to improve The breakdown voltage of NLDMOS device；Using the property for being more than the field oxygen with relative dielectric constant, the substitute medium layer makes Electric field strength in the drift region of the first side bottom of the drift region oxygen reduces, increase drift region electric field strength Distributing homogeneity, so as to improve the breakdown voltage of the NLDMOS device.
- 2. NLDMOS device as claimed in claim 1, it is characterised in that：Between the substrate draw-out area and the source region Formed with the field oxygen, the field oxygen, the outside in the drain region are also formed with the outside of the substrate draw-out area It is also formed with the field oxygen.
- 3. NLDMOS device as claimed in claim 1 or 2, it is characterised in that：The Semiconductor substrate is silicon substrate.
- 4. NLDMOS device as claimed in claim 3, it is characterised in that：The field oxygen is local field oxygen or shallow trench field oxygen, The material of the field oxygen is silica, and the material of the substitute medium layer is silicon nitride.
- 5. NLDMOS device as claimed in claim 1, it is characterised in that：The gate dielectric layer is gate oxide.
- 6. NLDMOS device as claimed in claim 1, it is characterised in that：In the P-type semiconductor substrate surface formed with p-type Epitaxial layer, is formed in outside the p-type in the p-type epitaxial layer bottom formed with n type buried layer, the drift region and the p-well Prolong in layer.
- 7. NLDMOS device as claimed in claim 1, it is characterised in that：In the Semiconductor substrate front formed with interlayer Film, at the top of the interlayer film formed with source electrode, the drain and gate formed by front metal layer, the source electrode by through The contact hole of the interlayer film and the source region and substrate draw-out area contact, the drain electrode is by through the interlayer film Contact hole and the drain contact, the grid pass through the contact hole through the interlayer film and the polysilicon gate and contact.
- 8. NLDMOS device as claimed in claim 1, it is characterised in that：A N trap is also formed with the drift region, it is described Drain region is formed in the N traps.
- 9. a kind of manufacture method of NLDMOS device, it is characterised in that include the following steps：Step 1: providing a P-type semiconductor substrate, field oxygen, one of them described field are formed in the P-type semiconductor substrate surface Oxygen is located above the drift region being subsequently formed, and makes this oxygen as drift region oxygen；Step 2: the part oxygen of the top area of drift region first side of oxygen is removed using lithographic etch process, it is described Second side of drift region field oxygen and the drain region being subsequently formed laterally contact, and the first side of the drift region oxygen, which is located at, to be subsequently formed Polysilicon gate bottom；Step 3: the field oxygen of the drift region oxygen is removed area filling substitute medium layer, the substitute medium layer has pair The blocking capability of ion implanting is more than the property of the field oxygen or is more than the property of the field oxygen with relative dielectric constant；Profit With the property for being more than the field oxygen with the blocking capability to ion implanting, the substitute medium layer makes positioned at the drift region The doping concentration of the drift region of first side bottom of oxygen reduces, so as to improve the breakdown voltage of NLDMOS device；Utilize tool There is the property that relative dielectric constant is more than the field oxygen, the substitute medium layer makes positioned at the first side bottom of the drift region oxygen Electric field strength in the drift region in portion reduces, the distributing homogeneity of increase drift region electric field strength, so as to improve described The breakdown voltage of NLDMOS device；Step 4: form the drift region of n-type doping in P-type semiconductor substrate；Step 5: photoetching opens p-well injection region and carries out p-well and be infused in the P-type semiconductor substrate to form p-well, the p-well With the drift region contacts side surfaces or separated by a distance；First side of the drift region oxygen and the p-well be separated by one section away from From；Step 6: formation gate dielectric layer and polysilicon gate, the polysilicon gate extend to the drift from the p-well in the horizontal Above area, the p-well covered by the polysilicon gate is used to form raceway groove, and the first side of the polysilicon gate is positioned at described P-well top, second side are located above the oxygen of the drift region；Step 7: carrying out N+ inject to form source region and drain region, the source region is formed in the p-well and and the polysilicon gate First side autoregistration, the drain region are formed in the drift region, and the second side of the field oxygen and the drain region laterally contact；Inject to form substrate draw-out area Step 8: carrying out P+, the substrate draw-out area is formed in the p-well and for by described in P-well is drawn.
- 10. the manufacture method of NLDMOS device as claimed in claim 9, it is characterised in that：In the substrate draw-out area and institute State and be also formed with the field oxygen between source region, the field oxygen, institute are also formed with the outside of the substrate draw-out area State and the field oxygen is also formed with the outside of drain region.
- 11. the manufacture method of the NLDMOS device as described in claim 9 or 10, it is characterised in that：The Semiconductor substrate is Silicon substrate.
- 12. the manufacture method of NLDMOS device as claimed in claim 11, it is characterised in that：The field oxygen for local field oxygen or Shallow trench field oxygen, the material of the field oxygen is silica, and the material of the substitute medium layer is silicon nitride.
- 13. the manufacture method of NLDMOS device as claimed in claim 9, it is characterised in that：The gate dielectric layer is gate oxidation Layer.
- 14. the manufacture method of NLDMOS device as claimed in claim 9, it is characterised in that：In the P-type semiconductor substrate table Face is all formed formed with p-type epitaxial layer in the p-type epitaxial layer bottom formed with n type buried layer, the drift region and the p-well In the p-type epitaxial layer.
- 15. the manufacture method of NLDMOS device as claimed in claim 9, it is characterised in that：It is also formed with the drift region One N trap, the drain region are formed in the N traps, and the N traps are formed after step 4 using N-type ion implanting.
- 16. the manufacture method of NLDMOS device as claimed in claim 9, it is characterised in that further include following steps：Step 9: form interlayer film in Semiconductor substrate front；Step 10: form the contact hole through the interlayer film, the corresponding source region of the contact hole and bottom and the lining Bottom draw-out area, the drain region and polysilicon gate contact；Source electrode, drain and gate are formed Step 11: forming front metal layer at the top of the interlayer film and carrying out chemical wet etching, The source electrode is contacted by the contact hole through the interlayer film and the source region and the substrate draw-out area, and the drain electrode is logical The contact hole through the interlayer film and the drain contact are crossed, the grid passes through the contact hole through the interlayer film and institute State polysilicon gate contact.
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| CN109860276B (en) * | 2019-02-14 | 2022-08-09 | 长江存储科技有限责任公司 | Semiconductor device and method of forming the same |
| CN115332324A (en) * | 2022-10-18 | 2022-11-11 | 广州粤芯半导体技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN117012835B (en) * | 2023-10-07 | 2024-01-23 | 粤芯半导体技术股份有限公司 | Laterally diffused metal oxide semiconductor device and method of manufacturing the same |
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| CN102130168A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Isolated LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
| CN102543738A (en) * | 2010-12-20 | 2012-07-04 | 上海华虹Nec电子有限公司 | High-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacture method for same |
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| KR100422393B1 (en) * | 2002-01-17 | 2004-03-11 | 한국전자통신연구원 | EDMOS device with the structure of lattice type drift region and method of manufacturing the same |
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| CN102130168A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Isolated LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof |
| CN102543738A (en) * | 2010-12-20 | 2012-07-04 | 上海华虹Nec电子有限公司 | High-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacture method for same |
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