CN102208414B - Super-junction channel metal oxide semiconductor field effect transistor and manufacturing method thereof - Google Patents
Super-junction channel metal oxide semiconductor field effect transistor and manufacturing method thereof Download PDFInfo
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- CN102208414B CN102208414B CN 201010158386 CN201010158386A CN102208414B CN 102208414 B CN102208414 B CN 102208414B CN 201010158386 CN201010158386 CN 201010158386 CN 201010158386 A CN201010158386 A CN 201010158386A CN 102208414 B CN102208414 B CN 102208414B
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Abstract
The invention discloses an improved super-junction channel metal oxide semiconductor field effect transistor and a manufacturing method thereof. The device effectively avoids the influence of imbalanced charge distribution, trapped charge and the like on device performance in the prior art, so that the device has higher performance characteristics. Meanwhile, the manufacturing cost of the device is effectively saved.
Description
Technical field
The present invention relates to a kind of device configuration and manufacture method of semiconductor power device.Be particularly related to device configuration and the manufacture method of super knot (super-junction) the groove metal oxide semiconductor field effect pipe (MOSFET) of a kind of RSO of having (Resurf Stepped Oxide) structure.
Background technology
In field of semiconductor, because super knot groove MOSFET device has higher puncture voltage and lower drain-source resistance (Rds), so it has more advantage than common groove MOSFET device in application.Yet, super knot groove MOSFET also Shortcomings in making and using.As everyone knows, the basic structure of super knot groove MOSFET device is that the method with Implantation forms P type and the N-type column doped structure that the interval replaces on heavily doped substrate, and it is both mutually close and be parallel to each other.But, in manufacturing process, this structure very easily is affected, for example in thermal environment subsequently, the factors such as trapped charge in diffusion motion and column doped region can occur again in the foreign ion between described P type and N-type column doped structure, these factors all can cause the CHARGE DISTRIBUTION in super knot groove MOSFET device uneven, thereby super knot groove MOSFET device performance is caused destructive impact.Especially, during lower than 200V, along with the narrowed width of column doped region, above-mentioned factor effect will be more obvious at voltage.
At U.S. Patent number 7,601, disclosed a kind of method in 597 and can avoid effectively that in above-mentioned P type and N-type column doped region, the problem of diffusion again occurs foreign ion.Concrete method is: after all diffusion processes (form sacrificial oxide layer after such as etching groove, form grid oxic horizon, form P type tagma and form n+ source region etc.) finish, then carry out the formation of P type column doped region.Adopt the super knot groove MOSFET of this method formation as shown in Figure 1A.
Yet above-mentioned the deficiencies in the prior art part is, the high cost of super knot groove MOSFET.At first, after the etching of carrying out groove, P type column doped region will obtain by the method for the extra P type epitaxial loayer of growth; Secondly, need to carry out the planarization of extra chemico-mechanical polishing (CMP) process to realize that it is surperficial after the growing P-type epitaxial loayer; Again, need to carry out twice groove etching (etching forms the groove of trench gate, another time etching form P type column doped region than deep trench).And these above-mentioned processes can roll up manufacturing cost and not be suitable for volume production.In addition, the trapped charge factor in the column doped region causes that the unbalanced problem of CHARGE DISTRIBUTION still is not resolved.
Disclosed respectively the structure of the limitation that is used for solving super knot groove MOSFET in the people's such as the people's such as M.A.Gajda article " Industrialization of Resurf SteppedOxide Technology for Power Transistors " and Xin Yang article " Tunable Oxide-Bypassed Trench Gate MOSFET Breaking the IdealSuper-junction MOSFET Performance Line at Equal Column Width ", as shown in Figure 1B and Fig. 1 C.Except technical name was had any different, Figure 1B was very similar with two kinds of structures shown in Fig. 1 C, was all to have adopted greater than the majority carrier concentration in conventional MOS FET epitaxial loayer to have lower Rds and higher puncture voltage in its epitaxial loayer.Meanwhile, Figure 1B and trench gate in the structure shown in Fig. 1 C all extend into the drift region and all are lined with the thicker grid oxic horizon of relative general super knot groove MOSFET at the sidewall of trench gate with the bottom.Both unique differences are, only has an epitaxial loayer in structure shown in Figure 1B, and have two epitaxial loayers in the structure shown in Fig. 1 C, be epitaxial loayer 1 and epitaxial loayer 2, wherein epitaxial loayer 1 is positioned at above heavily doped substrate, epitaxial loayer 2 is positioned at the top of epitaxial loayer 1, and near channel region, the majority carrier concentration of epitaxial loayer 1 is lower than epitaxial loayer 2.Due to do not exist P type and N-type column doped region mutually, thereby just do not have the unbalanced problem of CHARGE DISTRIBUTION in two kinds of structures shown in Figure 1B and Fig. 1 C, thereby solved the technology limitation in super knot groove MOSFET device.Yet two kinds of structures shown in Figure 1B and Fig. 1 C only just can demonstrate the characteristic that is superior to super knot groove MOSFET at voltage under less than the condition of 200V.That is to say, when bias voltage surpassed 200V, traditional super knot groove MOSFET device had than the lower Rds value of above-mentioned two kinds of structures, and the advantage of so above-mentioned both structures will not exist when bias voltage surpasses 200V.
Therefore, in field of semiconductor, especially in the Design and manufacture field of super knot groove MOSFET device, need to propose a kind of device configuration of novelty to solve above-mentioned difficulty and design limitation.
Summary of the invention
The present invention has overcome the shortcoming that exists in the prior art, and a kind of improved semiconductor power device is provided, thereby has effectively improved the CHARGE DISTRIBUTION imbalance problem of device, effectively reduces the production cost of device.
According to embodiments of the invention, the super knot groove metal oxide semiconductor field effect pipe (MOSFET) with a kind of RSO structure is provided, comprising:
(a) substrate of the first conduction type;
(b) epitaxial loayer of the first conduction type, this epitaxial loayer is positioned at the upper surface of described substrate, and the majority carrier concentration of this epitaxial loayer is lower than described substrate;
(c) a plurality of grooves are positioned at described epitaxial loayer, and extend down into described epitaxial loayer from the upper surface of described epitaxial loayer;
(d) the first insulating barrier covers inner surface partly under described groove;
(e) a plurality of source region electrode, each described source region electrode are filled in the lower part of each described groove and near described the first insulating barrier;
(f) the second insulating barrier covers the inner surface of part on described groove, and covers the top of described the first insulating barrier and described source region electrode, and the thickness of this second insulating barrier is less than the thickness of described the first insulating barrier;
(g) a plurality of gate electrodes, each described gate electrode are filled in upper part and close described second insulating barrier of each described groove;
(h) the first column doped region of a plurality of the first conduction types, be positioned at described epitaxial loayer, and the partial sidewall of close described groove and the degree of depth of this first column doped region in described epitaxial loayer are less than the degree of depth of described groove in described epitaxial loayer;
(i) the second column doped region of a plurality of the second conduction types, be positioned at described epitaxial loayer, near and surround described the first column doped region, and described the second column doped region is parallel to described the first column doped region;
(j) tagma of a plurality of the second conduction types is positioned at described epitaxial loayer, near the partial sidewall of described groove and cover the upper surface of described the first column doped region and described the second column doped region;
(k) source region of a plurality of the first conduction types, be positioned at active area, the partial sidewall of the upper surface in close described tagma and close described groove, and the majority carrier concentration in described source region is higher than described epitaxial loayer;
(l) the 3rd insulating barrier, the top of the described gate electrode of covering; With
(m) termination environment is positioned at described super knot groove metal oxide semiconductor field effect tube terminal place.
According to embodiments of the invention, another kind of super knot groove metal oxide semiconductor field effect pipe (MOSFET) with RSO structure is provided, comprising:
(a) substrate of the first conduction type;
(b) epitaxial loayer of the first conduction type, this epitaxial loayer is positioned at the upper surface of described substrate, and the majority carrier concentration of this epitaxial loayer is lower than described substrate;
(c) a plurality of grooves are positioned at described epitaxial loayer, and extend down into described epitaxial loayer from the upper surface of described epitaxial loayer;
(d) the first insulating barrier covers inner surface partly under described groove;
(e) the second insulating barrier covers inner surface partly on described groove, is connected with described the first insulating barrier, and the thickness of this second insulating barrier is less than the thickness of described the first insulating barrier;
(f) a plurality of gate electrodes, each described gate electrode are filled in each described groove and close described the first insulating barrier and described the second insulating barrier;
(g) the first column doped region of a plurality of the first conduction types, be positioned at described epitaxial loayer, and the partial sidewall of close described groove and the degree of depth of this first column doped region in described epitaxial loayer are less than the degree of depth of described groove in described epitaxial loayer;
(h) the second column doped region of a plurality of the second conduction types, be positioned at described epitaxial loayer, near and surround described the first column doped region, and described the second column doped region is parallel to described the first column doped region;
(i) tagma of a plurality of the second conduction types is positioned at described epitaxial loayer, near the partial sidewall of described groove and cover the upper surface of described the first column doped region and described the second column doped region;
(j) source region of a plurality of the first conduction types, be positioned at active area, the partial sidewall of the upper surface in close described tagma and close described groove, and the majority carrier concentration in described source region is higher than described epitaxial loayer;
(k) the 3rd insulating barrier, the top of the described gate electrode of covering; With
(l) termination environment is positioned at described super knot groove metal oxide semiconductor field effect tube terminal place.
In some preferred embodiments, the bottom of described groove does not arrive the contact-making surface of described substrate and described epitaxial loayer.In other preferred embodiments, the bottom of described groove is crossed the contact-making surface of described substrate and described epitaxial loayer and is extended down in described substrate, simultaneously, the bottom surface of described the first column doped region and described the second column doped region is near the contact-making surface of described substrate and described epitaxial loayer.
In some preferred embodiments, described super knot groove MOSFET also comprises: the snowslide enhanced doped regions of a plurality of the second conduction types, be positioned at described tagma, and between every two adjacent described source regions, the bottom of described snowslide enhanced doped regions is positioned at the below, bottom in described source region, simultaneously, the majority carrier concentration of described snowslide enhanced doped regions is higher than described tagma; The shallow junction contact doping district of a plurality of the second conduction types, upper surface near described tagma, this shallow junction contact doping district is positioned between every two adjacent described source regions and is formed at the top of described snowslide enhanced doped regions, simultaneously, the majority carrier concentration in described shallow junction contact doping district is higher than described snowslide enhanced doped regions.
In some preferred embodiments, when puncture voltage was less than or equal to 100V, described termination environment was made of guard ring, and described the 3rd insulating barrier covers described termination environment.In other preferred embodiments, during greater than 100V, described termination environment is made of guard ring and a plurality of ditch grooved ring with suspended voltage when puncture voltage, and described the 3rd insulating barrier covers the top of described termination environment.
In some preferred embodiments, described super knot groove MOSFET also comprises the source metal level, above described the 3rd insulating barrier and extend down between every two adjacent described the 3rd insulating barriers.
In some preferred embodiments, channel bottom described in described super knot groove MOSFET power device does not contact described substrate top surface and is positioned at the top of described substrate.In other preferred embodiments, channel bottom described in described super knot groove MOSFET power device is to downward-extension and contact the upper surface of described substrate.
In some preferred embodiments, described the first conduction type is N-type, and described the second conduction type is the P type.
According to embodiments of the invention, a kind of manufacture method of super knot groove metal oxide semiconductor field effect pipe (MOSFET) of the RSO of having structure is provided, comprising:
(a) in the operation of the epitaxial loayer of upper surface growth first conduction type of the substrate of described the first conduction type;
(b) form the operation of one deck barrier oxide layer at the upper surface of described epitaxial loayer;
(c) upper surface in described barrier oxide layer provides trench mask, forms subsequently the operation of a plurality of grooves with the method for dried oxygen etching and dried silicon etching;
(d) form sacrificial oxide layer and the operation that removes this sacrificial oxide layer at described grooved inner surface;
(e) form the operation of screen oxide at described grooved inner surface;
(f) carry out the angled Implantation of dopant of the second conduction type and the operation of carrying out the diffusion of this dopant above described groove;
(g) carry out the angled Implantation of dopant of the first conduction type and the operation of carrying out the diffusion of this dopant above described groove;
(h) form the operation of the first insulating barrier at the inner surface of described groove;
(i) polysilicon that deposit is adulterated above described the first insulating barrier forms the operation of source region electrode;
(j) return the operation of carving from described the first insulating barrier and the source region electrode that is located thereon, make described the first insulating barrier and the source region electrode on it only be positioned at the bottom of described groove, remove simultaneously described barrier oxide layer;
(k) operation of the upper surface of the inner surface of part and described the first insulating barrier and described source region electrode formation the second insulating barrier on described groove, the thickness of described the second insulating barrier is less than the thickness of described the first insulating barrier;
(l) operation of the polysilicon formation gate electrode of deposit doping above described the second insulating barrier;
(m) described gate electrode is returned the operation of carving, make described gate electrode fill the upper part of described groove;
(n) provide the operation of tagma mask at the upper surface of described epitaxial loayer;
(o) carry out the Implantation of dopant of the second conduction type and the operation of diffusion, form the tagma;
(p) remove described tagma mask and the operation of source region mask is provided at the upper surface of described epitaxial loayer;
(q) carry out the Implantation of dopant of the first conduction type and the operation of diffusion, form the source region; With
(r) remove described source region mask and in the operation of upper surface deposit the 3rd insulating barrier of described epitaxial loayer.
In some preferred embodiments, in the operation of described formation groove, the described barrier oxide layer of described groove break-through extends into described epitaxial loayer.In other preferred embodiments, the described barrier oxide layer of described groove break-through and described epitaxial loayer extend into described substrate.
In some preferred embodiments, the operation of described formation the first insulating barrier comprises thermal oxide growth or oxidation deposit.
In some preferred embodiments, the method at described time quarter comprises chemico-mechanical polishing (CMP) or plasma etching.
In some preferred embodiments, the manufacture method of the super knot groove MOSFET of the described RSO of having structure also comprises: provide the contact trench mask also to form the operation of contact zone with the method for dried oxygen etching on described the 3rd insulating barrier; The energetic ion that carries out the dopant of the second conduction type injects the operation that forms the snowslide enhanced doped regions; The Implantation that carries out the second conductivity type dopant forms the operation in shallow junction contact doping district.More preferably, also comprise: in the operation of described super knot groove metal oxide semiconductor field effect pipe deposited on top metal level; Provide the source metal mask also to form the operation of source metal with the method for metal etch.
In some preferred embodiments, before the operation that described tagma mask is provided, also comprise the Implantation of the dopant that the guard ring mask is provided and carries out the second conduction type and the operation of diffusion.
An advantage of the invention is, adopted the RSO structure to reduce the CHARGE DISTRIBUTION imbalance in super knot groove metal oxide semiconductor field effect pipe, the impact of the problems such as trapped charge on device performance makes device have better operating characteristic.
Another advantage of the present invention is that in manufacture process, P type and N-type column doped region have adopted the generation type of doping, and only use etching groove one time, the cost of manufacture of having simplified manufacturing process and effectively having saved device.
Description of drawings
The advantage of these and other execution modes of the present invention will be by below in conjunction with being described in detail as follows of accompanying drawing, wherein:
Figure 1A is the cutaway view of the super knot groove MOSFET of prior art announcement.
Figure 1B is the cutaway view of the groove MOSFET of prior art announcement.
Fig. 1 C is the cutaway view of the another kind of groove MOSFET of prior art announcement.
Fig. 2 A is the cutaway view of super knot groove MOSFET according to a particular embodiment of the invention.
Fig. 2 B is the cutaway view according to the super knot groove MOSFET of another specific embodiment of the present invention.
Fig. 2 C is the cutaway view according to the super knot groove MOSFET of another specific embodiment of the present invention.
Fig. 2 D is the cutaway view according to the super knot groove MOSFET of another specific embodiment of the present invention.
Fig. 2 E is the cutaway view according to the super knot groove MOSFET of another specific embodiment of the present invention.
Fig. 3 A is the cutaway view according to the super knot groove MOSFET of another specific embodiment of the present invention.
Fig. 3 B is the cutaway view according to the super knot groove MOSFET of another specific embodiment of the present invention.
Fig. 4 A-4G is the cutaway view according to the super knot groove MOSFET manufacturing process of the embodiment of the present invention shown in Fig. 2 E.
Embodiment
Fig. 2 A has disclosed the super knot of the N raceway groove groove MOSFET according to a preferred embodiment of the present invention, and the super knot of this N raceway groove groove MOSFET is made on N+ substrate 200, and N-type epitaxial loayer 202 is formed on described substrate 200.The super knot of this N raceway groove groove MOSFET device also comprises a plurality of grooves 203, its upper surface from described N-type epitaxial loayer 202 extends to described substrate 200 tops vertically downward, and wherein said groove 203 bottoms do not contact the contact-making surface of described substrate 200 and described epitaxial loayer 202.The inner surface of 203 times parts of described groove covers the first insulating barrier 204 and fills the polysilicon that adulterates and forms source region electrode 205.On described groove 203, the inner surface of part covers the second insulating barrier 207 and fills the polysilicon that adulterates and forms gate electrode 206, wherein said the second insulating barrier 207 covers the inner surface of part on described groove, and cover the upper surface of described the first insulating barrier 204 and described source region electrode 205, the thickness of this second insulating barrier is less than described the first insulating barrier.N-type column doped region 208 is formed between every two adjacent grooves 203, and is parallel to P type column doped region 209 in epitaxial loayer 202.Described super knot groove MOSFET also comprises P type tagma 210, and it is formed between every two adjacent grooves 203 and is positioned at described N-type column doped region 208 and the top of described P type column doped region 209.In addition, be positioned at 210 upper surface places, each P type tagma, have n+ source region 211.P+ snowslide enhanced doped regions 212 is formed in tagma 210, and between adjacent n+ source region 211.P++ type shallow junction contact doping district 213 form with tagma 210 in, also between adjacent n+ source region 211, be positioned at simultaneously the top of described P+ snowslide enhanced doped regions 212.Described super knot groove MOSFET also comprises the 3rd insulating barrier 214, and its top that is formed at described gate electrode 206 is to realize the insulation between gate electrode and source metal.
Fig. 2 B has disclosed according to another preferred embodiment of the present invention, it has similar structure to super knot groove MOSFET shown in Fig. 2 A, difference is shown in Fig. 2 B that the groove 303 of super knot groove MOSFET starts from the upper surface of described epitaxial loayer and extends into vertically downward substrate 300 inside, simultaneously, the source region electrode 305 that is positioned at groove 303 also extends down into substrate 300 inside.In addition, N-type column doped region 308 and P type column doped region 309 are also to downward-extension and contact substrate 300 and the upper surface of epitaxial loayer 302.
Fig. 2 C has disclosed according to another preferred embodiment of the present invention, and it has similar structure to super knot groove MOSFET shown in Fig. 2 A, difference be the super knot groove MOSFET shown in Fig. 2 C have by guard ring 415 consist of the termination environment.In addition, source metal 416 covers the 3rd insulating barrier 414 tops and extends down between every two adjacent described the 3rd insulating barriers.In active area, described source metal 416 has realized that it contacts with electricity between described p++ type shallow junction contact doping district 413 and described n+ source region 411; Near termination environment place, described source metal 416 has realized that it contacts with electricity between described p++ type shallow junction contact doping district 413.
Fig. 2 D has disclosed according to another preferred embodiment of the present invention; it has similar structure to super knot groove MOSFET shown in Fig. 2 C, and difference is that the super knot groove MOS FE shown in Fig. 2 D has the termination environment that is made of guard ring 515 and a plurality of ditch grooved ring 517 with suspended voltage.
Fig. 2 E has disclosed according to another preferred embodiment of the present invention; it has similar structure to super knot groove MOSFET shown in Fig. 2 B, and difference is that the super knot groove MOSFET shown in Fig. 2 E has the termination environment that is made of guard ring 615 and a plurality of ditch grooved ring 617 with suspended voltage.In addition, source metal 616 is above the 3rd insulating barrier 614 and extend down between every two adjacent described the 3rd insulating barriers.In active area, described source metal 616 has realized that it contacts with electricity between described p++ type shallow junction contact doping district 613 and described n+ source region 611; In the termination environment, described source metal 616 has realized that it contacts with electricity between described p++ type shallow junction contact doping district 613.
Fig. 3 A has disclosed according to another preferred embodiment of the present invention, it has similar structure to super knot groove MOSFET shown in Fig. 2 A, and difference is there is no the source region electrode in each groove 703 of the super knot groove MOSFET shown in Fig. 3 A and gate electrode 706 only.Wherein the inner surface of 703 times parts of groove covers the first insulating barrier 704, and on described groove 703, the inner surface of part covers the second insulating barrier 707, and the polysilicon of filling doping at described groove 703 forms gate electrode 706.The thickness of wherein said the second insulating barrier 707 is less than the first insulating barrier 704.
Fig. 3 B has disclosed according to another preferred embodiment of the present invention, it has similar structure to super knot groove MOSFET shown in Fig. 3 A, difference is that the groove 803 of the super knot groove MOSFET shown in Fig. 3 B starts from the upper surface of described epitaxial loayer and extends into vertically downward substrate 800 inside, simultaneously, the gate electrode 806 that is positioned at groove 803 also extends down into substrate 800 inside.In addition, N-type column doped region 808 and P type column doped region 809 are also to downward-extension and contact substrate 800 and the contact-making surface of epitaxial loayer 802.
Fig. 4 A to Fig. 4 G is the concrete making step of the preferred embodiment of the present invention shown in shop drawings 2E.As shown in Fig. 4 A, at first, N-type epitaxial loayer 602 is formed at N+ type substrate 600 upper surfaces.After this, the upper surface at described epitaxial loayer 602 forms barrier oxide layer 620.Subsequently trench mask is covered on oxide layer 620, form a plurality of grooves 603 with the method for dried oxygen etching and dried silicon etching, the wherein said groove 603 described oxide layers 620 of break-through, described epitaxial loayer 602 and extending in described substrate 600.
As shown in Figure 4 B, at first, in inner surface formation sacrificial oxide layer (not shown) and the defective by causing in removing this sacrificial oxide layer elimination etching process of groove 603.After this, the inner surface along described groove 603 forms screen oxide 621.Subsequently, to form P type column doped region 609, described P type column doped region is near described groove 603 and be positioned at described epitaxial loayer 602 with the method B Implanted ion of angled Implantation.
As shown in Fig. 4 C, inject arsenic ion or phosphonium ion to form N-type column doped region 608 with the method for angled Implantation, at this moment, P type column doped region 609 is compressed.Described N-type column doped region is near described groove 603 and be parallel to described P type bar shaped doped region 609.
As shown in Fig. 4 D, the method by thermal oxide growth or thick oxide layer deposit forms the first insulating barrier 604 in the inner surface of described groove 603.After this, the polysilicon in the interior filling doping of described groove 603 forms source region electrode 605.Subsequently, described the first insulating barrier and described source region electrode 605 are returned to carve to make reserve enough spaces in described groove to make the second insulating barrier and gate electrode.
As shown in Fig. 4 E, the second insulating barrier 607 is formed at the inner surface of upper part of described groove 603 and the top of described the first insulating barrier 604 and described source region electrode, and the thickness of described the second insulating barrier 607 is less than the first insulating barrier 604.After this, the polysilicon in the interior filling doping of described groove 603 forms gate electrode 606.Subsequently, with the method for chemico-mechanical polishing or ion etching, described gate electrode 606 is returned quarter.
Next, provide guard ring mask (not shown), carry out the Implantation of P type dopant, and through spreading to form guard ring 615 and a plurality of ditch grooved ring 617 with suspended voltage.After this, provide tagma mask (not shown), carry out the Implantation of P type dopant, and through diffusion to form P type tagma 610.Source region mask (not shown) is provided subsequently, carries out the Implantation of N-type dopant, and by diffuseing to form n+ source region 611.Described source region 611 near the majority carrier concentration in the upper surface in P type tagma 610 and described n+ source region 611 higher than described epitaxial loayer 602.
As shown in Fig. 4 F, at first, at deposited on top the 3rd insulating barrier 614 of super knot groove MOSFET, and provide thereon the contact mask, afterwards, with the method formation contact hole of dried oxygen etching.Subsequently, the method B Implanted ion that injects with energetic ion is to form P+ snowslide enhanced doped regions 612, after this continue to inject BF2 forming p++ shallow junction contact doping district 613 with the method for Implantation, described P++ shallow junction contact doping district 613 is formed at described snowslide enhanced doped regions 612 tops.
As shown in Fig. 4 G, deposited metal 616 is located at the upper surface of described the 3rd insulating barrier 614 and extends down into contact hole.After this, provide source metal mask (not shown), form source metal with the described metal level 616 of the method etching of metal etch, contact with electricity between described p++ shallow junction contact doping district 613 and described n+ source region 611 to realize it.
Although at this, various embodiment have been described, are appreciated that without departing from the spirit and scope of the present invention and can make various modifications to the present invention.For example, can form with method of the present invention the structure of its conduction type and the various semiconductor regions of opposite conduction type described in literary composition, but the modification of having done should be forgiven within the scope of protection of present invention.
Claims (17)
1. one kind has the super knot groove metal oxide semiconductor field effect pipe that reduces surface field ladder oxide structure, comprising:
The substrate of the first conduction type;
The epitaxial loayer of the first conduction type, this epitaxial loayer is positioned at the upper surface of described substrate, and the majority carrier concentration of this epitaxial loayer is lower than described substrate;
A plurality of grooves are positioned at described epitaxial loayer, and extend down into described epitaxial loayer from the upper surface of described epitaxial loayer;
The first insulating barrier covers inner surface partly under described groove;
A plurality of source regions electrode, each described source region electrode are filled in lower part and close described first insulating barrier of each described groove;
The second insulating barrier covers the inner surface of part on described groove, and covers the top of described the first insulating barrier and described source region electrode, and the thickness of this second insulating barrier is less than the thickness of described the first insulating barrier;
A plurality of gate electrodes, each described gate electrode are filled in upper part and close described second insulating barrier of each described groove;
The first column doped region of a plurality of the first conduction types is positioned at described epitaxial loayer, and the partial sidewall of close described groove and the degree of depth of this first column doped region in described epitaxial loayer are less than the degree of depth of described groove in described epitaxial loayer;
The second column doped region of a plurality of the second conduction types is positioned at described epitaxial loayer, flush around the side in the first column district and both bottom surfaces, and described the second column doped region is parallel to described the first column doped region;
The tagma of a plurality of the second conduction types is positioned at described epitaxial loayer, near the partial sidewall of described groove and cover the upper surface of described the first column doped region and described the second column doped region;
The source region of a plurality of the first conduction types is positioned at active area, the partial sidewall of the upper surface in close described tagma and close described groove, and the majority carrier concentration in described source region is higher than described epitaxial loayer;
The 3rd insulating barrier, the top of the described gate electrode of covering; With
The termination environment is positioned at the periphery of described active area.
2. one kind has the super knot groove metal oxide semiconductor field effect pipe that reduces surface field ladder oxide structure, comprising:
The substrate of the first conduction type;
The epitaxial loayer of the first conduction type, this epitaxial loayer is positioned at the upper surface of described substrate, and the majority carrier concentration of this epitaxial loayer is lower than described substrate;
A plurality of grooves are positioned at described epitaxial loayer, and extend down into described epitaxial loayer from the upper surface of described epitaxial loayer;
The first insulating barrier covers inner surface partly under described groove;
The second insulating barrier covers inner surface partly on described groove, is connected with described the first insulating barrier, and the thickness of this second insulating barrier is less than the thickness of described the first insulating barrier;
A plurality of gate electrodes, each described gate electrode are filled in each described groove and close described the first insulating barrier and described the second insulating barrier;
The first column doped region of a plurality of the first conduction types is positioned at described epitaxial loayer, and the partial sidewall of close described groove and the degree of depth of this first column doped region in described epitaxial loayer are less than the degree of depth of described groove in described epitaxial loayer;
The second column doped region of a plurality of the second conduction types is positioned at described epitaxial loayer, flush around the side in the first column district and both bottom surfaces, and described the second column doped region is parallel to described the first column doped region;
The tagma of a plurality of the second conduction types is positioned at described epitaxial loayer, near the partial sidewall of described groove and cover the upper surface of described the first column doped region and described the second column doped region;
The source region of a plurality of the first conduction types is positioned at active area, the partial sidewall of the upper surface in close described tagma and close described groove, and the majority carrier concentration in described source region is higher than described epitaxial loayer;
The 3rd insulating barrier, the top of the described gate electrode of covering; With
The termination environment is positioned at the periphery of described active area.
3. reduction surface field ladder oxide according to claim 1 and 2 surpasses knot groove metal oxide semiconductor field effect pipe, and the bottom of wherein said groove does not arrive the contact-making surface of described substrate and described epitaxial loayer.
4. reduction surface field ladder oxide according to claim 1 and 2 surpasses knot groove metal oxide semiconductor field effect pipe, the bottom of wherein said groove is crossed the contact-making surface of described substrate and described epitaxial loayer and is extended down in described substrate, simultaneously, the bottom surface of described the first column doped region and described the second column doped region is near the contact-making surface of described substrate and described epitaxial loayer.
5. reduction surface field ladder oxide according to claim 1 and 2 surpasses knot groove metal oxide semiconductor field effect pipe, wherein also comprises:
The snowslide enhanced doped regions of a plurality of the second conduction types, be positioned at described tagma, and between every two adjacent described source regions, the bottom of described snowslide enhanced doped regions is positioned at the below, bottom in described source region, simultaneously, the concentration of the majority carrier of described snowslide enhanced doped regions is higher than described tagma;
The shallow junction contact doping district of a plurality of the second conduction types, upper surface near described tagma, this shallow junction contact doping district is positioned between every two adjacent described source regions and is formed at the top of described snowslide enhanced doped regions, simultaneously, the majority carrier concentration in described shallow junction contact doping district is higher than described snowslide enhanced doped regions.
6. reduction surface field ladder oxide according to claim 1 and 2 surpasses knot groove metal oxide semiconductor field effect pipe; wherein when puncture voltage is less than or equal to 100V; described termination environment is made of guard ring, and described the 3rd insulating barrier covers described termination environment.
7. reduction surface field ladder oxide according to claim 1 and 2 surpasses knot groove metal oxide semiconductor field effect pipe; wherein when puncture voltage during greater than 100V; described termination environment is made of guard ring and a plurality of ditch grooved ring with suspended voltage, and described the 3rd insulating barrier covers described termination environment.
8. reduction surface field ladder oxide according to claim 1 and 2 surpasses knot groove metal oxide semiconductor field effect pipe, wherein also comprises:
Source metal is above described the 3rd insulating barrier and extend down between every two adjacent described the 3rd insulating barriers.
9. reduction surface field ladder oxide according to claim 1 and 2 surpasses knot groove metal oxide semiconductor field effect pipe, and wherein said the first conduction type is N-type, and described the second conduction type is the P type.
10. manufacture method with the super knot groove metal oxide semiconductor field effect pipe that reduces surface field ladder oxide structure comprises:
Operation at the epitaxial loayer of upper surface growth first conduction type of the substrate of described the first conduction type;
Form the operation of one deck barrier oxide layer at the upper surface of described epitaxial loayer;
Upper surface in described barrier oxide layer provides trench mask, forms subsequently the operation of a plurality of grooves with the method for dried oxygen etching and dried silicon etching;
Form sacrificial oxide layer and the operation that removes this sacrificial oxide layer at described grooved inner surface;
Form the operation of screen oxide at described grooved inner surface;
Carry out the angled Implantation of dopant of the second conduction type and the operation of carrying out the diffusion of this dopant above described groove;
Carry out the angled Implantation of dopant of the first conduction type and the operation of carrying out the diffusion of this dopant above described groove;
Form the operation of the first insulating barrier at the inner surface of described groove;
The polysilicon of deposit doping forms the operation of source region electrode above described the first insulating barrier;
Described the first insulating barrier and the source region electrode that is located thereon are returned the operation of carving, make described the first insulating barrier and the source region electrode on it only be positioned at the bottom of described groove, remove simultaneously described barrier oxide layer;
The upper surface of the inner surface of part and described the first insulating barrier and described source region electrode forms the operation of the second insulating barrier on described groove, and the thickness of described the second insulating barrier is less than described the first insulating barrier;
The polysilicon of deposit doping forms the operation of gate electrode above described the second insulating barrier;
Described gate electrode is returned the operation of carving, make described gate electrode fill the upper part of described groove;
The operation of tagma mask is provided at the upper surface of described epitaxial loayer;
Carry out the Implantation of dopant of the second conduction type and the operation of diffusion, form the tagma;
Remove described tagma mask and the operation of source region mask is provided at the upper surface of described epitaxial loayer;
Carry out the Implantation of dopant of the first conduction type and the operation of diffusion, form the source region; With
Remove described source region mask and in the operation of upper surface deposit the 3rd insulating barrier of described epitaxial loayer.
11. the manufacture method of the super knot of reduction surface field ladder oxide according to claim 10 groove metal oxide semiconductor field effect pipe wherein forms in the operation of described groove, the described barrier oxide layer of described groove break-through extends into described epitaxial loayer.
12. the manufacture method of the super knot of reduction surface field ladder oxide according to claim 10 groove metal oxide semiconductor field effect pipe, wherein form in the operation of described groove, the described barrier oxide layer of described groove break-through and described epitaxial loayer extend into described substrate.
13. the manufacture method of the super knot of reduction surface field ladder oxide according to claim 10 groove metal oxide semiconductor field effect pipe, the formation method of wherein said the first insulating barrier comprises thermal oxide growth or oxidation deposit.
14. the manufacture method of the super knot of reduction surface field ladder oxide according to claim 10 groove metal oxide semiconductor field effect pipe, the method at wherein said time quarter comprises chemico-mechanical polishing or plasma etching.
15. the manufacture method of the super knot of reduction surface field ladder oxide according to claim 10 groove metal oxide semiconductor field effect pipe wherein also comprises:
Provide the contact mask also to form the operation of contact zone with the method for dried oxygen etching on described the 3rd insulating barrier;
The energetic ion that carries out the dopant of the second conduction type injects the operation that forms the snowslide enhanced doped regions;
The Implantation that carries out the dopant of the second conduction type forms the operation in shallow junction contact doping district.
16. the manufacture method of the super knot of reduction surface field ladder oxide according to claim 10 groove metal oxide semiconductor field effect pipe; wherein before the tagma mask is provided, also comprise the Implantation of the dopant that the guard ring mask first is provided and carries out the second conduction type and the operation of diffusion.
17. the manufacture method of the super knot of reduction surface field ladder oxide according to claim 15 groove metal oxide semiconductor field effect pipe wherein also comprises:
Operation at described super knot groove metal oxide semiconductor field effect pipe deposited on top metal level;
Provide the source metal mask also to form the operation of source metal with the method for metal etch.
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| CN103137698B (en) * | 2011-11-23 | 2016-04-27 | 力士科技股份有限公司 | A kind of mos field effect transistor and manufacture method |
| CN103137660B (en) * | 2011-11-30 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Super junction powder device terminal structure |
| CN102610643B (en) * | 2011-12-20 | 2015-01-28 | 成都芯源系统有限公司 | Trench MOSFET device |
| US8564058B1 (en) * | 2012-08-07 | 2013-10-22 | Force Mos Technology Co., Ltd. | Super-junction trench MOSFET with multiple trenched gates in unit cell |
| CN102881595B (en) * | 2012-08-17 | 2015-10-28 | 西安龙腾新能源科技发展有限公司 | A kind of manufacture method of super-junction high-voltage power device |
| CN104409334B (en) * | 2014-11-06 | 2017-06-16 | 中航（重庆）微电子有限公司 | A kind of preparation method of superjunction devices |
| CN106298533A (en) * | 2015-06-08 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of semiconductor device and semiconductor device |
| CN105655402B (en) * | 2016-03-31 | 2019-11-19 | 西安龙腾新能源科技发展有限公司 | Low pressure super node MOSFET terminal structure and its manufacturing method |
| CN107482049B (en) * | 2017-08-07 | 2020-03-31 | 电子科技大学 | Super-junction VDMOS device |
| CN110416285B (en) * | 2019-07-31 | 2024-06-07 | 电子科技大学 | Super junction power DMOS device |
| CN110993710B (en) * | 2019-12-30 | 2021-11-02 | 上海集成电路研发中心有限公司 | Single-photon avalanche diode and preparation method thereof |
| CN117242577A (en) * | 2022-04-14 | 2023-12-15 | 苏州龙驰半导体科技有限公司 | Transistor device and method of manufacturing transistor device |
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