CN102280487B - Power MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) device of novel groove structure and manufacture method thereof - Google Patents
Power MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) device of novel groove structure and manufacture method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 230000005669 field effect Effects 0.000 title abstract 2
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 152
- 239000002184 metal Substances 0.000 claims abstract description 94
- 229910052751 metal Inorganic materials 0.000 claims abstract description 94
- 239000010410 layer Substances 0.000 claims description 265
- 230000001413 cellular effect Effects 0.000 claims description 115
- 239000000758 substrate Substances 0.000 claims description 67
- 239000000463 material Substances 0.000 claims description 43
- 239000002210 silicon-based material Substances 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000002347 injection Methods 0.000 claims description 18
- 239000007924 injection Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 13
- 230000012010 growth Effects 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 10
- 230000005684 electric field Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 238000012423 maintenance Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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Abstract
The invention relates to a power MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) device of a novel groove structure and a manufacture method thereof. The unit cell of the element zone of the power MOSFET device adopts groove structure; an insulating oxide layer is arranged in the unit cell groove; the thickness of a second isolated gate oxide layer in the unit cell groove is more than the thickness of a first isolated gate oxide layer; conductive polysilicon is deposited in the cell unit groove; the extending distance of the first conductive polysilicon is more than the extending distance of the second conductive polysilicon in the unit cell groove; the groove mouth of the unit cell groove is covered by an insulating medium layer; a source electrode contact hole is filled with second contract hole filling metal; the second contract hole filling metal, a first conductive type filling zone and a second conductive type layer are in ohmic contact; source electrode metal is arranged above the unit cell groove; the source electrode metal and the second contact hole filling metal are electrically connected; and the first conductive polysilicon, the source electrode metal and the like are in potential connection. The power MOSFET device has the advantages of low conduction resistance, small grid leak electric charge Qgd, low switching speed, low switching loss, simple technology and low cost.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, especially a kind of power MOSFET device of Novel groove structure and manufacture method thereof belong to the technical field of semiconductor device.
Background technology
Super knot (Super Junction) theory and super-junction structure have been widely used in the middle of the multiple power MOSFET device, especially in the planar power MOSFET of 500V to 900V device series, become the main flow in this voltage series product, this mainly is because have the common power MOSFET of power MOSFET contrast of super-junction structure, its feature conducting resistance (product of conducting resistance and chip active region area) reduces greatly, switching speed significantly promotes, thereby reduced the power consumption of the machine system that uses this product, significantly promoted efficiency.
The most important condition of the existing super-junction structure power MOSFET device voltage endurance capability of impact and stability is the charge balance that consists of the P-N post of super-junction structure, specifically, only have when the net charge in P post and the N post equates, the P-N post could exhaust with withstand voltage the most fully.And the direct factor that affects P-N post charge balance comprises impurity concentration, the pattern of P post and N post.For the lower power MOSFET device of voltage, in order to improve the cellular integrated level of device, reduce conducting resistance, usually adopt the structure cell of groove shape, groove type power MOS FET(Trench MOSFET such as 60V to 250V), because the drain-source breakdown voltage (BVdss) of device is not high, therefore, the epilayer resistance rate of making device is smaller, the impurities concentration ratio is higher, if use the super-junction structure of existing P-N post in such devices, then also the p type impurity doped in concentrations profiled of P post denseer just can will be guaranteed withstand voltage, and the requirement of denseer doping all has larger difficulty for the existing process that forms the P post.At present reported and be widely used in the manufacturing process that the process that forms super knot P-N post comprises repeatedly extension, in the method, the P post is by repeatedly photoetching, repeatedly Implantation and the formation of high temperature knot, when the p type impurity of P post is denseer, final P cylindricality looks can be very easy to be subjected to the impact of alignment precision and the high temperature knot of each photoetching, thereby have reduced voltage endurance capability and the consistency of device; The process that another kind is used to form super knot P-N post comprises the manufacturing process that the deep trench extension is filled, in the method, the P post forms by deep plough groove etched and P type extension filling groove, for the groove with larger depth-to-width ratio, will fill the high extension of doping content in groove, also be to be difficult to realize.In sum, above-mentioned two kinds that reported and be widely used in high-voltage power MOSFET device the process that forms P-N post super-junction structure and be difficult in the mesolow power MOSFET device, implement and promote.
Publication number is that the Chinese patent application of CN 101246904 à discloses a kind of " semiconductor device and manufacture method thereof ", and its accompanying drawing 1 is its cross-sectional view; Propose in the file to come to injecting the p type impurity ion between the cellular of two groove structures by high-octane Implantation repeatedly, wherein the energy of each Implantation is different, thereby forms the P rod structure with certain depth by Implantation repeatedly.But there is following problem in the groove type power MOS FET that described CN 101246904 à publication applications have super-junction structure:
1, adopting repeatedly, the mode of macro-energy Implantation forms the P post, because injecting the ability of ceiling capacity is determined by implanter, and the maximum Implantation Energy of the existing implanter of commonly using is relatively limited, therefore, the degree of depth of P post can't be too dark, for example uses 1.5Mev B Implanted ion, and the degree of depth generally is about about 3 μ m, like this, the degree of depth of P post has just restricted the voltage endurance capability of device.
2, because device adopts the groove structure cell, spacing between adjacent cellular groove is smaller, therefore, the side direction of following when macro-energy is injected is injected and the rear final high temperature knot of injection all can and distribute near the p type impurity concentration the trenched side-wall of P post both sides produces the possibility of considerable influence, bring greater risk will for like this parameter characteristics such as cut-in voltage of device, reduce device reliability and consistency.
3, the same with traditional groove type power MOS FET device, its channel bottom zone still is positioned in the middle of the N-type epitaxial loayer, specifically, the bottom that is the grid conductive polycrystalline silicon of filling in the groove still is positioned in the middle of the N-type epitaxial loayer, and conductive polycrystalline silicon is consistent and thinner with the insulated gate oxidated layer thickness between the N-type epitaxial loayer, therefore, the charge or discharge charge Q gd between the grid leak in conducting or closing process compares with the Qgd of traditional groove type power MOS FET when device, not be improved significantly, like this, the switching speed of device and switching loss do not improve yet.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of power MOSFET device and manufacture method thereof of Novel groove structure is provided, its conducting resistance is low, and gd is little for the grid leak charge Q, and switching speed is fast, switching loss is low, and technique simply reaches with low cost.
According to technical scheme provided by the invention, the power MOSFET device of described Novel groove structure, on the top plan view of described MOSFET device, comprise the element region and the terminal protection district that are positioned at semiconductor substrate, described terminal protection district is positioned at the outer ring of element region, and the terminal protection district is around the embracing element district; Comprise the cellular that some rules are arranged and are parallel to each other and are arranged in parallel in the element region; On the cross section of described MOSFET device, semiconductor substrate has the first corresponding interarea and the second interarea, comprise the first conductive type epitaxial layer of the first conductivity type substrate and described the first conductivity type substrate of adjacency between described the first interarea and the second interarea, the top in the first conductive type epitaxial layer is provided with the second conductive type layer; Its innovation is:
On the cross section of described MOSFET device, the cellular of element region adopts groove structure, described cellular groove is positioned at the second conductive type layer, and by the first interarea of semiconductor substrate to downward-extension, the degree of depth stretches in the first conductive type epitaxial layer of described the second conductive type layer below; The superficial growth of described cellular trench wall has insulating oxide, described insulating oxide comprises the first insulated gate oxide layer and the second insulated gate oxide layer, described the first insulated gate oxide layer growth is in the top of cellular trenched side-wall, the second insulated gate oxide layer growth is in the bottom of cellular groove and cover bottom and the bottom of cellular trenched side-wall, the thickness of the second insulated gate oxide layer is greater than the thickness of the first insulated gate oxide layer, and the first insulated gate oxide layer is connected up and down with the second insulated gate oxide layer;
On the cross section of described MOSFET device, be deposited with conductive polycrystalline silicon in the cellular groove, described conductive polycrystalline silicon comprises the first conductive polycrystalline silicon and the second conductive polycrystalline silicon, described the first conductive polycrystalline silicon and the second conductive polycrystalline silicon extend downward the below of the second conductive type layer by the top of cellular groove, and the first conductive polycrystalline silicon distance of extending in cellular groove distance of extending greater than the second conductive polycrystalline silicon; The first conductive polycrystalline silicon is positioned at the center of cellular groove, the second conductive polycrystalline silicon is positioned at the both sides of the first conductive polycrystalline silicon, by the isolation of the 3rd insulated gate oxide layer, described the 3rd insulated gate oxide layer is connected up and down with the second insulated gate oxide layer between the first conductive polycrystalline silicon and the second conductive polycrystalline silicon; Isolate by the first insulated gate oxide layer between the second conductive polycrystalline silicon and cellular trench wall;
On the cross section of described MOSFET device, outer wall top corresponding between adjacent cellular groove is all with the first conduction type injection region; The notch of cellular groove is covered by insulating medium layer, the both sides of cellular groove are provided with the source electrode contact hole, be filled with the second contact hole in the described source electrode contact hole and fill metal, described the second contact hole is filled metal and the first conduction type injection region and the second conductive type layer ohmic contact; Cellular groove top is provided with source metal, and described source metal is covered in insulating medium layer and the second contact hole is filled on the metal, and source metal and the second contact hole are filled metal and be electrically connected; The first conductive polycrystalline silicon is connected with the source metal equipotential.
On the cross section of described MOSFET device, the top of cellular groove is provided with the first contact hole, and described the first contact hole is extended downward on the first conductive polycrystalline silicon by the insulating medium layer surface; Be provided with the first contact hole in the first contact hole and fill metal; The first conductive polycrystalline silicon is filled metal by the first contact hole and is connected with the source metal equipotential.
The second interarea of described semiconductor substrate is provided with drain metal.Described the first conductive polycrystalline silicon and source metal connect into zero potential.
A kind of power MOSFET device manufacture method of Novel groove structure, the manufacture method of described power MOSFET comprises the steps:
A, provide the semiconductor substrate with two relative interareas, described semiconductor substrate comprises the first conductivity type substrate and is positioned at the first conductive type epitaxial layer of described the first conductivity type substrate top, the surface of the first conductive type epitaxial layer forms the first interarea of semiconductor substrate, and the surface of the first conductivity type substrate forms the second interarea of semiconductor substrate;
B, on the first interarea of above-mentioned semiconductor substrate, the deposit hard mask layer;
C, optionally shelter and the etching hard mask layer, form the hard mask window of etching groove;
D, utilize above-mentioned hard mask window, by the anisotropic dry etch semiconductor substrate, form groove at the first interarea in the first conductive type epitaxial layer of semiconductor substrate, the degree of depth of described groove is less than the thickness of the first conductive type epitaxial layer;
E, remove the hard mask layer on above-mentioned the first interarea, and at the first interarea and the trench wall first insulative oxide material layer of growing, and form the first conductive polycrystalline silicon deposit hole in the center of cellular groove;
F, on above-mentioned the first interarea deposit the first conductive polycrystalline silicon material layer, described the first conductive polycrystalline silicon layer of material covers and is filled in the first conductive polycrystalline silicon deposit hole on the first insulative oxide material layer;
G, remove the first conductive polycrystalline silicon material layer on the first interarea, obtain being positioned at the first conductive polycrystalline silicon of cellular groove;
H, wet etching are removed the first insulative oxide material layer on the first interarea, remove simultaneously the first insulative oxide material layer on cellular trench wall top, obtain being positioned at the second insulated gate oxide layer of cellular groove bottom;
I, at the first interarea of above-mentioned semiconductor substrate growth the second insulative oxide material layer, described the second insulative oxide material layer is covered on the first interarea, and be covered in cellular groove upper inside wall, and obtain coating the 3rd insulated gate oxide layer on the first conductive polycrystalline silicon top; The second insulative oxide material interlayer on the 3rd insulated gate oxide layer and the cellular trenched side-wall forms the second conductive polycrystalline silicon deposit hole;
J, at the first interarea deposit second conductive polycrystalline silicon material layer of above-mentioned semiconductor substrate, described the second conductive polycrystalline silicon layer of material covers and is filled in the second conductive polycrystalline silicon deposit hole on the second insulative oxide material layer and the 3rd insulated gate oxide layer;
K, etching are removed the second conductive polycrystalline silicon material layer and the second insulative oxide material layer on above-mentioned the first interarea, the second conductive polycrystalline silicon that obtains being positioned at the first insulated gate oxide layer on cellular trenched side-wall top and be positioned at the second conductive polycrystalline silicon deposit hole;
L, on above-mentioned the first interarea, autoregistration Implantation the second conductive type impurity ion, and the second conductive type layer by high temperature knot forming element district, the degree of depth of the second conductive type layer in the first conductive type epitaxial layer in the described element region is less than the second conductive polycrystalline silicon distance to downward-extension in the cellular groove;
M, on above-mentioned the first interarea, carry out the source region photoetching, and inject the first conductive type impurity ion of high concentration, by the first conduction type injection region in high temperature knot forming element district;
N, on above-mentioned the first interarea, the deposit insulating medium layer, described insulating medium layer covers the first interarea of semiconductor substrate;
O, above-mentioned insulating medium layer is carried out contact hole photoetching and etching, all form the source electrode contact hole in the both sides of cellular groove, and obtain being positioned at cellular groove notch top first contact hole corresponding with the first conductive polycrystalline silicon;
P, filling contact hole is filled metal in above-mentioned the first contact hole and source electrode contact hole, and the first contact hole that obtains being positioned at the first contact hole is filled metal and is positioned at the second contact hole filling metal of source electrode contact hole; The second contact hole is filled the first conduction type injection region and the second conductive type layer ohmic contact of metal and its below, and the first contact hole is filled the metal first conductive polycrystalline silicon ohmic contact corresponding with its below;
Q, on above-mentioned insulating medium layer the deposit source metal, described source metal and the first contact hole are filled metal, the second contact hole is filled metal and all connected into equipotential;
R, on the second interarea of above-mentioned semiconductor substrate the deposit drain metal.
Described hard mask layer is that LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
Described insulating medium layer is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
Described the first contact hole fills metal and the second contact hole filling metal is aluminium, copper or tungsten.The thickness of the first insulated gate oxide layer in the described cellular groove is 200-1200.
The thickness of the second insulated gate oxide layer in the described cellular groove is 3000-10000.
Described " the first conduction type " and " the second conduction type " are among both, and for N-type MOSFET device, the first conduction type refers to N-type, and the second conduction type is the P type; For P type MOSFET device, the first conduction type is just in time opposite with type and the N type semiconductor device of the second conduction type indication.
Advantage of the present invention:
1, at element region, be provided with the first conductive polycrystalline silicon in the cellular groove, wherein the first conductive polycrystalline silicon degree of depth is darker, its part below the second conductive type layer is coated by the second thicker insulating oxide, and the first conductive polycrystalline silicon maintenance zero potential that is connected with source metal, when device withstand voltage, can produce because of charge inducing depletion layer in the adjacent cellular groove, support device withstand voltage, so just changed the withstand voltage situation of P-N knot that conventional groove type power MOSFET only relies on the second conductive type layer and the first conductive type epitaxial layer to consist of, therefore, under the prerequisite that satisfies with the identical withstand voltage needs of conventional groove type power MOSFET device, the first conductive type epitaxial layer resistivity in the power MOSFET device of the present invention just can improve greatly, thereby greatly reduces the conducting resistance of device.
2, in structure of the present invention, because the second conductive polycrystalline silicon is as the grid in the MOSFET structure, the area that itself and the first conductive type epitaxial layer overlap mutually is very limited, therefore, device open or turn off process in charge or discharge charge Q gd between the grid leak very little, so just greatly improve the switching speed of device, reduced the switching loss of device.
3, in structure of the present invention, the manufacturing process that forms structure cell all is that the operational characteristic by means of widely used semiconductor fabrications realizes, does not increase process implementing difficulty and cost, therefore, is beneficial to and promotes and batch production.
4, owing to the feature conducting resistance that has improved device, and manufacturing process is simple, and therefore, the chip area of device can suitably dwindle, thereby has reduced the manufacturing cost of device, has improved cost performance.
Description of drawings
Fig. 1 is structural representation of the present invention.
Fig. 2 ~ Figure 16 is power MOSFET device implementation processing step cutaway view of the present invention, wherein:
Fig. 2 is the cutaway view of semiconductor substrate.
Fig. 3 is the cutaway view after the hard mask open of formation.
Fig. 4 is the cutaway view behind the formation groove.
Fig. 5 is the cutaway view behind deposit the first insulative oxide material layer.
Fig. 6 is the cutaway view behind deposit the first conductive polycrystalline silicon material layer.
Fig. 7 is the cutaway view behind formation the first conductive polycrystalline silicon.
Fig. 8 is the cutaway view after formation the second insulated gate oxide layer.
Fig. 9 is the cutaway view behind growth the second insulative oxide material layer.
Figure 10 is the cutaway view behind deposit the second conductive polycrystalline silicon material layer.
Figure 11 is the cutaway view behind formation the first insulated gate oxide layer and the second conductive polycrystalline silicon.
Figure 12 is the cutaway view after formation the second conductive type layer.
Figure 13 is the cutaway view behind formation the first conduction type injection region.
Figure 14 is the cutaway view behind formation the first contact hole and the source electrode contact hole.
Figure 15 is the cutaway view behind the deposit source metal.
Figure 16 is the cutaway view after the deposit drain metal.
Figure 17 is the withstand voltage Electric Field Distribution schematic diagram of common groove power MOSFET device and groove power MOSFET device of the present invention, wherein:
Figure 17-a is the withstand voltage Electric Field Distribution schematic diagram of common groove power MOSFET device;
Figure 17-b is the withstand voltage Electric Field Distribution schematic diagram of groove power MOSFET device of the present invention.
Figure 18 is the withstand voltage current-voltage measured curve of drain-source (I-V Curve) of common 150V groove power MOSFET device and 150V groove power MOSFET device of the present invention.
Embodiment
The invention will be further described below in conjunction with concrete drawings and Examples.
Such as Fig. 1 ~ shown in Figure 16: take the N-type power MOSFET device as example, the present invention includes N+ substrate 1, N-type epitaxial loayer 2, N+ injection region 3, the second contact hole is filled metal 4, the first contact hole is filled metal 5, source metal 6, insulating medium layer 7, the first contact hole 8, source electrode contact hole 9, P trap layer 10, the first insulated gate oxide layer 11, drain metal 12, cellular groove 13, the 3rd insulated gate oxide layer 14, the second conductive polycrystalline silicon 15, the second insulated gate oxide layer 16, the first conductive polycrystalline silicon 17, the first interarea 18, the second interarea 19, hard mask layer 20, hard mask layer window 21, the first conductive polycrystalline silicon deposit hole 22, the first insulative oxide material layer 23, the first conductive polycrystalline silicon material layer 24, the second insulative oxide material layer 25, the second conductive polycrystalline silicon material layer 26 and the second conductive polycrystalline silicon deposit hole 27.
Such as Fig. 1 and shown in Figure 16: as described on the top plan view of power MOSFET device; comprise the element region that is positioned at the semiconductor substrate center and be positioned at the terminal protection district of described element region outer ring; described terminal protection district surrounds the encircling element district, comprises in the described element region that some rules are arranged and the cellular of connection parallel with one another.The element region structure that has only represented power MOSFET device among Fig. 1 and Figure 16, power MOSFET device can adopt existing conventional terminal protection plot structure.On the cross section of described power MOSFET device, described semiconductor substrate comprises N-type epitaxial loayer 2 and is positioned at the N+ substrate 1 of described N-type epitaxial loayer 2 belows, and described N+ substrate 1 is in abutting connection with N-type epitaxial loayer 2, and the concentration of N+ substrate 1 is greater than the concentration of N-type epitaxial loayer 2.Semiconductor substrate has two corresponding interareas, and described two interareas are the first interarea 18 and the second interarea 19; The surface of N-type epitaxial loayer 2 forms the first interarea 18, and the surface of N+ substrate 1 forms the second interarea 19, the first interareas 18 and the 19 corresponding distributions of the second interarea.Top in the N-type epitaxial loayer 2 is provided with P trap layer 10, and described P trap layer 10 runs through the N-type epitaxial loayer 2 of element region.
On the cross section of described power MOSFET device, the cellular of element region adopts groove structure, and particularly, element region comprises cellular groove 13.Described cellular groove 13 is positioned at P trap layer 10, cellular groove 13 extends to the second interarea 19 directions from the first interarea 18 of N-type epitaxial loayer 2, cellular groove 13 extends in the N-type epitaxial loayer 2 of P trap layer 10 below, and the distance of cellular groove 13 extensions is less than the thickness of N-type epitaxial loayer 2.The growth of cellular groove 13 inner wall surface has insulating oxide, described insulating oxide to comprise the first insulated gate oxide layer 11 and the second insulated gate oxide layer 16; Described the second insulated gate oxide layer 16 is positioned at the bottom of cellular groove 13, and is covered in sidewall and the lower surface of cellular groove 13 bottoms; The first insulated gate oxide layer 11 grows in the sidewall on cellular groove 13 tops.The first insulated gate oxide layer 11 is connected at the length direction of cellular groove 13 with the second insulated gate oxide layer 16, namely the bottom of the first insulated gate oxide layer 11 is connected with the top of the second insulated gate oxide layer 16, and the thickness of the second insulated gate oxide layer 16 is greater than the thickness of the first insulated gate oxide layer 11.
On the cross section of described power MOSFET device, be deposited with the first conductive polycrystalline silicon 17 in the cellular groove 13, described the first conductive polycrystalline silicon 17 is positioned at the center of cellular groove 13; The first conductive polycrystalline silicon 17 extends in the second insulated gate oxide layer 16 from the top of cellular groove 13, and the second insulated gate oxide layer 16 coats the bottom of the first conductive polycrystalline silicon 17.Both sides corresponding to the first conductive polycrystalline silicon 17 in the cellular groove 13 are provided with the second conductive polycrystalline silicon 15, described the second conductive polycrystalline silicon 15 is positioned at the top of cellular groove 13, and the second conductive polycrystalline silicon 15 is corresponding with the first insulated gate oxide layer 11 in the cellular groove 13 in the distance of cellular groove 13 interior extensions.The first conductive polycrystalline silicon 17 and the second conductive polycrystalline silicon 15 N-type epitaxial loayer 2 interior all extend to P trap layer 10 below, and the first conductive polycrystalline silicon 17 distance of extending greater than the second conductive polycrystalline silicon 15 to the distance of downward-extension; The second conductive polycrystalline silicon 15 terminates in the surface of the second insulated gate oxide layer 16 upper ends.15 of the first conductive polycrystalline silicon 17 and the second conductive polycrystalline silicons are isolated by the 3rd insulated gate oxide layer 14, described the 3rd insulated gate oxide layer 14 coats the top of conductive polycrystalline silicons 17, and the 3rd insulated gate oxide layer 14 and the first insulated gate oxide layer 11 are same manufacturing layer; The 3rd insulated gate oxide layer 14 is connected up and down with the second insulated gate oxide layer 16.All with N+ injection region 3, the concentration of described N+ injection region 3 is greater than the concentration of N+ substrate 1 above 13 outer walls of adjacent cellular groove.
On the cross section of described power MOSFET device, the notch of cellular groove 13 is covered by insulating medium layer 7; The both sides of cellular groove 13 are equipped with source electrode contact hole 9, and 9 of described adjacent source electrode contact holes have insulating medium layer 7.Be filled with the second contact hole in the described source electrode contact hole 9 and fill metal 4, described the second contact hole is filled metal 4 P trap layer 10 and N+ injection region 3 ohmic contact corresponding with its below.Be deposited with source metal 6 on the insulating medium layer 7, described source metal 6 is filled metal 4 with the second contact hole and is electrically connected; And source metal 6 and the first conductive polycrystalline silicon 17 connect into equipotential; Particularly, source metal 6 and the first conductive polycrystalline silicon 17 connect into zero potential.Be connected with the equipotential of 17 of the first conductive polycrystalline silicons in order to reach source metal 6, can adopt with the first conductive polycrystalline silicon 17 by lead-in wire draw after and source metal 6 connect into equipotential.Specific practice of the present invention is: the notch at cellular groove 13 arranges the first contact hole 8, described the first contact hole 8 is corresponding with the first conductive polycrystalline silicon 17, extends to the upper end of the first conductive polycrystalline silicon 17 after the first contact hole 8 passes the 3rd insulated gate oxide layer 14 from the surface of insulating medium layer 7.Be filled with the first contact hole filling metal 5, the first conductive polycrystalline silicons 17 in the first contact hole 8 and connect into equipotential by the first contact hole filling metal 5 with source metal 6.Be deposited with drain metal 12 at the second interarea 19, thereby form the drain electrode end of power MOSFET device.
The power MOSFET device of said structure, realize by following processing step:
A, provide the semiconductor substrate with two relative interareas, described semiconductor substrate comprises N+ substrate 1 and is positioned at the N-type epitaxial loayer 2 of described N+ substrate 1 top, the surface of N-type epitaxial loayer 2 forms the first interarea 18 of semiconductor substrate, and the surface of N+ substrate 1 forms the second interarea 19 of semiconductor substrate;
As shown in Figure 2: described N-type epitaxial loayer 2 is in abutting connection with N+ substrate 1; The material of semiconductor substrate comprises silicon, carries out corresponding operating by the first interarea 18 and the second interarea 19 at semiconductor substrate, can form power MOSFET device structure of the present invention;
B, on the first interarea 18 of above-mentioned semiconductor substrate, deposit hard mask layer 20;
C, optionally shelter and etching hard mask layer 20, form the hard mask window 21 of etching groove;
As shown in Figure 3: described hard mask layer 20 can adopt LPTEOS(low-pressure chemical vapor deposition tetraethyl orthosilicate), thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride, forms hard mask by photoetching and anisotropic etching thereafter; Can in the N-type epitaxial loayer 2 of semiconductor substrate, etch groove structure by hard mask window 21;
D, utilize above-mentioned hard mask window 21, by the anisotropic dry etch semiconductor substrate, at the N-type epitaxial loayer 2 interior formation grooves of semiconductor substrate, the degree of depth of described groove is less than the thickness of N-type epitaxial loayer 2 at the first interarea 18;
As shown in Figure 4: described groove comprises the cellular groove 13 that is positioned at element region, and the notch of cellular groove 13 is positioned on the first interarea 18, and cellular groove 13 is from the first interarea 18 to downward-extension;
E, remove the hard mask layer 20 on above-mentioned the first interarea 18, and at the first interarea 18 and the trench wall first insulative oxide material layer 23 of growing, and form the first conductive polycrystalline silicon deposit hole 22 in the center of cellular groove 13;
As shown in Figure 5: described the first insulative oxide material layer 23 is consistent with the thickness of the second insulated gate oxide layer 16 at the thickness of cellular groove 13 bottoms; Need first at the first interarea 18 growths the first insulative oxide material layer 23 for the second insulated gate oxide layer 16 is formed on the bottom at cellular groove 13; The first insulative oxide material layer 23 in the cellular groove 13 is less than the width of cellular groove 13, thereby can form in the center of cellular groove 13 the first conductive polycrystalline silicon deposit hole 22;
F, on above-mentioned the first interarea 18 deposit the first conductive polycrystalline silicon material layer 24, described the first conductive polycrystalline silicon material layer 24 is covered on the first insulative oxide material layer 23, and is filled in the first conductive polycrystalline silicon deposit hole 22;
As shown in Figure 6: can form the first conductive polycrystalline silicon 17 by deposit the first conductive polycrystalline silicon material layer 24;
G, remove the first conductive polycrystalline silicon material layer 24 on the first interarea 18, obtain being positioned at the first conductive polycrystalline silicon 17 of cellular groove 13;
As shown in Figure 7: remove the first conductive polycrystalline silicon material layer 24 and reservation and be positioned at the first conductive polycrystalline silicon material layer 24 in the first conductive polycrystalline silicon deposit hole 22, thereby can access the first conductive polycrystalline silicon 17;
H, wet etching are removed the first insulative oxide material layer 23 on the first interarea 18, remove simultaneously the first insulative oxide material layer 11 of cellular groove 13 upper inside wall, obtain being positioned at the second insulated gate oxide layer 16 of cellular groove 13 bottoms;
As shown in Figure 8: in order to obtain the second required insulated gate oxide layer 16, remove the first insulative oxide material layer 23 on the first interarea 18, and removal need to obtain the first insulative oxide material layer 23 at the first insulated gate oxide layer 11 positions, thereby can access the second insulated gate oxide layer 16, the bottom of described the second insulated gate oxide layer 16 parcels the first conductive polycrystalline silicon 17; The thickness of the second insulated gate oxide layer 16 is 3000-10000;
I, at the first interarea 18 growth second insulative oxide material layer 25 of above-mentioned semiconductor substrate, described the second insulative oxide material layer 25 is covered on the first interarea 18, and be covered in cellular groove 13 upper inside wall, and obtain coating the 3rd insulated gate oxide layer 14 on the first conductive polycrystalline silicon 17 tops; 25 on the second insulative oxide material layer on the 3rd insulated gate oxide layer 14 and cellular groove 13 sidewalls forms the second conductive polycrystalline silicon deposit hole 27;
As shown in Figure 9: can form simultaneously the first insulated gate oxide layer 11 and the 3rd insulated gate oxide layer 14 by the second insulated gate oxidation material layer 25, namely the first insulated gate oxide layer 11 and the 3rd insulated gate oxide layer 14 are same manufacturing layer; Can form in the both sides of the first conductive polycrystalline silicon 17 the second conductive polycrystalline silicon 15 by the second conductive polycrystalline silicon deposit hole 27; Described the second conductive polycrystalline silicon deposit hole 27 extends downwardly into the top end surface of the second insulated gate oxide layer 16 from the first interarea 18; The thickness of the first insulated gate oxide layer 11 and the 3rd insulated gate oxide layer 14 is 200-1200; The thickness of the first insulated gate oxide layer 11 and the 3rd insulated gate oxide layer 14 is consistent with oxidated layer thickness on interior cellular groove 13 sidewalls of existing MOSFET structure;
J, at the first interarea 18 deposits second conductive polycrystalline silicon material layer 26 of above-mentioned semiconductor substrate, described the second conductive polycrystalline silicon material layer 26 is covered on the second insulative oxide material layer 25 and the 3rd insulated gate oxide layer 14, and is filled in the second conductive polycrystalline silicon deposit hole 27;
As shown in figure 10: can be at the second conductive polycrystalline silicon deposit hole 27 interior formation the second conductive polycrystalline silicons 15 by deposit the second conductive polycrystalline silicon material layer 26;
K, etching are removed the second conductive polycrystalline silicon material layer 26 and the second insulative oxide material layer 25 on above-mentioned the first interarea 18, the second conductive polycrystalline silicon 15 that obtains being positioned at the first insulated gate oxide layer 11 of cellular groove 13 side wall upper part and be positioned at the second conductive polycrystalline silicon deposit hole 27;
As shown in figure 11: remove simultaneously the second conductive polycrystalline silicon material layer 26 and the second insulative oxide material layer 25 on the first interarea 18, thus can be at cellular groove 13 interior the first insulated gate oxide layer 11 and the second conductive polycrystalline silicons 15 of obtaining simultaneously;
L, on above-mentioned the first interarea 18, autoregistration Implantation p type impurity ion, and the P trap floor 10 by high temperature knot forming element district, the degree of depth of P trap layer 10 in N-type epitaxial loayer 2 in the described element region less than the second conductive polycrystalline silicon 15 in cellular groove 13 interior distances to downward-extension;
As shown in figure 12: the p type impurity ion that autoregistration is injected can be B ion commonly used, described P trap layer 10 is in the distance of N-type epitaxial loayer 2 distances less than the second conductive polycrystalline silicon 15, namely the lower end of the second conductive polycrystalline silicon 15 is positioned at the below of P trap layer 10, at this moment, the bottom of the first conductive polycrystalline silicon 17 is also below P trap layer 10;
M, on above-mentioned the first interarea 18, carry out the source region photoetching, and inject the N-type foreign ion of high concentration, and the N+ injection region 3 by high temperature knot forming element district;
As shown in figure 13: the N-type foreign ion that injects high concentration can be the As ion, and N+ injection region 3 forms the active area of MOSFET device architecture;
N, on above-mentioned the first interarea 18, deposit insulating medium layer 7, described insulating medium layer 7 covers the first interarea 18 of semiconductor substrates;
O, above-mentioned insulating medium layer 7 is carried out contact hole photoetching and etching, all form source electrode contact hole 9 in the both sides of cellular groove 13, and obtain being positioned at cellular groove 13 notches top first contact hole 8 corresponding with the first conductive polycrystalline silicon 17;
As shown in figure 14: described insulating medium layer 7 is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG);
P, fill metals at above-mentioned the first contact hole 8 and source electrode contact hole 9 interior filling contact holes, the first contact hole that obtains being positioned at the first contact hole 8 is filled metal 5 and is positioned at the second contact hole filling metal 4 of source electrode contact hole 9; The second contact hole is filled N+ injection region 3 and P trap layer 10 ohmic contact of metal 4 and its below, and the first contact hole is filled metal 5 first conductive polycrystalline silicon 17 ohmic contact corresponding with its below;
Q, on above-mentioned insulating medium layer 7 deposit source metal 6, described source metal 6 and the first contact hole are filled metal 5, the second contact hole is filled metal 4 and all connected into equipotential;
As shown in figure 15: particularly, the first conductive polycrystalline silicon 17 is filled metal 5 by the first contact hole and is connected into equipotential with source metal 6; Source metal 6 can adopt the conventional metal materials such as copper; Described the first contact hole fills metal and the second contact hole filling metal is aluminium, copper or tungsten.
R, on the second interarea 19 of above-mentioned semiconductor substrate deposit drain metal 12.
As shown in figure 16: by deposit drain metal 12 on the second interarea 19, form the drain electrode end of power MOSFET device.
The working mechanism of MOSFET device of the present invention is: P trap layer 10, the N+ injection region 3 of the second conductive polycrystalline silicon 15, the first insulated gate oxide layer 11 and the first insulated gate oxide layer 11 sides in the cellular groove 13 have consisted of groove-shaped MOS structure (Metal-oxide-semicondutor), because the thickness of the first insulated gate oxide layer 11 and the gate oxide thickness of common groove type power MOS FET are basically identical, thickness all is about 200-1200, therefore, the threshold voltage of the threshold voltage vt h of groove type power MOS FET of the present invention and common groove type power MOS FET is basically identical.
Also comprise the first conductive polycrystalline silicon 17 and the second insulated gate oxide layer 16 that coats the first conductive polycrystalline silicon 17 in the described groove cellular 13, described the first conduction class polysilicon 17 maintenance zero potential that is connected with source metal 6, described the second insulated gate oxide layer 16 is positioned at the below of P trap layer, and its thickness will obviously be thicker than the thickness of the first insulated gate oxide layer 11.When needing between power MOSFET device drain electrode end and the source terminal when withstand voltage, the drain electrode end that forms in drain metal 12 applies a positive voltage, source terminal connecting to neutral current potential; At this moment, zone, middle and lower part in the corresponding cellular groove 13, specifically, in the N-type epitaxial loayer 2 below the P trap layer 10 between adjacent cellular groove 13, namely can induce a large amount of electric charges near cellular groove 13 side-walls, therefore, under the effect of drain bias voltage, 13 of adjacent cellular grooves can produce depletion layer, i.e. the second insulated gate oxide layer 16 in the cellular groove 13 and the first conductive polycrystalline silicon 17 pressure-resistance structure that can form similar super knot, the depletion layer that support formation is withstand voltage; The depletion layer that the P-N knot that described depletion layer and P trap layer 10 and N-type epitaxial loayer 2 consist of produces bears the voltage drop between the device drain-source jointly, owing to there are two place's depletion layers jointly withstand voltage, therefore the voltage endurance capability of device increases greatly, thereby just increase the concentration of N-type epitaxial loayer 2, the resistivity that reduces N-type epitaxial loayer 2 reduces the conducting resistance of device, namely reduces the conducting resistance of device by the concentration that increases N-type epitaxial loayer 2.As shown in Figure 17, wherein, Figure 17-a is the withstand voltage electric field schematic diagram of the element region of common groove type power MOS FET device, and Figure 17-b is the withstand voltage electric field schematic diagram of the element region of groove type power MOS FET device of the present invention; As seen from the figure, the electric field line of common groove type power MOS FET substantially all is positioned at N-type epitaxial loayer 2, and withstand voltage is the P-N knot that relies on P trap layer 10 and N-type epitaxial loayer 2 to consist of fully; And in the second insulated gate oxide layer 16 that the electric field line of groove type power MOS FET of the present invention is distributed in the N-type epitaxial loayer 2 simultaneously and cellular groove 13 inwalls are thicker, withstand voltage dependence the second insulated gate oxide layer 16 is tied with the P-N that P trap layer 10 and N-type epitaxial loayer 2 consist of, and voltage endurance capability improves greatly.As shown in Figure 18, it is the withstand voltage current-voltage measured curve of drain-source (I-V Cureve) of two 150V groove type power MOS FET device, withstand voltage demand all is greater than 150V, the chip area of two device is identical, solid line is groove type power MOS FET device architecture of the present invention among the figure, dotted line is common groove type power MOS FET device architecture, wherein, adopt N-type epitaxial loayer 2 resistivity of structure devices of the present invention only have the ordinary construction device N-type epilayer resistance rate 1/2nd, as can be seen from the figure, under the prerequisite that has reduced device N-type epilayer resistance rate, the withstand voltage 190V that still reached of power MOSFET device of the present invention, the 175V that is higher than common power MOSFET device, simultaneously, because the reduction of N-type epilayer resistance rate, the feature conducting resistance of power MOSFET device of the present invention has reduced about 40% than the feature conducting resistance of common power MOSFET device.
In the structure cell of groove type power MOS FET device of the present invention, because the second conductive polycrystalline silicon 15 belows as the MOS device grids are the second insulated gate oxide layer 16, therefore, the second conductive polycrystalline silicon 15 is just very limited with the area that N-type epitaxial loayer 2 overlaps mutually, so, device open or turn off process in charge or discharge charge Q gd between the grid leak very little, so just greatly improved the switching speed of device, reduced the switching loss of device.
Claims (10)
1. the power MOSFET device of a groove structure on the top plan view of described MOSFET device, comprises the element region and the terminal protection district that are positioned at semiconductor substrate, and described terminal protection district is positioned at the outer ring of element region, and the terminal protection district is around the embracing element district; Comprise the cellular that some rules are arranged and are parallel to each other and are arranged in parallel in the element region; On the cross section of described MOSFET device, semiconductor substrate has the first corresponding interarea and the second interarea, comprise the first conductive type epitaxial layer of the first conductivity type substrate and described the first conductivity type substrate of adjacency between described the first interarea and the second interarea, the top in the first conductive type epitaxial layer is provided with the second conductive type layer; Its innovation is:
On the cross section of described MOSFET device, the cellular of element region adopts groove structure, described cellular groove is positioned at the second conductive type layer, and by the first interarea of semiconductor substrate to downward-extension, the degree of depth stretches in the first conductive type epitaxial layer of described the second conductive type layer below; The superficial growth of described cellular trench wall has insulating oxide, described insulating oxide comprises the first insulated gate oxide layer and the second insulated gate oxide layer, described the first insulated gate oxide layer growth is in the top of cellular trenched side-wall, the second insulated gate oxide layer growth is in the bottom of cellular groove and cover bottom and the bottom of cellular trenched side-wall, the thickness of the second insulated gate oxide layer is greater than the thickness of the first insulated gate oxide layer, and the first insulated gate oxide layer is connected up and down with the second insulated gate oxide layer;
On the cross section of described MOSFET device, be deposited with conductive polycrystalline silicon in the cellular groove, described conductive polycrystalline silicon comprises the first conductive polycrystalline silicon and the second conductive polycrystalline silicon, described the first conductive polycrystalline silicon and the second conductive polycrystalline silicon extend downward the below of the second conductive type layer by the top of cellular groove, and the first conductive polycrystalline silicon distance of extending in cellular groove distance of extending greater than the second conductive polycrystalline silicon; The first conductive polycrystalline silicon is positioned at the center of cellular groove, the second conductive polycrystalline silicon is positioned at the both sides of the first conductive polycrystalline silicon, by the isolation of the 3rd insulated gate oxide layer, described the 3rd insulated gate oxide layer is connected up and down with the second insulated gate oxide layer between the first conductive polycrystalline silicon and the second conductive polycrystalline silicon; Isolate by the first insulated gate oxide layer between the second conductive polycrystalline silicon and cellular trench wall;
On the cross section of described MOSFET device, outer wall top corresponding between adjacent cellular groove is all with the first conduction type injection region; The notch of cellular groove is covered by insulating medium layer, the both sides of cellular groove are provided with the source electrode contact hole, be filled with the second contact hole in the described source electrode contact hole and fill metal, described the second contact hole is filled metal and the first conduction type injection region and the second conductive type layer ohmic contact; Cellular groove top is provided with source metal, and described source metal is covered in insulating medium layer and the second contact hole is filled on the metal, and source metal and the second contact hole are filled metal and be electrically connected; The first conductive polycrystalline silicon is connected with the source metal equipotential.
2. the power MOSFET device of described groove structure according to claim 1, it is characterized in that: on the cross section of described MOSFET device, the top of cellular groove is provided with the first contact hole, and described the first contact hole is extended downward on the first conductive polycrystalline silicon by the insulating medium layer surface; Be provided with the first contact hole in the first contact hole and fill metal; The first conductive polycrystalline silicon is filled metal by the first contact hole and is connected with the source metal equipotential.
3. the power MOSFET device of described groove structure according to claim 1, it is characterized in that: the second interarea of described semiconductor substrate is provided with drain metal.
4. the power MOSFET device of described groove structure according to claim 1 and 2, it is characterized in that: described the first conductive polycrystalline silicon and source metal connect into zero potential.
5. the power MOSFET device manufacture method of a groove structure is characterized in that, the manufacture method of described power MOSFET comprises the steps:
(a), provide the semiconductor substrate with two relative interareas, described semiconductor substrate comprises the first conductivity type substrate and is positioned at the first conductive type epitaxial layer of described the first conductivity type substrate top, the surface of the first conductive type epitaxial layer forms the first interarea of semiconductor substrate, and the surface of the first conductivity type substrate forms the second interarea of semiconductor substrate;
(b), on the first interarea of above-mentioned semiconductor substrate, the deposit hard mask layer;
(c), optionally shelter and the etching hard mask layer, form the hard mask window of etching groove;
(d), utilize above-mentioned hard mask window, by the anisotropic dry etch semiconductor substrate, in the first conductive type epitaxial layer of semiconductor substrate, form groove at the first interarea, the degree of depth of described groove is less than the thickness of the first conductive type epitaxial layer;
(e), remove the hard mask layer on above-mentioned the first interarea, and at the first interarea and the trench wall first insulative oxide material layer of growing, and form the first conductive polycrystalline silicon deposit hole in the center of cellular groove;
(f), on above-mentioned the first interarea deposit the first conductive polycrystalline silicon material layer, described the first conductive polycrystalline silicon layer of material covers and is filled in the first conductive polycrystalline silicon deposit hole on the first insulative oxide material layer;
(g), remove the first conductive polycrystalline silicon material layer on the first interarea, obtain being positioned at the first conductive polycrystalline silicon of cellular groove;
(h), wet etching removes the first insulative oxide material layer on the first interarea, removes simultaneously the first insulative oxide material layer on cellular trench wall top, obtains being positioned at the second insulated gate oxide layer of cellular groove bottom;
(i), at the first interarea of above-mentioned semiconductor substrate growth the second insulative oxide material layer, described the second insulative oxide material layer is covered on the first interarea, and be covered in cellular groove upper inside wall, and obtain coating the 3rd insulated gate oxide layer on the first conductive polycrystalline silicon top; The second insulative oxide material interlayer on the 3rd insulated gate oxide layer and the cellular trenched side-wall forms the second conductive polycrystalline silicon deposit hole;
(j), at the first interarea deposit second conductive polycrystalline silicon material layer of above-mentioned semiconductor substrate, described the second conductive polycrystalline silicon layer of material covers and is filled in the second conductive polycrystalline silicon deposit hole on the second insulative oxide material layer and the 3rd insulated gate oxide layer;
(k), etching is removed the second conductive polycrystalline silicon material layer and the second insulative oxide material layer on above-mentioned the first interarea, the second conductive polycrystalline silicon that obtains being positioned at the first insulated gate oxide layer on cellular trenched side-wall top and be positioned at the second conductive polycrystalline silicon deposit hole;
(l), on above-mentioned the first interarea, autoregistration Implantation the second conductive type impurity ion, and the second conductive type layer by high temperature knot forming element district, the degree of depth of the second conductive type layer in the first conductive type epitaxial layer in the described element region is less than the second conductive polycrystalline silicon distance to downward-extension in the cellular groove;
(m), on above-mentioned the first interarea, carry out the source region photoetching, and inject the first conductive type impurity ion of high concentration, by the first conduction type injection region in high temperature knot forming element district;
(n), on above-mentioned the first interarea, the deposit insulating medium layer, described insulating medium layer covers the first interarea of semiconductor substrate;
(o), above-mentioned insulating medium layer is carried out contact hole photoetching and etching, all form the source electrode contact hole in the both sides of cellular groove, and obtain being positioned at cellular groove notch top the first contact hole corresponding with the first conductive polycrystalline silicon;
(p), filling contact hole is filled metal in above-mentioned the first contact hole and source electrode contact hole, obtains the second contact hole filling metal that is positioned at the first contact hole filling metal of the first contact hole and is positioned at the source electrode contact hole; The second contact hole is filled the first conduction type injection region and the second conductive type layer ohmic contact of metal and its below, and the first contact hole is filled the metal first conductive polycrystalline silicon ohmic contact corresponding with its below;
(q), on above-mentioned insulating medium layer the deposit source metal, described source metal and the first contact hole are filled metal, the second contact hole is filled metal and all connected into equipotential;
(r), deposit drain metal on the second interarea of above-mentioned semiconductor substrate.
6. the power MOSFET device manufacture method of described groove structure according to claim 5, it is characterized in that: described hard mask layer is that LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
7. the power MOSFET device manufacture method of described groove structure according to claim 5, it is characterized in that: described insulating medium layer is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
8. the power MOSFET device manufacture method of described groove structure according to claim 5, it is characterized in that: it is aluminium, copper or tungsten with the second contact hole filling metal that described the first contact hole is filled metal.
9. the power MOSFET device manufacture method of described groove structure according to claim 5, it is characterized in that: the thickness of the first insulated gate oxide layer in the described cellular groove is 200-1200.
10. the power MOSFET device manufacture method of described groove structure according to claim 5, it is characterized in that: the thickness of the second insulated gate oxide layer in the described cellular groove is 3000-10000.
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| CN113555414A (en) * | 2021-07-20 | 2021-10-26 | 江苏中科汉韵半导体有限公司 | Trench type silicon carbide field effect transistor and preparation method thereof |
| CN113991419B (en) * | 2021-10-22 | 2023-12-15 | 中国科学院半导体研究所 | Buried heterojunction device and preparation method thereof |
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| CN101083282A (en) * | 2006-05-30 | 2007-12-05 | 半导体元件工业有限责任公司 | Semiconductor device having sub-surface trench charge compensation regions and method |
| CN101510557A (en) * | 2008-01-11 | 2009-08-19 | 艾斯莫斯技术有限公司 | Superjunction device having a dielectric termination and methods for manufacturing the device |
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