CN100565879C - A kind of deep groove large power MOS device and manufacture method thereof - Google Patents
A kind of deep groove large power MOS device and manufacture method thereof Download PDFInfo
- Publication number
- CN100565879C CN100565879C CN 200810019085 CN200810019085A CN100565879C CN 100565879 C CN100565879 C CN 100565879C CN 200810019085 CN200810019085 CN 200810019085 CN 200810019085 A CN200810019085 A CN 200810019085A CN 100565879 C CN100565879 C CN 100565879C
- Authority
- CN
- China
- Prior art keywords
- groove
- polycrystalline silicon
- unit cell
- ring
- conductive polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention relates to a kind of deep groove large power MOS device and manufacture method thereof.This MOS device is on top plan view; the center is provided with the array that unit cell in parallel is formed; the periphery of unit cell array is provided with terminal protection structure; terminal protection structure is by at least one guard ring that is positioned at inner ring and be positioned at one of the outer ring and form by ring; all adopt groove-shaped conductive polycrystalline silicon owing to guard ring with by ring; in device manufacturing processes; unit cell gate electrode lead-in wire adopts directly perforate lead-in wire on the groove polysilicon; therefore compare with the deep groove large power MOS device manufacture method of existing common plane formula field plate structure; under the prerequisite that does not influence device performance; reduce two reticle and corresponding technology, reduced manufacturing cost greatly.Simultaneously, adopt a phosphorus to inject, and then adopt a boron injection and supporting annealing process to regulate conductive polycrystalline silicon resistance, reduce the leakage current between grid and source electrode greatly, and guaranteed under the prerequisite that does not increase N trap concentration, to obtain rational threshold voltage.
Description
Technical field
The present invention relates to a kind of large-power MOS part and manufacture method thereof, particularly a kind of deep groove large power MOS device and manufacture method thereof.This MOS device adopts groove conductive polycrystalline silicon guard ring and groove conductive polycrystalline silicon by the structural design of encircling; can under the prerequisite that does not influence device performance (as feature conducting resistance (Specific Rdson), withstand voltage, device capacitor etc.), reduce reticle quantity, thereby reduce the manufacturing cost of device.
Background technology
The basic demand of modern deep groove large power device is can high pressure resistant and big current work.Wherein, deep trench MOSFET normally by a large amount of groove MOS unit cell of parallel connection to realize big current work.But, for high pressure deep trench MOSFET, the surface potential that is positioned between each unit cell in parallel in the middle of the device is roughly the same, and is positioned at the unit cell on border (being terminal) with the current potential of substrate surface differs greatly, and often causes the too concentrated edge breakdown that has caused device of surface field.Therefore in order to guarantee high-power groove MOSFET operate as normal under high pressure, need take measures at device unit cell boundary usually is the terminal protection technology, reduces surface field intensity, improves the puncture voltage of high-power groove MOSFET.Terminal protection structure generally is made up of guard ring that is positioned at inner ring and the ring that ends that is positioned at the outer ring, and existing terminal protection structure adopts plane guard ring structure usually, sees shown in Figure 1.Guard ring and cover on the oxidation separator 15 on the scene by the plane conductive polycrystalline silicon 16 of ring as can be seen from Figure 1, metal connecting line 6 is drawn from the plane conductive polycrystalline silicon 16 on the field oxidation separator 15.This structure devices needs the source region photoetching when fabricating yard oxidation separator 15, and needs to increase field limiting ring injection and high temperature knot.Needing the polysilicon photoetching when making conductive polycrystalline silicon 7, is planarized structure because of it simultaneously, has also taken than large tracts of land, and chip cost is higher.Make the deep slot type large-power MOS part according to this requirement, need at present to use seven reticle, and finish by following technological process:
The first step, field oxide is grown up;
Second step, active area photoetching/etching (reticle 1);
The 3rd step, hard mask growth (reticle 2);
The 4th step, deep plough groove etched;
The 5th step, gate oxidation/polysilicon deposit/resistance of polycrystalline silicon adjustment;
The 6th step, polycrystalline photoetching/etching (reticle 3);
In the 7th step, N trap layer injects;
The 8th step, source electrode photoetching (reticle 4);
The 9th step, the inter-level dielectric deposit;
The tenth step, hole photoetching/etching (reticle 5);
The 11 step, aluminum metal deposit/photoetching/etching (reticle 6);
The 12 step, passivation layer deposit/photoetching/etching (reticle 7).
On the other hand, along with the deep groove large power MOS technology reaches its maturity, market competition is growing more intense, and therefore how to reduce manufacturing cost and become those skilled in the art's question of common concern under the prerequisite that guarantees device performance.Improve integrated level (promptly improving unit cell number in the unit are) and reduce the manufacturing cost that photoetching time number average can reduce device, wherein, improve integrated level and mainly realize, mainly be limited by the contraposition ability of mask aligner and the control of knot pattern yet dwindle unit cell spacing (Pitch) by dwindling unit cell spacing (Pitch).The production in enormous quantities ability of unit cell spacing (Pitch) can reach 1.2um～1.7um both at home and abroad at present, Dui Ying groove dimensions is 0.4um with it, the step photo-etching machine aligning accuracy require for+/-0.12um, among 0.9～1.1um unit cell spacing (Pitch) technology is being developed, extend downwards again, to be subjected to the restriction of mask aligner technological limits, exist device capacitor to increase simultaneously, cause difficult problems such as devices switch speed reduction.Reduce the reticle number and can under the prerequisite that does not influence device performance, reduce manufacturing cost.This is the present invention's problem of research emphatically.
Summary of the invention
The invention provides a kind of deep groove large power MOS device and manufacture method thereof; its objective is will be under the prerequisite that guarantees not influence device performance (as feature conducting resistance (Specific Rdson), withstand voltage and device capacitor etc.); improvement design by terminal protection structure and unit cell gate electrode pin configuration reduces by two reticle, thereby reduces the manufacturing cost of device.Adopt a phosphorus to inject simultaneously, adopt a boron injection and supporting annealing process to regulate conductive polycrystalline silicon resistance and then, guarantee rational grid source-drain current and threshold voltage.
For achieving the above object, the technical scheme that MOS device of the present invention adopts is: a kind of deep groove large power P type MOS device, and on top plan view, array is formed by the unit cell of parallel connection in the center, and the periphery of unit cell array is provided with terminal protection structure; Unit cell is by the groove conductive polycrystalline silicon and unify in the described array, and terminal protection structure is by at least one guard ring that is positioned at inner ring and be positioned at of outer ring and form by ring; Its innovation is: N trap layer is present in the whole terminal protection zone;
Guard ring adopts groove structure on the cross section, groove is positioned at light dope N trap layer, its degree of depth stretches into the doped with P type epitaxial loayer of N trap layer below, the trench wall superficial growth has the insulated gate oxide layer, be deposited with conductive polycrystalline silicon in the groove, the notch at groove top is covered by dielectric, constitutes the float guard ring of field plate structure of groove-shaped conductive polycrystalline silicon with this;
On the cross section, adopt groove structure by ring, this groove width is greater than the groove width of unit cell, groove is positioned at light dope N trap layer, its degree of depth stretches into the doped with P type epitaxial loayer of N trap layer below, the trench wall superficial growth has the insulated gate oxide layer, be deposited with conductive polycrystalline silicon in the groove, the groove top is provided with metal connecting line, the groove outside is the N trap layer of N trap layer or band P+ injection region, top, this metal connecting line connects into equipotential with the N trap layer in the conductive polycrystalline silicon in the groove and the groove outside, perhaps the conductive polycrystalline silicon in the groove is simultaneously connected into equipotential with the P+ injection region and the N trap layer in the groove outside, the notch at groove top is covered by dielectric, constitutes the ring that ends of groove-shaped conductive polycrystalline silicon with this.
Related content in the technique scheme is explained as follows:
1, in the such scheme; for the mating protection ring with by the design that encircles; reach the purpose of saving a polysilicon photoetching; the direct pin configuration from the groove conductive polycrystalline silicon of unit cell gate electrode lead-in wire; be specially: extend in the zone of the groove conductive polycrystalline silicon of unit cell array between guard ring and unit cell array; elongated end is the circular wire lead termination of a diameter greater than groove width; perhaps the drift angle line is greater than the polygon wire lead termination of groove width; the gate electrode fairlead is opened on this wire lead termination position, and metal connecting line is directly linked to each other with the groove conductive polycrystalline silicon.
2, in the such scheme; described groove-shaped float the field plate structure guard ring and by the ring mechanism of action be: N trap layer is present in the whole terminal protection zone; the groove guard ring is isolated it; (drain electrode adds negative voltage when this device normal bias; source ground) time; the maximum field point, promptly the Mi Qu of power line is present in the infall of main knot (the outermost unit cell N PN junction that trap/the P-epitaxial loayer is formed) unit cell groove corresponding with it.Except source electrode arrives the longitudinal electric field of drain electrode, also has from the unit cell direction to device outermost electric field.When the value of main knot reversed bias voltage greatly when making depletion region expand to the groove guard ring; groove guard ring electronics flow into main knot; it is positively charged that this guard ring is become by electric neutrality; this positive charge is distributed in the thin district, a surface of guard ring groove one side (near unit cell); the electric field that positive charge produces on the surface is opposite with original direction of an electric field (from the unit cell direction to the device outermost) in main zone of tying guard ring; therefore make this zone, especially main knot weakens with the electric field of the infall of groove.Groove guard ring exterior lateral area is then just in time opposite.Because power line all can be pooled to by ring, adopts the bigger groove of width by ring, plays the effect of dilution power line, reaches the effect that improves puncture voltage; Simultaneously in ring manufacturing process, once higher concentration phosphorus injects after contact etch finishes, make metal connecting line form good the contact with the conduction polycrystalline with the N trap, groove conductive polycrystalline silicon and N well region equipotential, thereby can not form inversion layer at its side (vertical plane), and it can collect SiO
2The cation of surface contamination, and these cations also are the factors that causes surperficial transoid, so by encircling the effect that improves surface stability in addition.
For achieving the above object; the technical scheme that MOS device making method of the present invention adopts is: a kind of manufacture method of deep groove large power P type MOS device; improvement design based on the above terminal protection structure and unit cell gate electrode pin configuration may further comprise the steps:
The first step, hard mask growth (reticle 1 ');
Second step, deep plough groove etched;
The 3rd step, gate oxidation/polysilicon deposit/resistance of polycrystalline silicon adjustment;
The 4th step, etching polysilicon;
In the 5th step, N trap layer injects;
The 6th step, source electrode photoetching (reticle 2 ');
The 7th step, the inter-level dielectric deposit;
The 8th step, hole photoetching/etching (reticle 3 ');
The 9th step, aluminum metal deposit/photoetching/etching (reticle 4 ');
The tenth step, passivation layer deposit/photoetching/etching (reticle 5 ').
Wherein the adjusting of polysilicon resistance is injected by at first adopting a phosphorus, adopts a boron injection and supporting annealing process to realize and then.Boron injects except regulating resistance of polycrystalline silicon, and an other important function is adjust work function between polysilicon and substrate poor, makes under the prerequisite that does not increase N trap concentration, obtains reasonably threshold voltage; Because boron is stronger to the penetrability of silicon dioxide, if only adopt boron to inject, follow-up high-temperature technology makes the boron ion infiltrate gate oxide in addition, causes the electric leakage of grid source to increase.And the penetrability of phosphorus is relatively poor, owing to fractional condensation is done to accumulate near the silicon of silicon/silicon dioxide interface, thereby plays the penetrability effect that suppresses boron, has guaranteed lower grid source-drain current.Therefore, use this injection technology, can guarantee rational grid source-drain current, and guarantee under the prerequisite that does not increase N trap concentration, to obtain rational threshold voltage.(increase N trap concentration and can increase parasitic capacitance, thereby reduce switching speed.)
Because the technique scheme utilization, the present invention compared with prior art has following advantage and effect:
1, MOS device guard ring of the present invention and all adopt groove-shaped conductive polycrystalline silicon by the ring field plate need not to form an oxygen separator, saves an active area reticle.The plane polysilicon field plate structure of comparing has also been saved area, has improved integrated level, has reduced manufacturing cost.
2, in order to reach the purpose of saving a polysilicon reticle, except adopting groove polysilicon field plate, the present invention all adopts the directly metal interconnection structure of perforate lead-in wire of groove polysilicon top also to improving by ring and unit cell gate electrode lead-in wire.And prior art is seen shown in Figure 2ly, because groove-shaped conductive polycrystalline silicon 7 tops are provided with the plane conductive polycrystalline silicon 16 of extension in the unit cell array, need increase the polysilicon reticle when making plane conductive polycrystalline silicon 16.Therefore, MOS device architecture of the present invention can be saved two reticle altogether, reduces production costs.
3, existing that manufacture method of the present invention and the contrast of existing manufacture method is as follows:
From the form of above contrast, can clearly find out following effect:
The first, manufacture method of the present invention has been saved active area reticle and corresponding technology;
The second, manufacture method of the present invention has been saved polycrystalline reticle and corresponding technology;
The 3rd, manufacture method of the present invention has saved growth oxide layer technology and field limiting ring injects and high temperature knot technology.
Generally speaking, the manufacturing cost of deep groove large power device can be simplified to the photoetching number of plies and calculate, increase by a layer photoetching and increase by 15% cost approximately, therefore the present invention has reduced Twi-lithography and approximately can reduce cost about 30%, and this effect for producing the deep slot type large-power MOS part in batches is significant.
4, adopt phosphorus injection and boron to inject and regulate polysilicon resistance, can obviously reduce the leakage current between grid and source electrode, and guarantee rational threshold voltage.
Description of drawings
Accompanying drawing 1 is the deep groove large power MOS device schematic diagram of existing common plane formula field plate structure;
Accompanying drawing 2 is the existing common pin configuration schematic diagram of deep groove large power MOS device;
Accompanying drawing 3 is an embodiment of the invention deep groove large power MOS device schematic top plan view;
Accompanying drawing 4 is the A-A profile of Fig. 3;
Accompanying drawing 5 is the B-B profile of Fig. 3.
In the above accompanying drawing: 1, unit cell array; 2, guard ring; 3, by ring; 4, insulating medium layer; 5, passivation layer; 6, metal connecting line; 7, groove-shaped conductive polycrystalline silicon; 8, N-trap; 9, P-type epitaxial loayer; 10, P+ substrate; 11, insulated gate oxide layer; 12, existing guard ring; 13, existing by ring; 14, unit cell; 15, an oxidation separator; 16, plane conductive polycrystalline silicon; 17, gate electrode wire lead termination.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described:
Embodiment: a kind of deep groove large power P type MOS device
Fig. 3 overlooks the state plane schematic diagram for a kind of deep groove large power P type MOS device.As can be seen from the figure, MOS device center is provided with unit cell array 1, and the periphery of this unit cell array 1 is provided with terminal protection structure.Unit cell array 1 by groove-shaped conductive polycrystalline silicon 7 with each unit cell and unify.Terminal protection structure is by a guard ring 2 that is positioned at inner ring and be positioned at of outer ring and form by ring 3.The present embodiment guard ring is one, but also can adopt two or more guard ring structures, and this is determined by actual needs.
Fig. 4 is the A-A profile of Fig. 3, and this figure is an embodiment of the invention deep groove large power MOS device schematic cross-section.As can be seen from the figure; guard ring 2 adopts groove structure on the cross section; groove is positioned at light dope N trap layer 8; its degree of depth stretches into the doped with P type epitaxial loayer 9 of N trap layer 8 below; the trench wall superficial growth has insulated gate oxide layer 11; be deposited with conductive polycrystalline silicon in the groove and form groove-shaped conductive polycrystalline silicon 7, the notch at groove top is covered by insulating medium layer 4, constitutes the float guard ring of field plate structure of groove-shaped conductive polycrystalline silicon with this.
On the cross section, adopt groove structure by ring 3, this groove is bigger than unit cell groove width, groove is positioned at light dope N trap layer 8, its degree of depth stretches into the doped with P type epitaxial loayer 9 of N trap layer 8 below, the trench wall superficial growth has insulated gate oxide layer 11, be deposited with conductive polycrystalline silicon in the groove and form groove-shaped conductive polycrystalline silicon 7, the groove top is provided with metal connecting line 6, this metal connecting line 6 connects into equipotential with the N trap layer 8 in the conductive polycrystalline silicon in the groove 7 and the groove outside, the notch at groove top is covered by insulating medium layer 4, constitutes the ring that ends of groove-shaped conductive polycrystalline silicon with this.Here need explanation: if when the N trap layer top in ring 3 the groove outside adds the P+ injection region, this metal connecting line connects into equipotential with the P+ injection region and the N trap layer in the groove outside simultaneously with the conductive polycrystalline silicon in the groove.Among Fig. 4, the N trap layer by the ring 3 grooves outside does not add the P+ injection region.
Fig. 5 is the B-B profile of Fig. 3, and this figure is a directly perforate lead-in wire schematic diagram on the groove polysilicon of gate electrode wire lead termination 17 of the embodiment of the invention.As can be seen from Figure 3, extend in the zone of the groove conductive polycrystalline silicon of unit cell array between guard ring and unit cell array, and elongated end is a length of side greater than the rectangle of groove width as gate electrode wire lead termination 17.As can be seen from Figure 5, each gate electrode wire lead termination 17 top drilling, and be deposited with interconnecting metal, groove conductive polycrystalline silicon 7 is directly linked to each other with metal connecting line 6.
The present invention makes the method for above-mentioned deep groove large power P type MOS device, may further comprise the steps:
The first step, the hard mask growth of silicon.Wherein hard mask can adopt LPTEOS or thermal oxidation silicon dioxide to add chemical vapour deposition (CVD) silicon dioxide or thermal oxidation silicon dioxide adds silicon nitride, forms hard mask by photoetching and anisotropic etching thereafter.
Second step, deep plough groove etched.Groove adopts anisotropic etching to form vertical sidewall (usually about 88 degree).
The 3rd step, gate oxidation/polysilicon deposit/resistance of polycrystalline silicon adjustment.Existing common process is adopted in gate oxidation/polysilicon deposit.The resistance of polycrystalline silicon adjustment at first adopts a phosphorus to inject, and adopts a boron to inject and then.
The 4th step, etching polysilicon.Etching polysilicon is the comprehensive anisotropic etching of disk.
In the 5th step, N trap layer injects.Wherein N trap layer covers the zone of whole terminal protection structure.
The 6th step, the source electrode photoetching.Source electrode utilizes well-known photoetching to add the ion injection and forms, and the ion that injects is a boron usually.
The 7th step, the inter-level dielectric deposit.The inter-level dielectric deposit can be chosen boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG) or silex glass (USG) etc.
The 8th step, hole photoetching/etching.
The 9th step, aluminum metal deposit/photoetching/etching.Prior art is adopted in the formation of hole and metal interconnecting wires, metal filledly can adopt tungsten plug technology or direct metal fill process.
The tenth step, passivation layer deposit/photoetching/etching.
Deep groove large power MOS device of the present invention adopts the groove-shaped guard ring and groove-shaped by ring of floating; under the prerequisite that guarantees properties of product, reduced Twi-lithography, saved chip area; reduce manufacturing cost greatly, applicable to the low-cost deep groove large power MOS device of making in enormous quantities.
The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (2)
1, a kind of deep groove large power P type MOS device, on top plan view, array is formed by the unit cell of parallel connection in the center, and the periphery of unit cell array is provided with terminal protection structure; Unit cell is by the groove conductive polycrystalline silicon and unify in the described array, and terminal protection structure is by at least one guard ring that is positioned at inner ring and be positioned at of outer ring and form by ring, it is characterized in that:
N trap layer is present in the whole terminal protection zone;
Guard ring adopts groove structure on the cross section, groove is positioned at light dope N trap layer, its degree of depth stretches into the doped with P type epitaxial loayer of N trap layer below, the trench wall superficial growth has the insulated gate oxide layer, be deposited with conductive polycrystalline silicon in the groove, the notch at groove top is covered by dielectric, constitutes the float guard ring of field plate structure of groove-shaped conductive polycrystalline silicon with this;
On the cross section, adopt groove structure by ring, this groove width is greater than the groove width of unit cell, groove is positioned at light dope N trap layer, its degree of depth stretches into the doped with P type epitaxial loayer of N trap layer below, the trench wall superficial growth has the insulated gate oxide layer, be deposited with conductive polycrystalline silicon in the groove, the groove top is provided with metal connecting line, the groove outside is the N trap layer of N trap layer or top band P+ injection zone, this metal connecting line connects into equipotential with the N trap layer in the conductive polycrystalline silicon in the groove and the groove outside, perhaps the conductive polycrystalline silicon in the groove is simultaneously connected into equipotential with the P+ injection region and the N trap layer in the groove outside, the notch at groove top is covered by dielectric, constitutes the ring that ends of groove-shaped conductive polycrystalline silicon with this.
2, deep groove large power P type MOS device according to claim 1; it is characterized in that: extend in the zone of the groove conductive polycrystalline silicon of described unit cell array between guard ring and unit cell array; elongated end is the circular wire lead termination of a diameter greater than the groove width of unit cell array; perhaps the length of side is greater than the polygon wire lead termination of the groove width of unit cell array; the gate electrode fairlead is opened on this wire lead termination position, and metal connecting line is directly linked to each other with the groove conductive polycrystalline silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810019085 CN100565879C (en) | 2008-01-08 | 2008-01-08 | A kind of deep groove large power MOS device and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810019085 CN100565879C (en) | 2008-01-08 | 2008-01-08 | A kind of deep groove large power MOS device and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101217144A CN101217144A (en) | 2008-07-09 |
| CN100565879C true CN100565879C (en) | 2009-12-02 |
Family
ID=39623535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810019085 Expired - Fee Related CN100565879C (en) | 2008-01-08 | 2008-01-08 | A kind of deep groove large power MOS device and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100565879C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752375B (en) * | 2009-12-29 | 2011-06-22 | 无锡新洁能功率半导体有限公司 | Groove type power MOS device with improved terminal protective structure |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719516B (en) * | 2009-11-20 | 2011-04-06 | 苏州硅能半导体科技股份有限公司 | Low gate charge deep trench power MOS device and manufacturing method thereof |
| CN102201409A (en) * | 2010-03-24 | 2011-09-28 | 万国半导体(开曼)股份有限公司 | Power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with tungsten spacing layer and production method thereof |
| CN101807574B (en) * | 2010-03-30 | 2012-02-29 | 无锡新洁能功率半导体有限公司 | Groove type power MOS device and manufacturing method thereof |
| CN102214689B (en) | 2010-04-06 | 2012-11-07 | 上海华虹Nec电子有限公司 | Terminal protection structure of super junction device and manufacturing method of terminal protection structure |
| CN101834209B (en) * | 2010-04-23 | 2012-01-11 | 无锡新洁能功率半导体有限公司 | Power MOS (Metal Oxide Semiconductor) device with groove and manufacturing method thereof |
| CN101866923B (en) * | 2010-05-18 | 2011-12-07 | 苏州硅能半导体科技股份有限公司 | Three-layer light cover groove MOS device and manufacture method |
| CN102593163B (en) * | 2010-09-09 | 2014-11-05 | 杭州士兰微电子股份有限公司 | High voltage vertical double-diffused metal oxide semiconductor (VDMOS) device structure and production method of high voltage VDMOS devices |
| CN101950760B (en) * | 2010-09-09 | 2013-09-18 | 杭州士兰微电子股份有限公司 | High-voltage VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) device structure and manufacturing method thereof |
| CN102130150A (en) * | 2010-12-13 | 2011-07-20 | 成都方舟微电子有限公司 | Junction terminal structure of semiconductor device |
| CN103426906B (en) * | 2012-05-21 | 2016-05-04 | 科轩微电子股份有限公司 | Groove type power metal oxygen half field effect transistor and its manufacture method |
| US9773863B2 (en) * | 2014-05-14 | 2017-09-26 | Infineon Technologies Austria Ag | VDMOS having a non-depletable extension zone formed between an active area and side surface of semiconductor body |
| JP6729523B2 (en) * | 2017-08-31 | 2020-07-22 | 株式会社デンソー | Silicon carbide semiconductor device and manufacturing method thereof |
| CN110854072B (en) * | 2020-01-07 | 2022-11-04 | 四川立泰电子有限公司 | Manufacturing process of low electromagnetic interference power device terminal structure |
-
2008
- 2008-01-08 CN CN 200810019085 patent/CN100565879C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752375B (en) * | 2009-12-29 | 2011-06-22 | 无锡新洁能功率半导体有限公司 | Groove type power MOS device with improved terminal protective structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101217144A (en) | 2008-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100555666C (en) | A kind of deep groove large power MOS device and manufacture method thereof | |
| CN100565879C (en) | A kind of deep groove large power MOS device and manufacture method thereof | |
| CN107204372B (en) | Trench type semiconductor device with optimized terminal structure and manufacturing method | |
| CN101752423B (en) | Groove type high-power MOS device and manufacturing method thereof | |
| CN103887173B (en) | Utilize the HF switch MOSFET of the low output capacitance exhausting P-shielding | |
| CN100555635C (en) | A kind of power groove MOS field effect tube and manufacture method thereof | |
| CN102280487B (en) | Power MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) device of novel groove structure and manufacture method thereof | |
| CN202534649U (en) | Stop effect-improving groove type power MOS device | |
| CN103151382B (en) | For optimizing the preparation method of the asymmetric polysilicon gate of termination design in groove power MOSFET | |
| CN102263133A (en) | Low-gate charge low-on resistance deep trench power metal oxide semiconductor field effect transistor (MOSFET) device and manufacturing method | |
| CN201146191Y (en) | High-power N type MOS device for deep groove | |
| CN102931090B (en) | Manufacturing method for super junction metal oxide semiconductor field effect transistor (MOSFET) | |
| CN101807574A (en) | Groove type power MOS device and manufacturing method thereof | |
| CN104576743A (en) | Deep-groove power MOS (metal oxide semiconductor) device with ultrahigh cellular density and manufacturing method of deep-groove power MOS device | |
| CN102544107A (en) | Power metal oxide semiconductor (MOS) device with improved terminal structure and manufacturing method for power MOS device | |
| CN101814528B (en) | Semiconductor element with improved terminal and manufacturing method thereof | |
| CN102420252A (en) | Ultrahigh cell density deep trench power metal oxide semiconductor (MOS) device and manufacturing method thereof | |
| CN104716177A (en) | Radio frequency LOMOS device for overcoming electricity leakage and manufacturing method of radio frequency LOMOS device for overcoming electricity leakage | |
| CN111048408A (en) | Short-channel silicon carbide MOSFET device integrated with Schottky diode and manufacturing method thereof | |
| CN201163629Y (en) | Power MOS field effect pipe with polysilicon field plate | |
| CN202473933U (en) | Power metal oxide semiconductor (MOS) device with improved terminal structure | |
| CN201877431U (en) | Semiconductor device having improved terminal | |
| CN201146192Y (en) | High-power P type MOS device for deep groove | |
| CN204375758U (en) | There is the deep-groove power MOS component of superelevation cellular density | |
| CN104600119A (en) | Power MOSFET (metal-oxide-semiconductor field effect transistor) device capable of achieving bidirectional current flowing and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091202 Termination date: 20200108 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |