CN102208447B - Semiconductor device with super-junction structure and manufacturing method thereof - Google Patents
Semiconductor device with super-junction structure and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to a semiconductor device with a super-junction structure and a manufacturing method thereof. The semiconductor device with the super-junction structure comprises an element region and a peripheral region which are positioned on a semiconductor substrate, wherein the super-junction structure is formed in the semiconductor substrate and exists in the element region and the peripheral region; a second column of a second conductive type extends in a first conductive type epitaxial layer in a current circulating direction; a second conductive type injection region is arranged right below the second column of the second conductive type; the concentration of a second conductive type impurity in the second conductive type injection region is not lower than that of the second conductive type impurity in the second column of the second conductive type; and the width of the second conductive type injection region, namely, the distance of the second conductive type injection region in a direction vertical to the current circulation, corresponds to the width of the second column of the second conductive type above the second conductive type injection region. The semiconductor device provided by the invention has the advantages of good reverse voltage resistance, simple manufacturing process, low manufacturing cost, suitability for batch production, safety and reliability.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, especially a kind of semiconductor device and manufacture method with super-junction structure belongs to the technical field of semiconductor device.
Background technology
A kind of known semiconductor structure-super-junction structure (Super Junction) is widely used in the middle of the semiconductor power MOSFET device, and it has the characteristic of high withstand voltage and low on-resistance.Super-junction structure is formed in the drift layer of device.This drift layer comprises N conductivity type columns (N post) and P conductivity type columns (P post), and N post and P post are alternately in abutting connection with a plurality of P-N posts of forming being set to forming super-junction structure.
The N post has the N conductive type impurity, and the P post has the P conductive type impurity, and the impurity level of the impurity level of N post and P post is consistent.When having the MOSFET device cut-off of super-junction structure, N post in the super-junction structure and P post are depleted respectively, depletion layer extends from the P-N junction interface of each N post and P intercolumniation, because impurity level and the impurity level in the P post in the N post equate, therefore depletion layer extends and exhausts N post and P post fully, thereby supports device withstand voltage.The height of device withstand voltage depends primarily on the degree of depth of depletion layer.Specifically, P post and N post are darker, and formed depletion layer is also darker during the device cut-off, and device withstand voltage is just higher; Otherwise P post and N post are more shallow, and formed depletion layer is also more shallow during the device cut-off, and device withstand voltage is just lower.
1), the manufacturing process of extension, photoetching and injection repeatedly the semiconductor technology of present known manufacturing super-junction structure comprises:; Specifically, its technical process comprise (a), on given N type semiconductor epitaxial loayer by photoetching process a plurality of windows that expose to; (b), by injecting p type impurity in the N-type epitaxial loayer of ion implantation technology in the window; (c), at above-mentioned N-type epitaxial loayer growth the second N-type epitaxial loayer that is injected with p type impurity; (d), repeat the method described in (a) and the position identical window that exposes to; (e), repeat the method described in (b) and in (d) middle window that forms, inject p type impurity; (f), repeat the method growth regulation three N-type epitaxial loayers on the second N-type epitaxial loayer described in (c); (g), repeat the technological process of (d)-(f), until form the n N-type epitaxial loayer of specifying the n layer, and all include the p type impurity that forms by above-mentioned Implantation in every one deck; (h), the high temperature thermal process so that the p type impurity in above-mentioned every layer of N-type epitaxial loayer diffusion and being communicated with up and down forms the P post, thereby forms alternately in abutting connection with P post and N post, the i.e. super-junction structure of arranging.Yet, can find out from the manufacturing process of above-mentioned repeatedly extension, photoetching and injection, form the P post in the super-junction structure, its operation is very loaded down with trivial details, extension repeatedly, photoetching and injection process have increased the manufacturing cost of device greatly, simultaneously, the complicated technology flow process improves greatly for consistency and the stability requirement of technical process, thereby has increased the voltage endurance capability of device and the fluctuation risk of reliability.
2), the deep trench extension manufacturing process of filling the semiconductor technology of present known manufacturing super-junction structure also comprises:." manufacture method of super junction MOSFET " introduced among the Chinese patent CN 101872724A just related to a kind of method of making super-junction structure with deep trench extension fill process.Specifically, its technical process comprise (a), at given N type semiconductor epitaxial loayer growth etching groove hard mask layer; (b), utilize photoetching to form the window of etching groove; (c), utilize hard mask layer as masking layer, etch deep trench at the N-type epitaxial loayer; (d), utilize epitaxy technique that P type extension is inserted deep trench, and utilize polysilicon that deep trench is filled up; (e), remove the hard mask layer of N-type epi-layer surface by the method for etching or chemico-mechanical polishing, thereby form alternately in abutting connection with P post and N post, the i.e. super-junction structure of arranging.Can find out from the manufacturing process that above-mentioned deep trench extension is filled, the P post degree of depth in the super-junction structure is to be determined by the deep plough groove etched degree of depth, and gash depth is darker, and super-junction structure is just darker, and the depletion layer that can obtain is just thicker, thereby voltage endurance capability will be higher.Yet, the degree of depth of groove mainly is that the capacity of equipment by etching groove is determined, for example for the device of 650V, its gash depth needs 35um-40um usually, and this degree of depth is for the requirement of etching groove equipment unusual height, if need higher withstand voltage device, so under the prerequisite that only changes gash depth, what will become is very difficult, and simultaneously, cost also can increase greatly.If resistivity that will be by increasing epitaxial loayer or thickness obtain higher withstand voltage, will greatly increase so the conducting resistance of device, thereby reduce the characteristic superiority of super-junction structure.And, utilize epitaxy technique to fill darker groove, the difficulty of technique and cost are all very high, also are unfavorable for stable batch production.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of semiconductor device and manufacture method thereof with super-junction structure is provided, its reverse voltage endurance is good, and manufacturing process is simple, and low cost of manufacture is suitable for batch production, and is safe and reliable.
According to technical scheme provided by the invention, described semiconductor device with super-junction structure, on the top plan view of described semiconductor device, comprise the element area and the neighboring area that are positioned on the semiconductor substrate, described element area is positioned at the center of semiconductor substrate, the neighboring area is positioned at the periphery of element area, and around described element area; On the cross section of described semiconductor device, in the first conduction epitaxial loayer of semiconductor substrate, comprise some to the first post with first conduction type and the second post with second conduction type; Described the first post and the second post extend in the first conductive type epitaxial layer of semiconductor substrate along the direction of current flowing; On the direction of vertical current circulation, by described the first post be connected arranging the many PN post is alternately connected that post consists of, in semiconductor substrate, form super-junction structure; Described super-junction structure is present in element area and neighboring area; Its innovation is:
On the cross section of described semiconductor device, the second post of the second conduction type extends in the first conductive type epitaxial layer along the direction of current flowing, and the degree of depth of the second post extension is less than the thickness of the first conductive type epitaxial layer;
On the cross section of described semiconductor device, be provided with the second conduction type injection region under described the second conduction type the second post, described the second conduction type injection region is surrounded by the second post of the second conduction type of the first conductive type epitaxial layer around the second conduction type injection region and top, the second conduction type injection region;
The second conductive type impurity concentration in described the second conduction type injection region is not less than the second conductive type impurity concentration in the second conduction type the second post;
The width of the second conduction type injection region, namely perpendicular to the distance on the current flowing direction, corresponding with the width of top, the second conduction type injection region the second conduction type the second post.
On the cross section of described semiconductor device, the width of described the second conduction type injection region, namely perpendicular to the distance on the current flowing direction, consistent or close with the width of top, the second conduction type injection region the second conduction type the second post.
On the cross section of described semiconductor device, right width and the degree of depth of PN post is all identical arbitrarily in the element area.
On the cross section of described semiconductor device, described element area comprises plane MOS structure or groove type MOS structure.
A kind of manufacture method with semiconductor device of super-junction structure, the manufacture method of described semiconductor device comprises the steps:
A, provide the semiconductor substrate with first conduction type, described semiconductor substrate to comprise the first conductive type epitaxial layer and the first conductivity type substrate; B, at the first conductive type epitaxial layer surface deposition hard mask layer corresponding to described semiconductor substrate; C, optionally shelter and the etching hard mask layer, form the hard mask open of a plurality of etching grooves, by described hard mask open, utilize the anisotropic lithographic method to form a plurality of grooves at the first conductive type epitaxial layer; D, utilize the first conductive type epitaxial layer surface hard mask layer as injecting masking layer, to above-mentioned channel bottom Implantation the second conductive type impurity, under the groove bottom land, form the second conduction type injection region; The hard mask layer on e, removal the first conductive type epitaxial layer surface; F, on the first conductive type epitaxial layer surface deposit the second conductive type epitaxial layer, described epitaxial loayer is filled in the above-mentioned groove, and is covered in the surface of the first conductive type epitaxial layer; G, the second conductive type epitaxial layer that covers the first conductive type epitaxial layer surface is polished and planarization, in the first conductive type epitaxial layer, form the second post with second conduction type; H, on the surface of above-mentioned semiconductor substrate corresponding to the first conductive type epitaxial layer, by conventional semiconductor technology, obtain element area corresponding to semiconductor device and neighboring area; Described element area comprises plane MOS structure or groove type MOS structure.
Described hard mask layer is that LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.The material of described semiconductor substrate comprises silicon.
The second conductive type impurity concentration in described the second conduction type injection region is not less than the second conductive type impurity concentration in the second conduction type the second post.
The degree of depth of described groove is less than the thickness of the first conductive type epitaxial layer in the semiconductor substrate.
On the cross section of described semiconductor device, the first conductive type epitaxial layer that forms the second conduction type the second post both sides in the first conductive type epitaxial layer forms the first post with first conduction type, described the second post with second conduction type and the first post with first conduction type form PN post pair, and right width and the degree of depth of PN post is all identical arbitrarily in the element area.
Described " the first conduction type " and " the second conduction type " are among both, and for the N type semiconductor device, the first conduction type refers to N-type, and the second conduction type is the P type; For the P type semiconductor device, the first conduction type is just in time opposite with type and the N type semiconductor device of the second conduction type indication.
Advantage of the present invention:
1, by the second conduction type injection region is set below the second post of the second conduction type, so that device is when cut-off, except the first post of the second post of the second conduction type and the first conduction type fully exhaust produce the first depletion layer support withstand voltage, the second conduction type injection region and the first conductive type epitaxial layer also can fully exhaust generation the second depletion layer and support withstand voltage, therefore, when keeping the super-junction structure degree of depth, be the PN post under the constant prerequisite of the degree of depth, increasing by the second conduction type injection region can Effective Raise device withstand voltage ability and reliability.
2, when device will reach the withstand voltage target of expection setting, adding described the second conduction type injection region can guarantee to reduce the second post degree of depth, i.e. gash depth of the second conduction type under the prerequisite that the device withstand voltage ability is constant or voltage endurance capability improves; Can greatly reduce like this etching groove and with the technology difficulty of the second conductive type epitaxial layer filling groove, improve technology stability; Simultaneously, select also can correspondingly to increase for the equipment of above-mentioned two step process, thus the processing cost of reduction device.
3, described the second conduction type injection region forms by inject the second conductive type impurity at channel bottom, its used ion implantation technology, the semiconductor technology of process conditions and equipment and routine is fully compatible, simply should control, be very suitable for batch production, therefore, when guaranteeing properties of product, save cost, improved cost performance.
Description of drawings
Fig. 1 is structural representation of the present invention.
Fig. 2 ~ Fig. 8 is the implementation processing step cutaway view of semiconductor device of the present invention, wherein:
Fig. 2 is the structural representation of semiconductor substrate.
Fig. 3 is the cutaway view after the hard mask open of formation.
Fig. 4 is the cutaway view behind the formation groove.
Fig. 5 is the cutaway view behind formation the second conduction type injection region.
Fig. 6 is the cutaway view behind formation the second conductive type epitaxial layer.
Fig. 7 is to the cutaway view after the second conductive type epitaxial layer planarization.
Fig. 8 is the cutaway view after the complete MOS structure of formation.
Fig. 9 is the reverse withstand voltage depletion layer schematic diagram in semiconductor device components of the present invention zone.
Figure 10 a ~ Figure 11 is cutaway view and the reverse withstand voltage source-drain current-voltage pattern of emulation of existing structure and element area of the present invention, wherein:
Figure 10 a is the element area cutaway view of existing structure.
Figure 10 b is the reverse withstand voltage source-drain current-voltage pattern of the element area emulation of existing structure.
Figure 11 is the reverse withstand voltage source-drain current-voltage pattern of element area emulation of the present invention.
Embodiment
The invention will be further described below in conjunction with concrete drawings and Examples.
Such as Fig. 1 ~ shown in Figure 9: take the N type semiconductor device as example, the present invention includes source metal 1, conductive polycrystalline silicon 2, P post 3, N post 4, insulating medium layer 5, N-type epitaxial loayer 6, P type injection region 7, N+ substrate 8, P type well region 9, N-type source region 10, MOS structure 11, insulating oxide 12, hard mask open 13, hard mask layer 14, groove 15, P type epitaxial loayer 16, the first depletion layer 17 and the second depletion layer 18.
Such as Fig. 1 and shown in Figure 8: as described in have on the cross section of semiconductor device of super-junction structure, comprise element area and neighboring area, described element area is positioned at the central area of semiconductor substrate, and the neighboring area is positioned at the periphery of element area, and around described element area.Described semiconductor substrate comprises N-type epitaxial loayer 6 and N+ substrate 8, and described N-type epitaxial loayer 6 is in abutting connection with described N+ substrate 8.On the cross section of described semiconductor device with super-junction structure, comprise manyly to the first post with N-type conduction type and the second post with P-type conduction type in the described N-type epitaxial loayer 6, namely N post 4 forms the first post, and P post 3 forms the second post.Described N post 4 and P post 3 are arranged alternately in N-type epitaxial loayer 6, form super-junction structure; Described N post 4 and P post 3 be along the N-type epitaxial loayer 6 interior extensions at semiconductor substrate of the direction of current flowing, and namely P post 3 extends to the directions near N+ substrate 8 N-type epitaxial loayer 6 is interior; On the direction perpendicular to current flowing, N post 4 alternately is connected with P post 3 the formation super-junction structure is set, and described super-junction structure is arranged at device element area and neighboring area.
On described semiconductor device cross-section, be provided with in the described N-type epitaxial loayer 6 many to alternately in abutting connection with the PN post that arranges pair, every pair of PN post is to the formation that links to each other with a P post 3 by a N post 4.Described P post 3 extends in N-type epitaxial loayer 6 interior directions to N+ substrate 8 along the direction of current flowing, and the distance of extension is less than the thickness of N-type epitaxial loayer 6; Right width and the degree of depth of PN post is all identical arbitrarily in the element area.N-type epitaxial loayer 6 is being divided into the adjacent N post 4 of a plurality of and corresponding P post 3 by a plurality of P posts 3 on the direction of current flowing.Under P post 3, be provided with P type injection region 7, described P type injection region 7 is surrounded by the P post 3 of its top and N-type epitaxial loayer 6 on every side, the width of P type injection region 7 and the width of P post 3 are basically identical, P type injection region 7 corresponding to P-type conduction type dopant concentration greater than P post 3 corresponding P-type conduction type dopant concentration.
On the cross section of described semiconductor device, the element of described element area has MOS structure 11, and described MOS structure 11 comprises plane MOSFET or trench MOSFEF structure; Electric current is in longitudinal flow, namely perpendicular to the direction that MOSFET is set in the element area; Also namely flow along the direction of 8 of N-type epitaxial loayer 6 and N+ substrates.Among Fig. 1 and Fig. 8, provided the structure of plane MOSFET.
On the cross section of described semiconductor device, separate P type well region 9 is formed at the top of super-junction structure in described element area, and described two adjacent P type well regions 9 are isolated by corresponding N post 4, and P type well region 9 is connected with the P post 3 of below; Described P type well region 9 utilizes the N post isolated, guarantees the passage of current flowing in the MOS structure 11.On the top of P type well region 9, separate N-type source region 10 is set.The N-type source region 10 of part, P type well region 9 N post 4 poor with the horizontal junction depth in N-type source region 10, isolation P type well region are insulated oxide layer 12 and cover, be coated with conductive polycrystalline silicon 2 above the insulating oxide 12, the insulating oxide 12 on the element area and conductive polycrystalline silicon 2 are insulated dielectric layer 5 and coat.Above the insulating medium layer 5 and zone of 5 of adjacent insulating medium layers covers and is filled with source metal 1, and source metal 1 is electrically connected into equipotential with the N-type source region 10 of exposing to the open air out with P type well region 9.Described insulating medium layer 5 also covers the upper surface of neighboring area super-junction structure, and described source metal 1 also extends the upper surface that is covered in part neighboring area insulating medium layer 5; Be positioned on the insulating medium layer 5 of element area and joint portion, neighboring area and be coated with conductive polycrystalline silicon 2.
The semiconductor device structure of said structure, adopt following processing step to realize:
A, provide the semiconductor substrate with N-type conduction type, the material of described semiconductor substrate comprises silicon; Described semiconductor substrate comprises N-type epitaxial loayer 6 and N+ substrate 8, and wherein N-type epitaxial loayer 6 is used for providing the N post 4 of super-junction structure, and wherein N+ substrate 8 has the N+ conduction type of high-dopant concentration; N-type epitaxial loayer 6 is in abutting connection with N+ substrate 8, as shown in Figure 2;
B, at N-type epitaxial loayer 6 surface deposition hard mask layers 14 corresponding to described semiconductor substrate; Described hard mask layer 14 can adopt LPTEOS(low-pressure chemical vapor deposition tetraethyl orthosilicate), thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride, forms hard mask by photoetching and anisotropic etching thereafter;
C, form one deck hard mask layers 14 at N-type epitaxial loayer 6, by optionally sheltering and etching, formation has a plurality of hard mask open 13 for etching groove, and described hard mask open 13 comprises the hard mask open that is positioned at element area and the hard mask open that is positioned at the neighboring area; Utilize the anisotropic dry etching, form groove 15; Described groove 15 by N-type epitaxial loayer 6 surfaces downwards at N-type epitaxial loayer 6 interior extension distance to a declared goal, groove 15 is at the degree of depth of the N-type epitaxial loayer 6 interior extensions thickness less than the N-type epitaxial loayer, and N-type epitaxial loayer 6 is divided into a plurality of N posts 4, the degree of depth of described N post 4 is consistent with the degree of depth of groove 15; As shown in Figure 3;
D, utilize the lip-deep hard mask layers 14 of N-type epitaxial loayer 6 as injecting masking layers, inject p type impurity to above-mentioned groove 15 bottoms by Implantation, form the P type injection region 7 that is positioned under groove 15 bottom lands; As shown in Figure 4;
The hard mask layer 14 on e, removal N-type epitaxial loayer 6 surfaces;
F, on N-type epitaxial loayer 6 surfaces deposit P type epitaxial loayer 16, described P type epitaxial loayer 16 is filled in the above-mentioned groove 15, and covers on the surface of N-type epitaxial loayer 6; Behind groove 15 interior injection P type epitaxial loayers 16, P type epitaxial loayer 16 is at N-type epitaxial loayer 6 interior formation P posts 3, thereby at N post 4 and P post 3 that the 6 interior formation of N-type epitaxial loayer are arranged alternately, forms super-junction structure; P post 3 corresponding P-type conduction type dopant concentration are less than the impurity concentration of the P-type conduction type of above-mentioned P type injection region 7; As shown in Figure 6;
G, the P type epitaxial loayer 16 that covers N-type epitaxial loayer 6 surfaces is polished and planarization, remove the P type epitaxial loayer 16 on N-type epitaxial loayer 6 surfaces after, have many semiconductor substrate structures to the PN post thereby form; As shown in Figure 7;
In certain embodiments, also can not remove this P type epitaxial loayer of part, namely keep the P type epitaxial loayer of suitable thickness at device surface;
H, on the surface of above-mentioned semiconductor substrate corresponding to N-type epitaxial loayer 6, by conventional semiconductor technology, obtain element area corresponding to semiconductor device and neighboring area; Described element area comprises plane MOS structure or groove type MOS structure; Such as Fig. 1 and shown in Figure 8; The manufacture method of described plane MOS structure can be with reference to disclosed manufacture method among the ZL01807673.4; The manufacture method of described groove type MOS structure can be with reference to disclosed manufacture method among the ZL200510110709.8; By forming plane MOS structure or groove type MOS structure at element area, obtain having the semiconductor device structure of super-junction structure.
As shown in Figure 9: the working mechanism that the present invention has the semiconductor device of super-junction structure is; Described P type injection region 7 be positioned at P post 3 under, width and P post 3 width are basically identical, and are surrounded by P post 3 and N-type epitaxial loayer 6.When semiconductor device reverse when withstand voltage, be that drain electrode applies positive voltage (corresponding to the N-type device), gate electrode is connected zero potential with the source electrode, the PN junction reverse bias that is consisted of by P post 3 and N post 4, depletion layer is from the PN junction interface to P post 3 and 4 extensions of N post and exhaust P post 3 and N post 4 fully, forms the first depletion layer 17; Meanwhile, the PN junction that is made of P type injection region 7 and N-type epitaxial loayer 6 also is reverse bias, depletion layer extends from the PN junction interface to P type injection region 7 and N-type epitaxial loayer 6, because the impurity concentration of P type injection region 7 is more than or equal to P post 3 impurity concentrations, and P post 3 impurity concentrations are greater than N post 4 and N-type epitaxial loayer 6 impurity concentrations, therefore, above-mentioned depletion layer is greater than distance in the 7 interior extensions of P type injection region in the distance of N-type epitaxial loayer 6 interior extensions, and because the width of the width of P type injection region 7 and P post 3 is basically identical, so the depletion layer that adjacent two P type injection regions 7 and the N-type epitaxial loayer 6 between it produce can fully link together, and forms the second depletion layer 18; Described the first depletion layer 17 and the second depletion layer 18 also can fully be connected and form the depletion layer of an integral body supporting device withstand voltage simultaneously.Under the condition that is keeping identical P post 3 degree of depth, increase P type injection region 7 and will increase certain thickness depletion layer, therefore just can increase the voltage endurance capability of device; In like manner, when when guaranteeing to reach the device withstand voltage demand of appointment, increase the degree of depth that P type injection region 7 can correspondingly reduce P post 3, thereby reduce the technology difficulty of groove 15 etchings and P type epitaxial loayer 16 filling grooves, improve technology stability, increase the cost performance of product.
Figure 10 a, Figure 10 b and Fig. 9, shown in Figure 11 have contrasted existing tradition and have had the semiconductor device components zone of super-junction structure and cutaway view and the reverse withstand voltage source-drain current-voltage pattern of emulation that the present invention has added the semiconductor device components district with super-junction structure of P type injection region 7.Wherein Figure 10 a is existing semiconductor device components zone with super-junction structure, it is characterized in that the P post 3 that consists of super-junction structure extends to N+ substrate layer 8, and its below does not have a P type injection region 7, when withstand voltage, mainly is to come withstand voltage by the depletion layer that P post 3 and N post 4 produce reverse; Wherein Figure 10 b is under the structure of Figure 10 a, when N-type epitaxial loayer 6 thickness are 45 μ m, withstand voltage result was leaked in the source of emulation gained when P post 3 degree of depth were 45 μ m, and withstand voltage is about 795V, abscissa represents the reverse withstand voltage of semiconductor device among Figure 10 b, and ordinate represents the degree of depth of P post 3; Wherein Fig. 9 is the semiconductor device components zone that the present invention has super-junction structure, it is characterized in that the P post 3 that consists of super-junction structure does not extend to N+ substrate 8, simultaneously, its below is provided with the width P type injection region 7 basically identical with it, P type injection region 7 is surrounded by P post 3 and N-type epitaxial loayer 6, reverse when withstand voltage, the depletion layer that produces except P post 3 and N post 4 support withstand voltage, P type injection region 7 and N-type epitaxial loayer 6 can produce equally depletion layer and support withstand voltage; Wherein Figure 11 is under the structure of Fig. 9, when N-type epitaxial loayer 6 thickness are 45 μ m, the withstand voltage result of drain-source of emulation gained when P post 3 degree of depth are 39 μ m, the in length and breadth coordinate of Figure 11 represents that the implication that represents with Figure 10 b is identical, can find out that its withstand voltage is about 800V, the voltage endurance capability in the time of can reaching P post 3 degree of depth fully and be 45 μ m.Guaranteeing under the constant prerequisite of voltage endurance capability groove 15 etching depths to have been reduced by 6 μ m, improved the technology stability of etching groove and filling, reduced processing cost, simplified manufacturing process, adaptability is good, and is safe and reliable.
Claims (9)
1. semiconductor device with super-junction structure, on the top plan view of described semiconductor device, comprise the element area and the neighboring area that are positioned on the semiconductor substrate, described element area is positioned at the center of semiconductor substrate, the neighboring area is positioned at the periphery of element area, and around described element area; On the cross section of described semiconductor device, in the first conduction epitaxial loayer of semiconductor substrate, comprise some to the first post with first conduction type and the second post with second conduction type; Described the first post and the second post extend in the first conductive type epitaxial layer of semiconductor substrate along the direction of current flowing; On the direction of vertical current circulation, by described the first post be connected arranging the many PN post is alternately connected that post consists of, in semiconductor substrate, form super-junction structure; Described super-junction structure is present in element area and neighboring area; It is characterized in that:
On the cross section of described semiconductor device, the second post of the second conduction type extends in the first conductive type epitaxial layer along the direction of current flowing, and the degree of depth of the second post extension is less than the thickness of the first conductive type epitaxial layer;
On the cross section of described semiconductor device, be provided with the second conduction type injection region under described the second conduction type the second post, described the second conduction type injection region is surrounded by the second post of the second conduction type of the first conductive type epitaxial layer around the second conduction type injection region and top, the second conduction type injection region;
The second conductive type impurity concentration in described the second conduction type injection region is not less than the second conductive type impurity concentration in the second conduction type the second post;
The width of the second conduction type injection region, namely perpendicular to the distance on the current flowing direction, consistent with the width of top, the second conduction type injection region the second conduction type the second post.
2. the semiconductor device with super-junction structure according to claim 1 is characterized in that: on the cross section of described semiconductor device, right width and the degree of depth of PN post is all identical arbitrarily in the element area.
3. the semiconductor device with super-junction structure according to claim 1, it is characterized in that: on the cross section of described semiconductor device, described element area comprises plane MOS structure or groove type MOS structure.
4. the manufacture method with semiconductor device of super-junction structure is characterized in that, the manufacture method of described semiconductor device comprises the steps:
(a), provide the semiconductor substrate with first conduction type, described semiconductor substrate to comprise the first conductive type epitaxial layer and the first conductivity type substrate;
(b), at the first conductive type epitaxial layer surface deposition hard mask layer corresponding to described semiconductor substrate;
(c), optionally shelter and the etching hard mask layer, form the hard mask open of a plurality of etching grooves, by described hard mask open, utilize the anisotropic lithographic method to form a plurality of grooves at the first conductive type epitaxial layer;
(d), the hard mask layer that utilizes the first conductive type epitaxial layer surface is as injecting masking layer, to above-mentioned channel bottom Implantation the second conductive type impurity, forms the second conduction type injection region under the groove bottom land;
(e), remove the hard mask layer on the first conductive type epitaxial layer surface;
(f), on the first conductive type epitaxial layer surface deposit the second conductive type epitaxial layer, described epitaxial loayer is filled in the above-mentioned groove, and is covered in the surface of the first conductive type epitaxial layer;
(g), the second conductive type epitaxial layer that covers the first conductive type epitaxial layer surface is polished and planarization, in the first conductive type epitaxial layer, form the second post with second conduction type;
(h), on the surface of above-mentioned semiconductor substrate corresponding to the first conductive type epitaxial layer, obtain element area corresponding to semiconductor device and neighboring area; Described element area comprises plane MOS structure or groove type MOS structure;
The degree of depth of described groove is less than the thickness of the first conductive type epitaxial layer in the semiconductor substrate;
Described element area is positioned at the center of semiconductor substrate, and the neighboring area is positioned at the periphery of element area, and around described element area.
5. described manufacture method with semiconductor device of super-junction structure according to claim 4, it is characterized in that: described hard mask layer is that LPTEOS, thermal oxidation silicon dioxide add chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride.
6. described manufacture method with semiconductor device of super-junction structure according to claim 4, it is characterized in that: the material of described semiconductor substrate comprises silicon.
7. described manufacture method with semiconductor device of super-junction structure according to claim 4, it is characterized in that: the second conductive type impurity concentration in described the second conduction type injection region is not less than the second conductive type impurity concentration in the second conduction type the second post.
8. described manufacture method with semiconductor device of super-junction structure according to claim 4, it is characterized in that: the degree of depth of described groove is less than the thickness of the first conductive type epitaxial layer in the semiconductor substrate.
9. described manufacture method with semiconductor device of super-junction structure according to claim 4, it is characterized in that: on the cross section of described semiconductor device, the first conductive type epitaxial layer that forms the second conduction type the second post both sides in the first conductive type epitaxial layer forms the first post with first conduction type, described the second post with second conduction type and the first post with first conduction type form PN post pair, and right width and the degree of depth of PN post is all identical arbitrarily in the element area.
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| CN 201110132941 CN102208447B (en) | 2011-05-20 | 2011-05-20 | Semiconductor device with super-junction structure and manufacturing method thereof |
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| CN102208447B true CN102208447B (en) | 2013-04-24 |
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| CN104779297A (en) * | 2015-04-24 | 2015-07-15 | 无锡同方微电子有限公司 | High-voltage super junction MOSFET structure and manufacturing method thereof |
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| CN107342226B (en) * | 2017-07-19 | 2020-07-31 | 无锡新洁能股份有限公司 | Manufacturing method of ultra-small unit size longitudinal super junction semiconductor device |
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| CN109755291B (en) * | 2017-11-08 | 2022-08-16 | 深圳尚阳通科技有限公司 | Super junction device and manufacturing method thereof |
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