CN104779297A - High-voltage super junction MOSFET structure and manufacturing method thereof - Google Patents
High-voltage super junction MOSFET structure and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 4
- 238000003892 spreading Methods 0.000 claims description 4
- 230000007480 spreading Effects 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 9
- 238000000407 epitaxy Methods 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a high-voltage super junction MOSFET structure and a manufacturing method thereof. The structure comprises at least one transistor unit. Each transistor unit comprises an N-type heavy doping substrate and an N-type light doping epitaxial layer formed on the N-type heavy doping substrate, wherein a first P column and a second P column are formed in the N-type light doping epitaxial layer, the top end of the first P column and the top end of the second P column are connected with a first P-type body area and a second P-type body area respectively, and the first P-type body area and the second P-type body area are located in the N-type light doping epitaxial layer; a gate structure is formed on the surface of the N-type light doping epitaxial layer and located between the first P column and the second P column, the two ends of the gate structure are in contact with the first P-type body area and the second P-type body area respectively, and the bottom end of the first P column and the bottom end of the second P column are each connected with a P-island structure. The voltage-resistant performance of the super junction MOSFET structure can be effectively improved, and the super junction MOSFET structure is further improved in the high voltage and super-high voltage direction.
Description
Technical field
The invention belongs to field of semiconductor devices, relate to a kind of high pressure super node MOSFET structure and preparation method thereof.
Background technology
VDMOSFET (high-voltage power MOSFET) can reduce conducting resistance by the thickness of thinning drain terminal drift region, but, the thickness of thinning drain terminal drift region will reduce the puncture voltage of device, therefore in VDMOSFET, the puncture voltage improving device and the conducting resistance reducing device are conflicts, super node MOSFET adopts new structure of voltage-sustaining layer, utilize a series of P type that is alternately arranged and N type semiconductor thin layer, under lower reverse voltage, P type N-type region is exhausted, realize electric charge mutually to compensate, thus make N-type region realize high puncture voltage under high-dopant concentration, thus obtain low on-resistance and high-breakdown-voltage simultaneously, break traditions the theoretical limit of power MOSFET ON resistance.
It is low that super node MOSFET has conduction loss, gate charge is low, switching speed is fast, device heating is little, the advantage that efficiency is high, product can be widely used in PC, notebook computer, net book or mobile phone, the power supply of illumination (high-voltage gas discharging light) product and the high-end consumption electronic product such as television set (liquid crystal or plasma TV) and game machine or adapter.
Refer to Fig. 1 and Fig. 2, be shown as conventional high pressure super node MOSFET structure (hereinafter referred to as HV-MOS) and low pressure super node MOSFET structure (hereinafter referred to as low pressure LV-MOS) respectively.As shown in Figure 1, high pressure super node MOSFET comprises N-type heavy doping substrate 101, N-type light dope epitaxial loayer 102 and the P post 103 be formed in described N-type light dope epitaxial loayer 102 and P type tagma 104, and described N-type light dope epitaxial loayer 102 surface is formed with gate oxide 105 and polysilicon gate 106.As shown in Figure 2, low pressure super node MOSFET comprises and is formed at polysilicon pillar 107 in N-type epitaxy layer and polysilicon gate 108.HV-MOS and LV-MOS is by certain technology mode in N-type epitaxy layer, forms the groove structure of a longitudinal direction, while device withstand voltage, greatly can reduce conducting resistance like this, improves device performance.
But high-voltage MOS pipe and low pressure metal-oxide-semiconductor have again a lot of difference on device architecture and process:
1), in lateral device dimensions, the primitive unit cell size (pitch) of HV-MOS is general at tens microns, and the pitch of LV-MOS generally only has several microns.On identical chip area, the primitive unit cell density of LV-MOS can exceed much than HV-MOS, so low-voltage device requires higher for technology feature size and lithography alignment accuracy etc., difficulty is larger.
2), on device longitudinal size, the N-type epitaxy layer thickness of HV-MOS and gash depth generally have tens microns, and LV-MOS can at several micron.For the such deep groove structure introduced, its degree of depth is darker, and technology difficulty is larger, so high tension apparatus depends on the degree of depth and the technique of groove more;
3) groove realize in technique, the P post (Ppillar-trench) of HV-MOS is made up of p type impurity, first N-type epitaxy layer utilizes deep etching technique directly dig out groove structure, then epitaxial growth p type impurity layer.And the polysilicon pillar of LV-MOS is made up of silicon dioxide layer and polysilicon layer, in N-type epitaxy layer, dig out groove, then heat growth silicon dioxide dielectric layer, carry out the deposit of polysilicon, the polysilicon pillar needed for formation.
For super node MOSFET, the withstand voltage P post primarily of deep groove structure decides, but the restriction of technological ability, often limit the development continued toward high pressure/superhigh pressure direction.
Therefore, provide a kind of high pressure super node MOSFET structure and preparation method thereof, be necessary to promote MOSFET element voltage endurance capability further.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of high pressure super node MOSFET structure and preparation method thereof, and the voltage endurance capability for solving prior art mesohigh super node MOSFET structure needs the problem improved further.
For achieving the above object and other relevant objects, the invention provides a kind of high pressure super node MOSFET structure, comprise at least one transistor unit, described transistor unit comprises:
N-type heavy doping substrate and the N-type light dope epitaxial loayer be formed on described N-type heavy doping substrate;
A P post and the 2nd P post is formed in described N-type light dope epitaxial loayer;
A described P post and the 2nd P capital end are connected to a P type tagma and the 2nd P type tagma, and a described P type tagma and the 2nd P type tagma are positioned at described N-type light dope epitaxial loayer;
Described N-type light dope epi-layer surface is formed with grid structure; Described grid structure is between a described P post and the 2nd P post, and described grid structure two ends contact with a described P type tagma and the 2nd P type tagma respectively;
Wherein:
A described P post and the 2nd P post bottom are all connected with a P island structure.
Alternatively, the width of described P island structure is more than or equal to the width of a described P post or the 2nd P post.
Alternatively, the thickness of described P island structure is 1 ~ 3 micron.
Alternatively, the degree of depth of a described P post and the 2nd P post is 30 ~ 60 microns.
Alternatively, a described P post and the 2nd P post are p type single crystal silicon.
Alternatively, N-type heavy doping source region and P type heavy doping contact zone is all formed with in a described P type tagma and the 2nd P type tagma; Described N-type heavy doping source region and P type heavy doping contact zone contact with the source metal of device surface; Insulator separation is passed through between described source metal and described grid structure.
Alternatively, described grid structure comprises the gate oxide being formed at described N-type light dope epi-layer surface and the polysilicon gate being formed at described gate oxide surface.
The present invention also provides a kind of manufacture method of high pressure super node MOSFET structure, comprises the following steps:
The semiconductor chip that one comprises N-type heavy doping substrate and N-type light dope epitaxial loayer from bottom to top is successively provided, carries out injecting and spreading on described N-type light dope epitaxial loayer top, form a P type tagma and the 2nd P type tagma;
Etch, the first groove and the second groove is formed in described N-type light dope epitaxial loayer, wherein, first, second groove described runs through first, second P type tagma described respectively and extends toward described N-type light dope epitaxial loayer bottom direction, and does not run through described N-type light dope epitaxial loayer;
Ion implantation is carried out to described first groove and the second channel bottom, forms a P island structure respectively at first, second channel bottom described;
In described first groove and the second groove, fill p type semiconductor layer, form a P post and the 2nd P post;
Grid structure is formed in described N-type light dope epi-layer surface; Described grid structure is between a described P post and the 2nd P post, and described grid structure two ends contact with a described P type tagma and the 2nd P type tagma respectively.
Alternatively, the thickness of described P island structure is 1 ~ 3 micron.
Alternatively, after described N-type light dope epi-layer surface forms grid structure, further comprising the steps of:
In a described P type tagma and the 2nd P type tagma, carry out source region injection, form N-type heavy doping source region;
The insulating barrier of described grid structure is covered in described N-type light dope epi-layer surface growth, perform hole of going forward side by side etching and hole are injected, obtain contact hole and be positioned at the P type heavy doping contact zone bottom contact hole, described P type heavy doping contact zone is formed in a described P type tagma and the 2nd P type tagma and adjacent described N-type heavy doping source region;
Form source metal at described surface of insulating layer, described source metal is filled into described contact hole and contacts with described N-type heavy doping source region and P type heavy doping contact zone; By described insulator separation between described source metal and described grid structure.
As mentioned above, high pressure super node MOSFET structure of the present invention and preparation method thereof, there is following beneficial effect: in high pressure super node MOSFET structure of the present invention, one P post and the 2nd P post bottom are all connected with a P island structure, the existence of described P island structure suitably can increase gash depth on the one hand, on the other hand, for darker groove, due to the restriction of process conditions, channel bottom is often narrower, doping can be lower, and form described P island structure by carrying out doping at channel bottom, can optimize channel bottom doping.The factor of above two aspects can make high pressure super node MOSFET realize higher voltage endurance capability.
Accompanying drawing explanation
Fig. 1 is shown as the structural representation of prior art mesohigh super node MOSFET.
Fig. 2 is shown as the structural representation of prior art mesolow super node MOSFET.
Fig. 3 ~ Fig. 4 is shown as the schematic diagram of high pressure super node MOSFET structure of the present invention.
Fig. 5 is shown as in the manufacture method of high pressure super node MOSFET structure of the present invention and carries out injecting and spreading on described N-type light dope epitaxial loayer top, forms the schematic diagram in first, second P type tagma.
Fig. 6 is shown as in the manufacture method of high pressure super node MOSFET structure of the present invention and etches, and forms the schematic diagram of the first groove and the second groove in described N-type light dope epitaxial loayer.
Fig. 7 is shown as the schematic diagram forming a P island structure in the manufacture method of high pressure super node MOSFET structure of the present invention at first, second channel bottom described respectively.
Fig. 8 is shown as in the manufacture method of high pressure super node MOSFET structure of the present invention and fills p type semiconductor layer in described first groove and the second groove, forms the schematic diagram of a P post and the 2nd P post.
Fig. 9 is shown as the schematic diagram forming grid structure in the manufacture method of high pressure super node MOSFET structure of the present invention in described N-type light dope epi-layer surface.
Figure 10 is shown as the schematic diagram forming insulating barrier, contact hole, P type heavy doping contact zone and source metal in the manufacture method of high pressure super node MOSFET structure of the present invention.
Element numbers explanation
101,201 N-type heavy doping substrates
102,202 N-type light dope epitaxial loayers
103 P posts
104 P type tagmas
105,207 gate oxides
106,108,208 polysilicon gates
107 polysilicon pillars
203 the one P posts
204 the 2nd P posts
205 the one P type tagmas
206 the 2nd P type tagmas
209 P island structures
210 N-type heavy doping source regions
211 P type heavy doping contact zones
212 source metal
213 insulating barriers
214 first grooves
215 second grooves
216 contact holes
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 3 to Figure 10.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment one
The invention provides a kind of high pressure super node MOSFET structure, refer to Fig. 3, be shown as the schematic diagram of this structure, comprise at least one transistor unit, described transistor unit comprises:
N-type heavy doping substrate 201 and the N-type light dope epitaxial loayer 202 be formed on described N-type heavy doping substrate 201;
A P post 203 and the 2nd P post 204 is formed in described N-type light dope epitaxial loayer 202;
A described P post 203 and the 2nd P post 204 top are connected to P type tagma 205 and a 2nd P type tagma 206, and a described P type tagma 205 and the 2nd P type tagma 206 are positioned at described N-type light dope epitaxial loayer 202;
Described N-type light dope epitaxial loayer 202 surface is formed with grid structure; Described grid structure is between a described P post 205 and the 2nd P post 206, and described grid structure two ends contact with a described P type tagma 205 and the 2nd P type tagma 206 respectively;
Wherein:
A described P post 203 and the 2nd P post 204 bottom are all connected with a P island structure 209.
Concrete, the width of described P island structure 209 is more than or equal to the width of a described P post 203 or the 2nd P post 204.The existence of described P island structure can suitably increase the groove structure degree of depth, and in the present embodiment, the thickness of described P island structure 209 is preferably 1 ~ 3 micron.Meanwhile, described P island structure 209 can also optimize the doping bottom groove structure.
In the present embodiment, described grid structure comprises the gate oxide 207 being formed at described N-type light dope epitaxial loayer 202 surface and the polysilicon gate 208 being formed at described gate oxide 207 surface.The degree of depth of a described P post 203 and the 2nd P post 204 is 30 ~ 60 microns.A described P post 203 and the 2nd P post 204 are p type single crystal silicon, thus MOSFET structure of the present invention is high pressure super node MOSFET.
As shown in Figure 4, N-type heavy doping source region 210 and P type heavy doping contact zone 211 is all formed with in a described P type tagma 205 and the 2nd P type tagma 206; Described N-type heavy doping source region 210 and P type heavy doping contact zone 211 contact with the source metal 212 of device surface; Isolated by insulating barrier 213 between described source metal 212 and described grid structure.
In high pressure super node MOSFET structure of the present invention, one P post and the 2nd P column bottom are all connected with a P island structure, the existence of described P island structure can suitably increase the groove structure degree of depth, on the one hand on the other hand, for darker groove, due to the restriction of process conditions, channel bottom is often narrower, and doping can be lower, and forms described P island structure by carrying out doping at channel bottom, can optimize bottom groove structure and adulterate, thus promote the voltage endurance capability of high pressure super node MOSFET structure further.
Embodiment two
The present invention also provides a kind of manufacture method of high pressure super node MOSFET structure, comprises the following steps:
First Fig. 5 is referred to, the semiconductor chip that one comprises N-type heavy doping substrate 201 and N-type light dope epitaxial loayer 202 from bottom to top is successively provided, carry out injecting and spreading on described N-type light dope epitaxial loayer 202 top, form P type tagma 205 and a 2nd P type tagma 206.
Then Fig. 5 is referred to, etch, the first groove 214 and the second groove 215 is formed in described N-type light dope epitaxial loayer 202, wherein, first, second groove described runs through first, second P type tagma described respectively and extends toward described N-type light dope epitaxial loayer 202 bottom direction, and does not run through described N-type light dope epitaxial loayer 202.
Then refer to Fig. 7, carry out ion implantation to bottom described first groove 214 and the second groove 215, form a P island structure 209 respectively at first, second channel bottom described.
Concrete, the width of described P island structure 209 is more than or equal to the width of the first groove 214 and the second groove 215.The existence of described P island structure 209 suitably can increase gash depth, and in the present embodiment, the thickness of described P island structure 209 is preferably 1 ~ 3 micron.Meanwhile, due to the restriction of process conditions, channel bottom is often narrower, and doping can be lower, and forms described P island structure 209 by carrying out doping at channel bottom, can optimize channel bottom doping.
Refer to Fig. 8 again, in described first groove and the second groove, fill p type semiconductor layer, form a P post 203 and the 2nd P post 204.
Concrete, adopt epitaxy technique to grow described p type semiconductor layer, the material of described p type semiconductor layer is p type single crystal silicon.It is pointed out that the p type semiconductor layer also multiple part as P type tagma being filled in described first groove 214 and the second groove 215 top.
Refer to Fig. 9 again, form grid structure on described N-type light dope epitaxial loayer 202 surface; Described grid structure is between a described P post 203 and the 2nd P post 204, and described grid structure two ends contact with a described P type tagma 205 and the 2nd P type tagma 206 respectively.
Concrete, first at device surface growth gate oxide 207, depositing polysilicon grid 208, and etch, obtain described grid structure.
Further, after described N-type light dope epi-layer surface forms grid structure, further comprising the steps of:
As shown in Figure 9, in a described P type tagma 205 and the 2nd P type tagma 206, carry out source region injection, form N-type heavy doping source region 210;
As shown in Figure 10, the insulating barrier 213 of described grid structure is covered in the superficial growth of described N-type light dope epitaxial loayer 202, perform hole of going forward side by side etching and hole are injected, obtain contact hole 216 and be positioned at the P type heavy doping contact zone 211 bottom contact hole, described P type heavy doping contact zone 211 is formed in a described P type tagma 205 and the 2nd P type tagma 206 and adjacent described N-type heavy doping source region 210;
As shown in Figure 4, form source metal 212 on described insulating barrier 213 surface, described source metal 212 is filled into described contact hole 216 and contacts with described N-type heavy doping source region 210 and P type heavy doping contact zone 211; Isolated by described insulating barrier 213 between described source metal 212 and described grid structure.
So far, making obtains high pressure super node MOSFET structure of the present invention, this manufacture method adds doping in one step step after deep trouth technique, a P post and the 2nd P column bottom is made all to be connected with a P island structure, effectively can improve the withstand voltage properties of super node MOSFET structure, super node MOSFET structure is advanced toward high pressure/superhigh pressure direction further.
In sum, high pressure super node MOSFET structure of the present invention and preparation method thereof, there is following beneficial effect: in high pressure super node MOSFET structure of the present invention, one P post and the 2nd P post bottom are all connected with a P island structure, the existence of described P island structure can suitably increase the groove structure degree of depth on the one hand, on the other hand, for darker groove, due to the restriction of process conditions, channel bottom is often narrower, doping can be lower, and form described P island structure by carrying out doping at channel bottom, can optimize channel bottom doping.The factor of above two aspects can make high pressure super node MOSFET realize higher voltage endurance capability.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. a high pressure super node MOSFET structure, comprises at least one transistor unit, and described transistor unit comprises:
N-type heavy doping substrate and the N-type light dope epitaxial loayer be formed on described N-type heavy doping substrate;
A P post and the 2nd P post is formed in described N-type light dope epitaxial loayer;
A described P post and the 2nd P capital end are connected to a P type tagma and the 2nd P type tagma, and a described P type tagma and the 2nd P type tagma are positioned at described N-type light dope epitaxial loayer;
Described N-type light dope epi-layer surface is formed with grid structure; Described grid structure is between a described P post and the 2nd P post, and described grid structure two ends contact with a described P type tagma and the 2nd P type tagma respectively;
It is characterized in that:
A described P post and the 2nd P post bottom are all connected with a P island structure.
2. high pressure super node MOSFET structure according to claim 1, is characterized in that: the width of described P island structure is more than or equal to the width of a described P post or the 2nd P post.
3. high pressure super node MOSFET structure according to claim 1, is characterized in that: the thickness of described P island structure is 1 ~ 3 micron.
4. high pressure super node MOSFET structure according to claim 1, is characterized in that: the degree of depth of a described P post and the 2nd P post is 30 ~ 60 microns.
5. high pressure super node MOSFET structure according to claim 1, is characterized in that: a described P post and the 2nd P post are p type single crystal silicon.
6. high pressure super node MOSFET structure according to claim 1, is characterized in that: be all formed with N-type heavy doping source region and P type heavy doping contact zone in a described P type tagma and the 2nd P type tagma; Described N-type heavy doping source region and P type heavy doping contact zone contact with the source metal of device surface; Insulator separation is passed through between described source metal and described grid structure.
7. high pressure super node MOSFET structure according to claim 1, is characterized in that: described grid structure comprises the gate oxide being formed at described N-type light dope epi-layer surface and the polysilicon gate being formed at described gate oxide surface.
8. a manufacture method for high pressure super node MOSFET structure, is characterized in that, comprises the following steps:
The semiconductor chip that one comprises N-type heavy doping substrate and N-type light dope epitaxial loayer from bottom to top is successively provided, carries out injecting and spreading on described N-type light dope epitaxial loayer top, form a P type tagma and the 2nd P type tagma;
Etch, the first groove and the second groove is formed in described N-type light dope epitaxial loayer, wherein, first, second groove described runs through first, second P type tagma described respectively and extends toward described N-type light dope epitaxial loayer bottom direction, and does not run through described N-type light dope epitaxial loayer;
Ion implantation is carried out to described first groove and the second channel bottom, forms a P island structure respectively at first, second channel bottom described;
In described first groove and the second groove, fill p type semiconductor layer, form a P post and the 2nd P post;
Grid structure is formed in described N-type light dope epi-layer surface; Described grid structure is between a described P post and the 2nd P post, and described grid structure two ends contact with a described P type tagma and the 2nd P type tagma respectively.
9. the manufacture method of high pressure super node MOSFET structure according to claim 8, is characterized in that: the thickness of described P island structure is 1 ~ 3 micron.
10. the manufacture method of high pressure super node MOSFET structure according to claim 8, is characterized in that: after described N-type light dope epi-layer surface forms grid structure, further comprising the steps of:
In a described P type tagma and the 2nd P type tagma, carry out source region injection, form N-type heavy doping source region;
The insulating barrier of described grid structure is covered in described N-type light dope epi-layer surface growth, perform hole of going forward side by side etching and hole are injected, obtain contact hole and be positioned at the P type heavy doping contact zone bottom contact hole, described P type heavy doping contact zone is formed in a described P type tagma and the 2nd P type tagma and adjacent described N-type heavy doping source region;
Form source metal at described surface of insulating layer, described source metal is filled into described contact hole and contacts with described N-type heavy doping source region and P type heavy doping contact zone; By described insulator separation between described source metal and described grid structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510203291.9A CN104779297A (en) | 2015-04-24 | 2015-04-24 | High-voltage super junction MOSFET structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510203291.9A CN104779297A (en) | 2015-04-24 | 2015-04-24 | High-voltage super junction MOSFET structure and manufacturing method thereof |
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| CN107342226A (en) * | 2017-07-19 | 2017-11-10 | 无锡新洁能股份有限公司 | The manufacture method of extra small unit size longitudinal direction super-junction semiconductor device |
| CN111370305A (en) * | 2020-04-30 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Deep groove type super junction device and manufacturing method thereof |
| CN111883422A (en) * | 2020-07-16 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of super junction device |
| CN116404034A (en) * | 2023-06-07 | 2023-07-07 | 西安电子科技大学 | Silicon carbide power device matched with floating junction to introduce sheet-shaped P channel |
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| US20090101974A1 (en) * | 2007-10-22 | 2009-04-23 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN102208447B (en) * | 2011-05-20 | 2013-04-24 | 无锡新洁能股份有限公司 | Semiconductor device with super-junction structure and manufacturing method thereof |
| CN204596793U (en) * | 2015-04-24 | 2015-08-26 | 无锡同方微电子有限公司 | A kind of high pressure super node MOSFET structure |
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| US20090101974A1 (en) * | 2007-10-22 | 2009-04-23 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN102208447B (en) * | 2011-05-20 | 2013-04-24 | 无锡新洁能股份有限公司 | Semiconductor device with super-junction structure and manufacturing method thereof |
| CN204596793U (en) * | 2015-04-24 | 2015-08-26 | 无锡同方微电子有限公司 | A kind of high pressure super node MOSFET structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107342226A (en) * | 2017-07-19 | 2017-11-10 | 无锡新洁能股份有限公司 | The manufacture method of extra small unit size longitudinal direction super-junction semiconductor device |
| CN107342226B (en) * | 2017-07-19 | 2020-07-31 | 无锡新洁能股份有限公司 | Manufacturing method of ultra-small unit size longitudinal super junction semiconductor device |
| CN111370305A (en) * | 2020-04-30 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Deep groove type super junction device and manufacturing method thereof |
| CN111883422A (en) * | 2020-07-16 | 2020-11-03 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of super junction device |
| CN116404034A (en) * | 2023-06-07 | 2023-07-07 | 西安电子科技大学 | Silicon carbide power device matched with floating junction to introduce sheet-shaped P channel |
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