CN104103522A - Method for manufacturing high withstand voltage super junction terminal structure - Google Patents
Method for manufacturing high withstand voltage super junction terminal structure Download PDFInfo
- Publication number
- CN104103522A CN104103522A CN201410333424.XA CN201410333424A CN104103522A CN 104103522 A CN104103522 A CN 104103522A CN 201410333424 A CN201410333424 A CN 201410333424A CN 104103522 A CN104103522 A CN 104103522A
- Authority
- CN
- China
- Prior art keywords
- termination environment
- withstand voltage
- cellular region
- termination
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 230000001413 cellular effect Effects 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 238000002360 preparation method Methods 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 17
- 238000000407 epitaxy Methods 0.000 abstract 1
- 238000005429 filling process Methods 0.000 abstract 1
- 230000000903 blocking effect Effects 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to the technical field of semiconductor process manufacture and specifically relates to a method for manufacturing a high withstand voltage super junction terminal structure. The method includes, by means of two times of etch processes and once epitaxy filling process, forming in a terminal area a semiconductor column, deeper than a cellular area, in a second conductive type, and introducing a field limiting ring structure to the top end of the semiconductor column in the second conductive type in the terminal area. The method for manufacturing the high withstand voltage super junction terminal structure has the advantages of being capable of increasing breakdown voltage of the terminal area so that avalanche breakdown occurs in the cellular area; since the cellular area has higher current processing capability, reliability of devices are improved; the method is particularly applicable to manufacturing the high withstand voltage super junction terminal structure.
Description
Technical field
The invention belongs to semiconductor technology manufacturing technology field, relate to specifically a kind of preparation method of high withstand voltage superjunction termination structure.
Background technology
At present, the application of power MOSFET device is more and more wider, is widely used in DC-DC converter, DC-AC converter, the fields such as power amplifier.Vertical double-diffused MOS field-effect transistor (VDMOS), there is the advantages such as switching speed is fast, loss is little, input impedance is high, driving power is little, frequency characteristic is good, mutual conductance highly linear, become the power device being most widely used at present.
For VDMOS, its puncture voltage BV is mainly determined by drift region.Drift region is thicker, and doping content is lower, and puncture voltage is higher, but, when puncture voltage improves, its conducting resistance (on-resistance) R
onalso increase (R thereupon
on∝ BV
2.5), cause the sharply increase of power consumption.This " silicon limit (silicon limit) " broken in the appearance of super knot (Superjunction) VDMOS device, introduce the super-junction structure of the staggered N-type of heavy doping and P type semiconductor by the light dope drift region at traditional VDMOS, when device is operated in blocking-up situation lower time, according to charge balance theory, HeNXing district, p type island region exhausts completely, drift region is just equivalent to an intrinsic layer, and puncture voltage is just only relevant and irrelevant with doping content with the thickness of drift region.Under identical puncture voltage, can increase the doping content of hyperconjugation VDMOS drift layer, reduce its conducting resistance, improved conducting resistance and withstand voltage between restricting relation (R
on∝ BV
1.3), therefore hyperconjugation VDMOS is obtained application in various high energy efficiency occasions rapidly, and market prospects are very extensive.
Terminal Design has great importance for the withstand voltage and reliability of super knot.Conventionally need to have than the withstand voltage higher terminal structure of cellular, breakdown point will occur in cellular region like this, because Area Ratio termination environment, cellular region is much larger, can bear the electric current larger than termination environment, be conducive to improve the reliability of device.As shown in Figure 1, termination environment adopts the super-junction structure identical with cellular region the same to most widely used super knot power device terminal at present, and main design principle is still the withstand voltage principle of super knot.But, due to the limitation of technology controlling and process, usually can make the withstand voltage lower than cellular region of termination environment, avalanche breakdown is occurred in termination environment, reduce the reliability of device.
Summary of the invention
Object of the present invention, is exactly for the problems referred to above, proposes a kind of preparation method of high withstand voltage superjunction termination structure.
Technical scheme of the present invention is that a kind of manufacture method of non-homogeneous super-junction structure, is characterized in that, comprises the following steps:
A preparation method for high withstand voltage superjunction termination structure, is characterized in that, comprises the following steps:
The first step: generate N-epitaxial loayer 2 in N+ substrate 1 upper surface extension;
Second step: adopt photoetching and body silicon etching process, generate multiple shallow slots on the N-of termination environment part epitaxial loayer 2 upper stratas;
The 3rd step: adopt photoetching and body silicon etching process, carry out etching in cellular region and termination environment simultaneously, generate multiple deep trouths on N-epitaxial loayer 2 upper stratas of cellular region and termination environment part respectively, the deep trouth of termination environment part is arranged in the shallow slot of termination environment part corresponding one by one with shallow slot, and the groove total depth that is therefore positioned at termination environment part will be greater than the groove total depth that is positioned at cellular region part;
The 4th step: epitaxial growth P type silicon is filled the grooved region in cellular region and termination environment, forms P Xing Zhu district respectively in cellular region He in termination environment, in termination environment, the shallow slot of P type column top forms field limiting ring 8;
The 5th step: complete other common process steps of device.
Beneficial effect of the present invention is, by twice etching and an extension fill process, form the second conductive type semiconductor post darker than cellular region in termination environment, and the second conductive type semiconductor capital end has been introduced the second conduction type field limiting ring structure in termination environment, improve the puncture voltage of termination environment, make avalanche breakdown occur in cellular region, because cellular region has stronger current handling capability, the reliability of device is improved.
Brief description of the drawings
Fig. 1 is traditional hyperconjugation VDMOS structural representation;
Fig. 2 is that embodiment 1 is through the device architecture figure after processing step 1;
Fig. 3 is that embodiment 1 is through the device architecture figure after processing step 2;
Fig. 4 is that embodiment 1 is through the device architecture figure after processing step 3;
Fig. 5 is that embodiment 1 entered the device architecture figure after processing step 4;
Fig. 6 is that embodiment 1 is through the device architecture figure after processing step 5;
Fig. 7 is that the avalanche current of traditional hyperconjugation VDMOS structure in the time there is avalanche breakdown distributes and breakdown point schematic diagram;
Fig. 8 is that the avalanche current of the hyperconjugation VDMOS structure that obtains of the preparation method of embodiment 1 in the time there is avalanche breakdown distributes and breakdown point schematic diagram;
The avalanche current of the hyperconjugation VDMOS structure of the beneficial effect in Tu9Shi verification terminal district P type field limiting ring district in the time there is avalanche breakdown distributes and breakdown point schematic diagram;
Figure 10 is the I-V characteristic curve of traditional hyperconjugation VDMOS arrangement works under blocking mode in Fig. 7, punctures withstand voltage about 1169V;
Figure 11 is the I-V characteristic curve of the hyperconjugation VDMOS arrangement works that obtains of the preparation method that proposes by embodiment 1 in Fig. 8 under blocking mode, punctures withstand voltage about 1184V;
Figure 12 is the I-V characteristic curve of the hyperconjugation VDMOS arrangement works that obtains of the preparation method that proposes by embodiment 1 in Fig. 8 under blocking mode, punctures withstand voltage about 1182V;
Figure 13 is embodiment 2 structural representations;
Figure 14 is at embodiment 3 structural representations.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described
Embodiment 1:
This example comprises the following steps:
Step 1: extension N-epitaxial loayer 2 on N+ substrate 1, as shown in Figure 2;
Step 2: utilize photoetching and body silicon etching process, form on N-epitaxial loayer 2 upper stratas of termination environment II part the shallow slot 8 that multiple degree of depth are h, as shown in Figure 3;
Step 3: utilize photoetching and body silicon etching process, carry out deep etching in cellular region I and termination environment II simultaneously, generate multiple deep trouths on N-epitaxial loayer 2 upper stratas of cellular region and termination environment part respectively, the deep trouth of termination environment should be corresponding one by one with shallow slot 8, the structure forming as shown in Figure 4, the deep trouth 3 of termination environment is by larger than the degree of depth of the deep trouth of cellular region 4, and its total depth is poor is the degree of depth h of shallow slot;
Step 4: epitaxial growth P type Si fills the grooved region of cellular and terminal, then after, chemical mechanical polish process is carried out in N-epitaxial loayer 2 surfaces, remove the second unnecessary conductive type semiconductor, the structure generating as shown in Figure 5, comprise terminal P Xing Zhu district 3, cellular P Xing Zhu district 4, field limiting ring 8, field limiting ring 8 is positioned at 3 tops, terminal P Xing Zhu district;
Step 5: other common process steps that complete hyperconjugation VDMOS device, generate device architecture as shown in Figure 6, comprise cellular region, termination environment, substrate 1, drift region 2, P Xing Zhu district, termination environment 3, P Xing Zhu district, cellular region 4, cut-off ring 5 P type tagmas, cellular region 6, source metal 7, P type tagma, termination environment 8, drain metal 9.
This routine operation principle is:
Because the withstand voltage size of super-junction structure and the doping content of electric charge compensating region are irrelevant, and it is closely related with the degree of depth of super-junction structure, the P type semiconductor doped column 3 of termination environment II is darker than P type semiconductor doped column 4 degree of depth of cellular region I, thereby the voltage endurance capability of termination environment II is higher than cellular region I.On the other hand, introduce field limiting ring 8 at P type semiconductor doped column 3 tops of termination environment II, can further improve terminal withstand voltage.In the time that device avalanche breakdown occurs, breakdown point is prone in cellular region I, because cellular region I has more outstanding current handling capability, thereby has improved the reliability of device.
In order to verify the beneficial effect of the present embodiment, utilize emulation tool Tsuprem4 to generate superjunction termination structure, as shown in Figure 8, and its electrology characteristic is simulated with emulation tool Medici, in order to contrast, also simulated a traditional hyperconjugation VDMOS terminal structure with Tsuprem4 and Medici, as shown in Figure 7.
Fig. 7 is that the avalanche current of traditional hyperconjugation VDMOS structure in the time of avalanche breakdown distributes and depletion region distribution map.In this model configuration, device cellular region I comprises three P type posts, and termination environment II comprises 11 P type posts.The concentration of the N-type drift region of cellular region I, termination environment II is 1*10
15cm
-3, the concentration of P type post is 2.4*10
15cm
-3, width is 5um, and intercolumniation is 12um, and the post degree of depth is 60um.Figure 10 is the I-V characteristic curve of hyperconjugation VDMOS arrangement works under blocking mode in Fig. 7, and device withstand voltage is about 1169V.
Fig. 8 is that the avalanche current of this routine hyperconjugation VDMOS structure in the time of avalanche breakdown distributes and depletion region distribution map.In this structure, the width in the P type field limiting ring district 8 of termination environment II is 9um, be positioned on P type post 3, and left and right respectively exceeds P post 2um, and concentration is consistent with P post, and other structure and parameters are all the same with the traditional hyperconjugation VDMOS structure in Fig. 7.Figure 11 is the I-V characteristic curve of hyperconjugation VDMOS arrangement works under blocking mode in Fig. 8, and device withstand voltage is about 1184V.
Secondly, in order to verify the beneficial effect in the P type field limiting ring district 8 of termination environment II in the hyperconjugation VDMOS structure that this example proposes, analog simulation as avalanche current distribution and the depletion region distribution map of the hyperconjugation VDMOS terminal structure of Fig. 9 when the avalanche breakdown.In Fig. 9, termination environment II does not have P type field limiting ring district, and all the other parameters are the same with the hyperconjugation VDMOS structure in Fig. 8.Figure 12 is the I-V characteristic curve of hyperconjugation VDMOS arrangement works under blocking mode in Fig. 8, and device withstand voltage is about 1182V.
By Fig. 7, Fig. 8 and Fig. 9 contrast the breakdown point of the hyperconjugation VDMOS structure that can find the proposition of this example in cellular region I, because cellular region I has more outstanding current handling capability with respect to termination environment II, therefore the reliability of device is higher.The voltage endurance capability that Figure 10 and Figure 11 is contrasted to a kind of novel hyperconjugation VDMOS structure of finding that the present invention proposes rises to some extent.
Embodiment 2:
As shown in figure 13, this example is from the different of embodiment 1, and the second conductive type semiconductor post 8 in the II of termination environment is connected state.This routine preparation method only need to change the mask plate figure of body silicon etching in step 2, and all the other steps are identical with embodiment 1.
Embodiment 3:
As shown in figure 14, this example is from the different of embodiment 1, and the second conductive type semiconductor post 8 in the II of termination environment is part connected state.This routine preparation method only need to change the mask plate figure of body silicon etching in step 2, and all the other steps are identical with embodiment 1.
The present invention is equally applicable to the preparation of P raceway groove hyperconjugation VDMOS device, super knot DIODE or super knot IGBT.
Claims (1)
1. a preparation method for high withstand voltage superjunction termination structure, is characterized in that, comprises the following steps:
The first step: generate the low-doped semiconductor epitaxial layers of the first conduction type (2) in the first conduction type high doping semiconductor substrate (1) upper surface extension;
Second step: adopt photoetching and body silicon etching process, generate multiple shallow slots on the low-doped semiconductor epitaxial layers of the first conduction type (2) upper strata of termination environment part;
The 3rd step: adopt photoetching and body silicon etching process, carry out etching in cellular region and termination environment simultaneously, generate multiple deep trouths on the low-doped semiconductor epitaxial layers of the first conduction type (2) upper strata of cellular region and termination environment part respectively, the deep trouth of termination environment part is arranged in the shallow slot of termination environment part corresponding one by one with shallow slot, and the groove total depth that is positioned at termination environment part is greater than the groove total depth that is positioned at cellular region part;
The 4th step: epitaxial growth the second conductive type semiconductor is filled the grooved region in cellular region and termination environment, in cellular region He in termination environment, form the second conductive type semiconductor post district respectively, in termination environment, the shallow slot of the second conductive type semiconductor column top forms field limiting ring (8).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410333424.XA CN104103522B (en) | 2014-07-14 | 2014-07-14 | A kind of preparation method of high pressure super-junction terminal structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410333424.XA CN104103522B (en) | 2014-07-14 | 2014-07-14 | A kind of preparation method of high pressure super-junction terminal structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104103522A true CN104103522A (en) | 2014-10-15 |
| CN104103522B CN104103522B (en) | 2016-08-24 |
Family
ID=51671555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410333424.XA Expired - Fee Related CN104103522B (en) | 2014-07-14 | 2014-07-14 | A kind of preparation method of high pressure super-junction terminal structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104103522B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104779298A (en) * | 2015-04-24 | 2015-07-15 | 无锡同方微电子有限公司 | Super-junction MOSFET terminal structure and manufacturing method thereof |
| CN104952910A (en) * | 2015-05-19 | 2015-09-30 | 上海先进半导体制造股份有限公司 | Terminal structure of super-junction semiconductor device and manufacturing method thereof |
| CN111146271A (en) * | 2019-12-20 | 2020-05-12 | 北京时代民芯科技有限公司 | Super-junction MOSFET structure with terminal structure and preparation method |
| CN111627984A (en) * | 2020-06-04 | 2020-09-04 | 中芯集成电路制造(绍兴)有限公司 | Super junction device and manufacturing method thereof |
| CN117153737A (en) * | 2023-10-27 | 2023-12-01 | 深圳安森德半导体有限公司 | Preparation method of super junction MOS terminal resistant to avalanche breakdown |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1744329A (en) * | 2004-08-31 | 2006-03-08 | 株式会社电装 | Semiconductor device having super junction structure and method for manufacturing the same |
| JP2006114866A (en) * | 2004-09-15 | 2006-04-27 | Fuji Electric Holdings Co Ltd | Manufacturing method for semiconductor element |
| US20070148931A1 (en) * | 2005-12-26 | 2007-06-28 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| JP2009004547A (en) * | 2007-06-21 | 2009-01-08 | Toshiba Corp | Semiconductor device |
| CN102655172A (en) * | 2011-03-04 | 2012-09-05 | 特瑞诺科技股份有限公司 | Charge balance power device and manufacturing method thereof |
-
2014
- 2014-07-14 CN CN201410333424.XA patent/CN104103522B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1744329A (en) * | 2004-08-31 | 2006-03-08 | 株式会社电装 | Semiconductor device having super junction structure and method for manufacturing the same |
| JP2006114866A (en) * | 2004-09-15 | 2006-04-27 | Fuji Electric Holdings Co Ltd | Manufacturing method for semiconductor element |
| US20070148931A1 (en) * | 2005-12-26 | 2007-06-28 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
| JP2009004547A (en) * | 2007-06-21 | 2009-01-08 | Toshiba Corp | Semiconductor device |
| CN102655172A (en) * | 2011-03-04 | 2012-09-05 | 特瑞诺科技股份有限公司 | Charge balance power device and manufacturing method thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104779298A (en) * | 2015-04-24 | 2015-07-15 | 无锡同方微电子有限公司 | Super-junction MOSFET terminal structure and manufacturing method thereof |
| CN104952910A (en) * | 2015-05-19 | 2015-09-30 | 上海先进半导体制造股份有限公司 | Terminal structure of super-junction semiconductor device and manufacturing method thereof |
| CN111146271A (en) * | 2019-12-20 | 2020-05-12 | 北京时代民芯科技有限公司 | Super-junction MOSFET structure with terminal structure and preparation method |
| CN111627984A (en) * | 2020-06-04 | 2020-09-04 | 中芯集成电路制造(绍兴)有限公司 | Super junction device and manufacturing method thereof |
| CN117153737A (en) * | 2023-10-27 | 2023-12-01 | 深圳安森德半导体有限公司 | Preparation method of super junction MOS terminal resistant to avalanche breakdown |
| CN117153737B (en) * | 2023-10-27 | 2024-02-13 | 深圳安森德半导体有限公司 | Preparation method of super junction MOS terminal resistant to avalanche breakdown |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104103522B (en) | 2016-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104183627B (en) | Super junction power device terminal structure | |
| CN107316899B (en) | Semi-super junction device and manufacturing method thereof | |
| CN101969073B (en) | Rapid superjunction longitudinal double-diffusion metal oxide semiconductor transistor | |
| CN103579353B (en) | Half hyperconjugation VDMOS of buried regions assisted by a kind of P of having type | |
| CN103746002B (en) | A kind of step groove-field limiting ring composite terminal structure | |
| CN104241376A (en) | Super junction structure, preparation method of super junction structure and semiconductor device | |
| CN104103522B (en) | A kind of preparation method of high pressure super-junction terminal structure | |
| CN103219386B (en) | A kind of lateral power with high K insulation layer | |
| CN103579351A (en) | LDMOS (laterally diffused metal oxide semiconductor) device provided with super-junction buried layer | |
| CN103199104B (en) | A kind of crystal circle structure and apply its power device | |
| CN104934465A (en) | Super junction composition preparation method | |
| CN102231390A (en) | Vertical double-diffused metal oxide semiconductor power device with super junction structure | |
| CN107221561A (en) | A kind of lamination Electric Field Modulated high-voltage MOSFET structure and preparation method thereof | |
| CN103337498A (en) | BCD semiconductor device and manufacturing method thereof | |
| CN102097480A (en) | N-type super-junction transverse double-diffusion metal oxide semiconductor tube | |
| CN103268860A (en) | Manufacturing method of IGBT (insulated gate bipolar transistor) device integrated with diode | |
| CN106783620A (en) | Hyperconjugation VDMOS device structure of anti-EMI filter and preparation method thereof | |
| CN203288599U (en) | VDMOS device of novel structure | |
| CN104779296A (en) | Asymmetric super junction MOSFET structure and manufacturing method thereof | |
| CN108091567B (en) | Semi-super junction FS IEGT structure and manufacturing method thereof | |
| CN108054194B (en) | Semiconductor device voltage-withstanding layer with three-dimensional lateral variable doping | |
| CN102637733A (en) | Super junction insulated-gate bipolar transistor | |
| CN103560148B (en) | A kind of junction termination structures of superjunction devices and manufacture method thereof | |
| CN201749852U (en) | Fast ultra-junction longitudinal double diffusion metal oxide semiconductor tube | |
| CN106328688A (en) | Structure and manufacturing method of terminal voltage-division region for super-junction device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160824 Termination date: 20200714 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |