CN111627984A - Super junction device and manufacturing method thereof - Google Patents
Super junction device and manufacturing method thereof Download PDFInfo
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
Abstract
The invention provides a super-junction device and a manufacturing method thereof, wherein the super-junction device is provided with a super-junction terminal structure in a first conductive type epitaxial layer of a terminal area, the super-junction terminal structure comprises a plurality of first conductive type columns and second conductive type columns which are arranged alternately, a main junction and a plurality of second conductive type areas, and at least one second conductive type column is arranged between at least part of adjacent second conductive type areas at intervals, so that on the basis of ensuring the pressure resistance, the forming process window of the second conductive type areas can be enlarged, and the process difficulty is reduced.
Description
Technical Field
The invention relates to the technical field of super junction devices, in particular to a super junction device and a manufacturing method thereof.
Background
In order to more effectively improve the breakdown voltage, in the prior art, on the basis of the structure of a Vertical Double-diffused metal oxide semiconductor field effect transistor (VDMOS, Vertical Double-diffused MOSFET) device, a super junction device called CoolMOS is proposed, in which a super junction structure (SuperJunction) is formed in a core region and a terminal region located at the periphery of the core region, and the super junction structure mainly includes a voltage-withstanding layer formed by alternately arranged P-type columns (P-pilar) and N-type columns (N-pilar), and N + regions and P + regions formed above and below the voltage-withstanding layer.
In the conventional process, a super junction structure in a core region and a terminal region of a CoolMOS super junction device is manufactured through multiple times of epitaxy and ion implantation, and the specific process generally comprises the following steps: firstly, depositing an epitaxial layer, carrying out related P-type and N-type ion implantation on the epitaxial layer, then, repeating epitaxial layer deposition and ion implantation for multiple times, annealing, and forming P-type columns and N-type columns which are alternately arranged in a core region and a peripheral terminal region; then, surface VDMOS fabrication is performed, including: a Field Oxide (FOX) layer, a gate oxide layer (GOX), a polysilicon gate, N + and P + regions (N plus) and (P plus), an interlayer dielectric layer (ILD), source and drain contacts, source and drain metal electrodes, and the like.
The CoolMOS adopts a 3D-RESURF (3-Dimensions Reduced Surface Field) principle to mutually deplete the P-type columns and the N-type columns which are alternately arranged before breakdown so as to obtain higher withstand voltage and reduce the magnitude of on-resistance during forward conduction. The ion implantation process used to form the P-type and N-type columns is very sensitive and the range of implant concentration (which may also be referred to as the ion implantation process window) is small, thus requiring tight control of the doping concentration near the surface of the device.
In addition, when the field oxide layer is formed, the segregation coefficients of silicon dioxide in the field oxide layer and silicon in the epitaxial layer are different, so that the phenomenon of boron absorption and phosphorus removal can be caused, the distribution of surface doping impurities can be changed, and the voltage resistance of the super junction device is directly influenced. Moreover, due to the influence of many factors such as the atmosphere, furnace tube, temperature, position, etc. of the process for forming the field oxide layer, the phenomenon of boron absorption and phosphorus removal is difficult to control in the actual process, and the implantation concentration range of the ion implantation process for forming the P-type and N-type columns is further reduced.
Disclosure of Invention
The invention aims to provide a super junction device and a manufacturing method thereof, which can increase a forming process window of a second conductive type area on the basis of ensuring the pressure resistance so as to reduce the process difficulty.
In order to solve the above technical problem, the present invention provides a super junction device, including a first conductive type epitaxial layer, where the first conductive type epitaxial layer has a core region and a terminal region located at a periphery of the core region, where the super junction device is provided with a super junction terminal structure in the first conductive type epitaxial layer of the terminal region, and the super junction terminal structure includes:
a plurality of first conductive type pillars and second conductive type pillars arranged alternately;
a main junction proximate the core region and formed on a top end of at least one first and/or second conductivity type pillar;
and the second conductive type regions are positioned at the periphery of the main junction and are respectively formed on the top ends of the corresponding second conductive type columns, and at least one second conductive type column is arranged between at least part of adjacent second conductive type regions.
Optionally, the first conductivity type epitaxial layer is a stacked structure of multiple epitaxial layers, the main junction and the second conductivity type region are located in a topmost epitaxial layer of the first conductivity type epitaxial layer, and both the conductivity type and the depth are the same.
Optionally, a ratio of a line width of the second conductive type region to a line width of the second conductive type column directly below the second conductive type region is 0.8 to 1.2, and/or a ratio of a doping concentration of the second conductive type region to a doping concentration of the second conductive type column is 1 to 50.
Optionally, the second conductivity type regions are uniformly distributed, or the distribution density of the second conductivity type regions gradually decreases along a direction from the main junction to the boundary of the termination region.
Optionally, the second conductivity-type pillars are uniformly distributed in the termination region, but the number of the second conductivity-type pillars in the interval between adjacent second conductivity-type regions is gradually increased, so that the distribution density of the second conductivity-type regions is gradually decreased along the direction from the main junction to the boundary of the termination region; or, the number of the second conductive type pillars of the interval between the adjacent second conductive type regions is the same, but the distribution density of the second conductive type pillars in the termination region is gradually reduced along the direction from the main junction to the boundary of the termination region, so that the distribution density of the second conductive type regions is gradually reduced along the direction from the main junction to the boundary of the termination region.
Optionally, a super junction structure is formed in the first conductivity type epitaxial layer of the core region, and the super junction structure includes a plurality of first conductivity type pillars and second conductivity type pillars alternately arranged.
The invention also provides a manufacturing method of the super junction device, which comprises the following steps:
providing a substrate having a core region and a termination region;
forming a first conductive type epitaxial layer on the substrate, forming a plurality of first conductive type pillars and second conductive type pillars which are alternately arranged in the first conductive type epitaxial layer of the terminal region, and forming a main junction and a plurality of second conductive type regions, wherein the main junction is close to the core region and is formed on the top end of at least one first conductive type pillar and/or second conductive type pillar, each second conductive type region is located at the periphery of the main junction and is respectively formed on the top end of the corresponding second conductive type pillar, and at least one second conductive type pillar is arranged between at least part of adjacent second conductive type regions.
Optionally, the step of forming a first conductive type epitaxial layer having a plurality of second conductive type pillars and the second conductive type regions on the substrate includes:
(a) growing a bottom epitaxial layer on the substrate;
(b) carrying out first ion implantation on a partial region of the bottom epitaxial layer by adopting second conductive type ions;
(c) circularly executing the steps (a) to (b) until the number of circulation reaches the required number;
(d) growing a topmost epitaxial layer, and performing second ion implantation on a partial region of the topmost epitaxial layer by adopting second conductive type ions, wherein the region subjected to the second ion implantation is aligned to the corresponding region subjected to the first ion implantation;
(e) annealing, so that the diffusion regions corresponding to the first ion implantation are connected in two bottom epitaxial layers which are adjacent up and down to form second conductive type columns and first conductive type columns which are alternately arranged, and the diffusion regions corresponding to the second ion implantation are connected with the top ends of the corresponding second conductive type columns to form second conductive type regions;
or, the step of forming the first conductive type epitaxial layer having the second conductive type pillars and the second conductive type regions on the substrate includes:
(a) growing a bottom epitaxial layer having a first conductivity type on the substrate;
(b) etching the bottom epitaxial layer with partial thickness to form a plurality of deep grooves;
(c) filling a second conductive type epitaxial layer in the deep groove to form second conductive type columns and first conductive type columns which are alternately arranged in the bottom epitaxial layer;
(d) growing a topmost epitaxial layer on the bottom epitaxial layer, wherein the topmost epitaxial layer and the bottom epitaxial layer form the first conduction type epitaxial layer;
(e) and forming a second conductive type region in the topmost epitaxial layer.
Optionally, the main junction and the second conductive type region have the same conductive type and are formed by the same process.
Optionally, a ratio of a line width of the second conductive type region to a line width of the second conductive type pillar directly below the second conductive type region is 0.8 to 1.2, and/or a ratio of a doping concentration of the second conductive type region to a doping concentration of the second conductive type pillar is 1 to 50.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. in the technical scheme of the invention, at least one second conductive type column is arranged between at least part of adjacent second conductive type regions, so that the forming process window of the second conductive type regions can be enlarged, and the process difficulty is reduced. For example, when the second conductive type region is formed by a process of implanting ions of the second conductive type into the topmost epitaxial layer, the optional concentration range of the ion implantation can be increased, thereby reducing the process difficulty. For example, when the second conductive type region is formed by etching the top epitaxial layer to form the shallow trench and filling the shallow trench with the corresponding material, at least one second conductive type pillar may be spaced between adjacent shallow trenches, so that an etching window of the shallow trench is relatively increased, and the process difficulty is reduced.
2. In the technical scheme of the invention, the line width of the second conductive type region is set to be 0.8-1.2 times of the line width of the second conductive type column right below the second conductive type region, so that the premature concentration of an electric field on a main junction can be effectively prevented, the withstand voltage of the device is stabilized, the problems that more second conductive type regions are required to be arranged due to the over-small line width of the second conductive type region, the concentration of a surface electric field is easy to concentrate and the withstand voltage is ensured can be solved, and the problems that the boron absorption and phosphorus removal phenomena in the process of forming a field oxide layer cause the change of the concentration of surface impurities to be increased and further the influence on the withstand voltage performance of the device is increased due to the over-large line width of the second conductive type region.
3. In the technical scheme of the invention, the line width of the second conductive type region is set to be 0.8-1.2 times of the line width of the second conductive type column right below the second conductive type region, so that the doping concentration of the second conductive type region can be changed in a larger range without influencing the withstand voltage of the terminal region, and therefore, the influence of the surface doping concentration change caused by the phenomenon of boron absorption and phosphorus removal in the process of forming the field oxide layer on the withstand voltage of the device can be greatly reduced, namely, the ion doping concentration range of the second conductive type region is enlarged relative to the existing ion doping concentration range, namely, the process window of forming the super junction terminal structure is enlarged, and the process difficulty of forming the second conductive type region is reduced.
Drawings
Fig. 1 to 4 are schematic cross-sectional structures of a super junction device according to an embodiment of the present invention.
Fig. 5 is a flowchart of a method of manufacturing a superjunction device according to an embodiment of the present invention.
Fig. 6 to 12 are schematic device cross-sectional structures in the method of manufacturing the superjunction device shown in fig. 5.
Fig. 13 is a flowchart of a method of manufacturing a superjunction device according to another embodiment of the present invention.
Fig. 14 to 18 are schematic device cross-sectional structures in the method of manufacturing a super junction device shown in fig. 13.
Detailed Description
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. As used herein, "and/or" means either or both.
Referring to fig. 1, an embodiment of the present invention provides a super junction device, where the super junction device includes a first conductivity type epitaxial layer 10, the first conductivity type epitaxial layer 10 has a core region (not shown) and a termination region located at a periphery of the core region, and the super junction device is provided with a super junction termination structure in the first conductivity type epitaxial layer 10 of the termination region. The super junction terminal structure includes: a plurality of first and second conductive type pillars 11 arranged alternately, a main junction 13, a plurality of second conductive type regions 12, a field oxide layer 14, a gate oxide layer 15, a gate layer 16, an interlayer dielectric layer 17, and a metal interconnection structure 18. The first conductive type pillar is a first conductive type epitaxial layer 10 sandwiched between two adjacent second conductive type pillars 11.
The first conductive epitaxial layer 10 may be a semiconductor layer doped with N-type dopant or P-type dopant formed on a silicon substrate, a silicon-on-insulator substrate, a silicon germanium substrate, or the like (not shown) known to those skilled in the art, and the first conductive epitaxial layer 10 may have the same conductivity type as the substrate, but a doping concentration lower or higher than the substrate, or may have a conductivity type different from that of the substrate. The first conductive type epitaxial layer 10 may be a structure of a multi-layered epitaxial layer stack.
The first conductive type epitaxial layer 10 has a core region for forming a core device and a termination region surrounding the core region and forming peripheral circuits such as an input/output circuit. The specific structural form of the core element in the core region may be designed as required, and optionally, the core element in the core region also adopts a super junction structure, that is, the super junction structure in the core region also has a plurality of first conductive type columns and second conductive type columns 11 arranged alternately, and the super junction structure in the core region is formed together with the super junction terminal structure in the terminal region. Alternatively, the distribution density of the second conductive type pillars 11 in the core region is different from the distribution density of the second conductive type pillars 11 in the termination region, and the line width of the second conductive type pillars 11 in the core region is different from the line width of the second conductive type pillars 11 in the termination region. As an example, the distribution density of the second conductive type pillars 11 in the core region is greater than the distribution density of the second conductive type pillars 11 in the terminal region, and the line width of the second conductive type pillars 11 in the core region is smaller than the line width of the second conductive type pillars 11 in the terminal region.
Note that the shape of the second conductive type pillar 11 in the core region in plan view may be the same as or different from the shape of the second conductive type pillar 11 in the termination region in plan view. For example, the first conductive type column and the second conductive type column 11 in the core region are arranged in parallel and in a stripe shape, and the first conductive type column and the second conductive type column 11 in the termination region are in a ring shape and surround the periphery of the core region; for another example, the first and second conductive type pillars 11 in the core and termination regions are both arranged in concentric rings.
In the present embodiment, the main junction 13 is disposed next to the core region and is formed on the top end of at least one first conductive type pillar and/or second conductive type pillar 11, for example, the main junction 13 is disposed on the top ends of four second conductive type pillars 11 next to the core region and is in contact with the top ends of the four second conductive type pillars 11 and with the top ends of the first conductive type pillars sandwiched on both sides of the four second conductive type pillars 11.
In this embodiment, each second conductive type region 12 is located at the periphery of the main junction 13 and is formed on the top end of the corresponding second conductive type pillar 11, and the second conductive type region 12 is in contact with the top end of the second conductive type pillar 11 directly below the second conductive type region 12. The number of second conductivity-type regions 12 may be set according to a specific withstand voltage class, and is generally greater than 2 and less than the number of second conductivity-type pillars 11 in the termination region. In order to ensure a higher withstand voltage, the ion concentration of each of the second conductivity type regions 12 may be lower than that of the main junction 13, and the line width may be smaller than that of the main junction 13. And in order to increase the process window of the second conductive type region 12, in this embodiment, the remaining second conductive type regions 12 are spaced by at least one second conductive type pillar 11 except that a plurality of second conductive type regions 12 next to the main junction 13 are continuously distributed on the adjacent second conductive type pillars 11.
In addition, the ratio of the line width W1 of the second conductive type region 12 to the line width W2 of the second conductive type pillar 11 directly below the second conductive type region is 0.8-1.2, specifically, for example, 0.8, 0.9, 1 or 1.1 or 1.2, which not only can effectively prevent the electric field on the main junction from being concentrated too early and stabilize the withstand voltage of the device, but also can solve the problem that the surface electric field is easy to be concentrated and the withstand voltage is guaranteed only by providing more second conductive type regions 12 due to too small line width of the second conductive type region 12, and solve the problem that the boron absorption and phosphorus removal phenomenon in the process of forming the field oxide layer due to too large line width of the second conductive type region 12 causes the change of the surface impurity concentration to be increased and the influence on the withstand voltage performance of the device to be increased. More importantly, the doping concentration of the second conductive type region 12 can be changed in a large range without affecting the withstand voltage of the terminal region, so that the influence of the surface doping concentration change caused by the phenomenon of boron absorption and phosphorus removal in the process of forming the field oxide layer on the withstand voltage of the device can be greatly reduced, that is, the ion doping concentration range of the second conductive type region 12 is enlarged compared with the existing ion doping concentration range of the second conductive type region 12, namely, the process window of forming the super junction terminal structure is enlarged, and the process difficulty of forming the second conductive type region 12 is reduced.
Optionally, a ratio of the doping concentration of the second conductive type region 12 to the doping concentration of the second conductive type pillar 11 is 1 to 50. As an example, when the doping concentration of the first conductive type column is 1e +15 and the doping concentration of the second conductive type column 11 is 1.6e +15, the doping concentration of the second conductive type region is 1e +15 to 5e + 16.
In this embodiment, the first conductive type epitaxial layer 10 is N-type single crystal silicon, and the second conductive type region 12 and the main junction 13 are both P-type single crystal silicon. The first conductive type epitaxial layer 10 is a multi-layered epitaxial layer stack structure having a lowermost epitaxial layer (not shown in fig. 1, refer to 100 in fig. 12), a uppermost epitaxial layer (not shown in fig. 1, refer to 105 in fig. 12), and an epitaxial layer sandwiched between the lowermost epitaxial layer and the uppermost epitaxial layer. The main node 13 and the second conductive type region 12 have the same conductive type and are both formed in the topmost epitaxial layer, the top surfaces of the second conductive type region 12 and the main node 13 are both flush with the top surface of the topmost epitaxial layer, and the bottom surfaces of the second conductive type region 12 and the main node 13 are both flush with the bottom surface of the topmost epitaxial layer, that is, the depths of the main node 13 and the second conductive type region 12 are both the same. The top surfaces of all the second conductive type pillars 11 are flush with the bottom surface of the topmost epitaxial layer, and the bottom surfaces of all the second conductive type pillars 11 are flush with each other and extend into a partial depth of the bottommost epitaxial layer.
In this embodiment, the second conductivity type regions 12 are unevenly distributed, 3 second conductivity type regions 12 next to the main junction 13 are respectively disposed on the top ends of three second conductivity type pillars 11 that are continuously adjacent, and the remaining second conductivity type regions 12 are disposed at equal intervals and are all spaced by one second conductivity type pillar 11 in the direction from the main junction 13 to the terminal region boundary. The thus-arranged second conductivity type region 12 can improve the surface potential distribution of the super junction termination structure, avoiding the concentration of a local electric field.
It should be noted that the technical solution of the present invention is not limited to the structure of the above embodiment, when the second conductive type pillars 11 in the terminal area are uniformly distributed and have the same line width, the interval between adjacent second conductive type regions 12 in the terminal area may also be gradually increased, or the second conductive type regions 12 are uniformly distributed, that is, the number of the second conductive type pillars 11 spaced between any adjacent second conductive type regions 12 is the same; alternatively, when the interval between two adjacent second conductivity type pillars 11 in the termination region is gradually increased, the number of second conductivity type pillars 11 of the interval between adjacent second conductivity type regions 12 in the termination region is the same, so that the interval between adjacent second conductivity type regions 12 in the termination region is gradually increased and the distribution density of the second conductivity type regions 12 in the termination region is gradually decreased. Specifically, as an example, as shown in fig. 2, the second conductive type pillars 11 in the terminal area are uniformly distributed, the line widths of the second conductive type pillars 11 are the same, the line widths of the first conductive type pillars are also the same, the line widths of the second conductive type regions 12 are the same, and the number of the second conductive type pillars 11 spaced between two adjacent second conductive type regions 12 is gradually increased from the outer sidewall of the main junction 13 toward the boundary of the terminal area, for example, 0, 1, 2, 3 …. As another example, referring to fig. 3, the second conductivity-type pillars 11 in the termination region are uniformly distributed, the line widths of the second conductivity-type pillars 11 are the same, the line widths of the first conductivity-type pillars are also the same, the line widths of the second conductivity-type regions 12 are the same, the second conductivity-type regions 12 in the termination region are uniformly distributed, one second conductivity-type pillar 11 is spaced between the second conductivity-type region 12 next to the main junction 13 and the main junction 13, and one second conductivity-type pillar 11 is spaced between any two adjacent second conductivity-type regions 12 in the remaining second conductivity-type regions 12. As still another example, referring to fig. 4, the line widths of the second conductivity-type pillars 11 located at the periphery of the main junction 13 in the terminal region are all the same, the intervals between adjacent second conductivity-type pillars 11 are gradually increased along the direction from the main junction 13 to the terminal region boundary, that is, the line widths of the first conductivity-type pillars are gradually increased, but the line widths of the respective second conductivity-type regions 12 are the same, and one second conductivity-type pillar 11 is also arranged between two adjacent second conductivity-type regions 12, and one second conductivity-type pillar 11 is also arranged between the second conductivity-type region 12 next to the main junction 13 and the main junction 13, so that the distribution density of the second conductivity-type regions 12 in the terminal region is gradually decreased along the direction from the main junction 13 to the terminal region boundary.
It should be further noted that, in the direction parallel to the substrate surface, the shape of the cross section of the second conductivity type region 12 on the top end of the second conductivity type pillar 11 depends on the shape of the cross section of the second conductivity type pillar 11 in the terminal region, when the shape of the cross section of the second conductivity type pillar 11 in the terminal region is a ring shape, the shape of the cross section of the second conductivity type region 12 is a ring shape, the shape of the cross section of the combination of the plurality of second conductivity type regions 12 is a plurality of concentric ring shapes, when the shape of the cross section of the second conductivity type pillar 11 in the terminal region is a bar shape, the shape of the cross section of the second conductivity type region 12 is a bar shape, and the shape of the cross section of the combination of the plurality of second conductivity type regions 12 is a plurality of mutually parallel bar shapes.
Based on the structure of the super junction device shown in fig. 1 to 4, the invention also provides a manufacturing method of the super junction device, which comprises the following steps:
providing a substrate having a core region and a termination region;
forming a first conductive type epitaxial layer on the substrate, forming a plurality of first conductive type pillars and second conductive type pillars which are alternately arranged in the first conductive type epitaxial layer of the terminal region, and forming a main junction and a plurality of second conductive type regions, wherein the main junction is close to the core region and is formed on the top end of at least one first conductive type pillar and/or second conductive type pillar, each second conductive type region is located at the periphery of the main junction and is respectively formed on the top end of the corresponding second conductive type pillar, and at least one second conductive type pillar is arranged between at least part of adjacent second conductive type regions.
In order to better understand the method for manufacturing the superjunction device of the present invention, the superjunction device shown in fig. 1 is taken as an example, and the method for manufacturing the superjunction device of the present invention is described in detail with reference to fig. 5 and fig. 6 to fig. 12, and fig. 13 and fig. 14 to fig. 18, respectively.
Referring to fig. 5, an embodiment of the invention provides a method for manufacturing a super junction device, including:
s1a, growing a bottom epitaxial layer on a substrate with a core region and a terminal region;
s1b, performing first ion implantation on a partial region of the bottom epitaxial layer by adopting second conductive type ions;
s1c, circularly executing the steps S1 a-S1 b until the circulating times reach the required times;
s1d, growing a topmost epitaxial layer, and performing second ion implantation on a partial region of the topmost epitaxial layer by adopting second conductive type ions, wherein the region subjected to the second ion implantation is aligned with the corresponding region subjected to the first ion implantation;
s1e, annealing, so that the diffusion regions corresponding to the first ion implantation are connected in two bottom epitaxial layers adjacent to each other up and down to form second conductive type columns and first conductive type columns which are alternately arranged, and the diffusion regions corresponding to the second ion implantation are connected with the top ends of the corresponding second conductive type columns to form second conductive type regions;
s1f, performing third ion implantation on the topmost epitaxial layer close to the core region by adopting second conductive type ions to form a main junction, wherein the bottom of the main junction is contacted with the top end of at least one second conductive type column;
s1g, forming a field oxide layer at least on the surface of the first conduction type epitaxial layer of the terminal area, wherein the field oxide layer exposes the top surface of the main junction;
s1h, forming a gate oxide layer on at least part of the top surface of the main junction and a gate layer on the gate oxide layer, wherein the gate layer and the gate oxide layer also extend to the surface of the field oxide layer at the periphery of the main junction;
s1i, forming an interlayer dielectric layer on the gate layer, the field oxide layer and the main junction, wherein the interlayer dielectric layer is provided with a contact hole exposing partial surface of the main junction and a contact hole exposing partial surface of the gate;
s1j, forming a metal interconnection structure, wherein the metal interconnection structure fills the contact hole and extends on part of the upper surface of the interlayer dielectric layer.
Referring to fig. 6, in step S1a, a substrate (not shown) having a core region and a termination region, such as a Si single crystal substrate, is provided, and a bottom epitaxial layer 100 is formed on the substrate by a deposition process, such as chemical vapor deposition or atomic layer deposition, wherein the bottom epitaxial layer 100 is a semiconductor layer doped with first conductivity type ions (e.g., N-type ions such as germanium and/or arsenic), and the bottom epitaxial layer 100 is, for example, N-type single crystal Si; then, a first patterned photoresist layer 20 is formed through a series of photolithography processes of photoresist coating, exposure, development, etc., the first patterned photoresist layer 20 having ion implantation openings for forming second conductive type pillars.
With reference to fig. 6, in step S1b, first, the top layer of the bottom-most epitaxial layer 100 is ion-implanted with second conductivity type ions, such as one or a combination of boron, boron fluoride, phosphorus, etc., along a vertical incidence direction by using the first patterned photoresist layer 20 as a mask to form a plurality of second conductivity type ion-implanted regions 110 with the same depth. Then, the first patterned photoresist layer 20 is removed.
Referring to fig. 7 to 8, in step S1c, the above steps S1a to S1b are repeated, and the specific number of times and the thickness of the bottom epitaxial layer formed each time are different based on the required withstand voltage and the subsequent annealing process. This embodiment is repeated four times, and finally, the bottom epitaxial layers 101, 102, 103, and 104 having the first conductivity type, the bottom epitaxial layers 101 and 102, 103. 104 may be the same and thinner than the lowest epitaxial layer 100, the doping concentration of the first conductivity type ions of the bottom epitaxial layers 101, 102, 103, 104 may be the same as the doping concentration of the first conductivity type ions of the bottom epitaxial layer 101, a second conductivity type ion implantation region 111 aligned with the second conductivity type ion implantation region 110 is formed in the bottom epitaxial layer 101, a second conductivity type ion implantation region 112 aligned with the second conductivity type ion implantation region 111 is formed in the bottom epitaxial layer 102, a second conductivity type ion implantation region 113 aligned with the second conductivity type ion implantation region 112 is formed in the bottom epitaxial layer 103, and a second conductivity type ion implantation region 114 aligned with the second conductivity type ion implantation region 113 is formed in the bottom epitaxial layer 104.
Referring to fig. 9, in step S1d, a topmost epitaxial layer 105 is formed on a bottom epitaxial layer 104 by a deposition process such as chemical vapor deposition or atomic layer deposition, wherein the topmost epitaxial layer 105 is a semiconductor layer doped with first conductivity type ions (e.g., N-type ions such as germanium and/or arsenic) and has a thickness smaller than that of the bottom epitaxial layer 104, and the doping concentration of the first conductivity type ions may be the same as that of the first conductivity type ions of the bottom epitaxial layer 104. Then, a second patterned photoresist layer 30 is formed through a series of photolithography processes such as photoresist coating, exposure, and development, the second patterned photoresist layer 30 has an upper surface capable of exposing a region of the topmost epitaxial layer 105 for forming a second conductive type region and shielding surfaces of other regions of the topmost epitaxial layer 105, the second patterned photoresist layer 30 has a plurality of ion implantation openings for forming the second conductive type region, a line width of each ion implantation opening of the second patterned photoresist layer 30 is 0.8 to 1.2 times a line width of the ion implantation opening of the first patterned photoresist layer 20, and at least one second conductive type ion implantation region 111 is spaced between at least some adjacent ion implantation openings. Next, using the second patterned photoresist layer 30 as a mask, performing ion implantation on the top layer of the topmost epitaxial layer 105 along a vertical incident direction by using second conductive type ions to form a plurality of second conductive type ion implantation regions 120 with the same depth, wherein the doping concentrations of the second conductive type ions in the second conductive type ion implantation regions 120 and the second conductive type ion implantation regions 114 are different. For example, the doping concentration ratio of the second conductive type ions in the second conductive type ion implantation region 120 and the second conductive type ion implantation region 114 is 1 to 50. Then, the second patterned photoresist layer 30 is removed. Referring to fig. 9 and 10, in step S1e, a rapid annealing process is used to anneal the entire device having the second conductive type ion implantation region 120, and the second conductive type ions in the second conductive type ion implantation regions 110 to 114 are longitudinally and laterally diffused, wherein after the second conductive type ions in the second conductive type ion implantation regions 110 to 114 are longitudinally diffused, the bottom of the second conductive type ion implantation region 114 is connected to the top of the second conductive type ion implantation region 113, the bottom of the second conductive type ion implantation region 113 is connected to the top of the second conductive type ion implantation region 112, the bottom of the second conductive type ion implantation region 112 is connected to the top of the second conductive type ion implantation region 111, the bottom of the second conductive type ion implantation region 111 is connected to the top of the second conductive type ion implantation region 110, second conductive type columns 11 are formed, the bottom epitaxial layer 100, the bottom epitaxial layers 101-104 and the top epitaxial layer 105 are stacked to form a first conductive type epitaxial layer 10, the first conductive type epitaxial layer 10 sandwiched between two adjacent second conductive type columns 11 is used as a first conductive type column, and therefore the first conductive type columns and the second conductive type columns 11 which are alternately arranged are formed on the first conductive type epitaxial layer 10. The bottom of the second conductive type ion implantation region 120 is diffused to the top of the corresponding second conductive type pillar 11 to form a second conductive type region 12, and the line width of the second conductive type region 12 is 0.8 to 1.2 times the line width of the second conductive type pillar 11.
Referring to fig. 10, in step S1f, a third patterned photoresist layer (not shown) having a surface capable of exposing the region of the topmost epitaxial layer 105 for forming the main junction and blocking the other regions of the topmost epitaxial layer 105 is formed through a series of photolithography processes including photoresist coating, exposure, development, and the like. Then, using the third patterned photoresist layer as a mask, performing ion implantation on the top layer of the topmost epitaxial layer 105 along a vertical incident direction by using second conductive type ions to form an ion implantation region having the same depth as the second conductive type ion implantation region 120, where the doping concentrations of the second conductive type ions in the ion implantation region and the second conductive type ion implantation region 120 may be the same or different. The third patterned photoresist layer is then removed and an annealing process is performed to form the main junction 13.
Referring to fig. 11, in step S1g, a field oxide layer 14 is formed by silicon oxide deposition, photolithography, and etching. The field oxide layer 14 is usually formed on the surface of the core region and the surface of the termination region together, the field oxide layer 14 of the termination region can expose part or all of the top surface of the main junction 13, and the field oxide layer of the core region can expose the surface of the region where the MOS transistor is to be formed. The process of forming the field oxide layer 14 may refer to a conventional field oxide process in the art and will not be described in detail herein.
With continued reference to fig. 11, in step S1h, first, the gate oxide layer 15 and the gate electrode layer 16 may be sequentially formed by a gate-first process or a gate-last process, wherein the gate oxide layer 15 may be silicon oxide or a high-K dielectric with a dielectric constant K greater than 7, the gate electrode layer 16 is polysilicon when the gate oxide layer 15 is silicon dioxide, and the gate electrode layer 16 is a metal gate when the gate oxide layer 15 is a high-K dielectric. The process of forming the gate oxide layer 15 and the gate electrode layer 16 can refer to a conventional gate process in the art, and will not be described in detail herein.
After the gate layer 16 is formed, N-type and/or P-type ion implantation may be performed on the main junction and other regions using the gate layer 16 as a mask to form well and source regions and other structures. Ion implantation may be further performed from the substrate side facing away from the first conductivity type epitaxial layer 10 to form a drain region.
Referring to fig. 12, in step S1i, first, an interlayer dielectric layer 17 may be covered on the device surfaces in the core region and the termination region by a chemical vapor deposition process, and a chemical mechanical polishing process is used to planarize a top surface of the interlayer dielectric layer 17, and the planarized interlayer dielectric layer 17 embeds the gate layer 16, the field oxide layer 14, and the main junction 13; the interlayer dielectric layer 17 is then etched by photolithography and contact hole etching processes to form contact holes in the interlayer dielectric layer 17 exposing portions of the surface of the gate layer 16 and to form contact holes exposing corresponding regions of the main junctions 13.
Referring to fig. 12, in step S1j, a metal interconnection structure 18 is formed by a series of processes including metal deposition, photolithography, and etching, the metal interconnection structure 18 includes a contact plug filled in the contact hole and a metal line covering a portion of the interlayer dielectric layer 17, and the metal line is electrically connected to the contact plug. The material of metal interconnect structure 18 may include at least one of Co, Ni, W, Cu, Al.
Steps S1 g-S1 j complete the fabrication of the surface VDMOS portion, thereby forming a superjunction termination structure in the termination region.
According to the manufacturing method of the super-junction device, the corresponding first conduction type column, second conduction type column and second conduction type region are formed by circularly performing the processes of epitaxial layer deposition and ion implantation, and the formed super-junction device has low on-resistance and satisfactory voltage resistance. In addition, during ion implantation, the line width of an ion implantation window for forming the second conductive type region is set to be 0.8 to 1.2 times of the line width of the ion implantation window for forming the second conductive type column each time, so as to increase the ion implantation concentration range for forming the second conductive type region, thereby enlarging the process window for forming the super junction terminal structure, reducing the process difficulty for forming the second conductive type region, further solving the problem that more second conductive type regions are required to be arranged due to the over-small line width of the second conductive type region to avoid the surface electric field from being easily concentrated and ensure the voltage resistance, and solving the problem that the boron absorption and phosphorus removal phenomenon in the process for forming the field oxide layer causes the change of the surface impurity concentration to be increased due to the over-large line width of the second conductive type region, and further the influence on the voltage resistance of the device is increased.
It should be noted that in the above embodiments, the main junction 13 and the second conductive type region 12 are formed by two ion implantations, but in other embodiments of the present invention, the second patterned photoresist layer 30 in fig. 9 may also have an opening exposing the opening for forming the main junction 13, so that the main junction 13 and the second conductive type region 12 may be formed simultaneously by the same ion implantation process, thereby further simplifying the process.
In addition, the forming process of the second-type conductive pillar of the present invention is not limited to the above example, and in other embodiments of the present invention, the first conductive-type pillar and the second conductive-type pillar that are alternately arranged may also be formed through a process of trench etching and filling.
Specifically, referring to fig. 13 and 14 to 18, another embodiment of the present invention further provides a method for manufacturing a superjunction device, including:
s2a, growing a bottom epitaxial layer of the first conductivity type on a substrate (not shown) having a core region and a termination region, specifically, referring to fig. 14, the bottom epitaxial layer 10a of the first conductivity type may be formed by multiple epitaxial layer deposition processes, and the thickness thereof may be equal to the stack thickness of the bottom epitaxial layer 100 and the bottom epitaxial layers 101 to 104 in fig. 8.
S2b, etching the bottom epitaxial layer with partial thickness to form a plurality of deep grooves. Specifically, with reference to fig. 14, in step S2b, a first patterned photoresist layer 20 is first formed on the surface of the bottom epitaxial layer 10a by a photolithography process, and then the bottom epitaxial layer 10a is etched to a desired depth by using the first patterned photoresist layer 20 as a mask to form a plurality of deep trenches 11 a. The first patterned photoresist layer 20 is then removed.
S2c, filling the deep groove with a second conduction type epitaxial layer to form second conduction type columns and first conduction type columns which are alternately arranged in the bottom epitaxial layer. Specifically, referring to fig. 14 and 15, in step S2c, an epitaxial layer may be filled in each deep trench 11b through an epitaxial layer deposition process, and second conductive type ions are used for in-situ doping during the epitaxial layer deposition process, so that the filled epitaxial layer is a second conductive type epitaxial layer, and after the filling is completed, the excess second conductive type epitaxial layer on the top surface of the bottom epitaxial layer 10a is removed through a chemical mechanical polishing process, so as to form second conductive type pillars 11 filled in each deep trench 11a, where the bottom epitaxial layer 10a between adjacent second conductive type pillars 11 is a first conductive type pillar. In order to ensure the filling quality of the second conductivity type epitaxial layer in the deep trench 11a, the second conductivity type epitaxial layer deposition and the chemical mechanical polishing may be repeated multiple times.
S2d, growing a topmost epitaxial layer on the bottom epitaxial layer, wherein the topmost epitaxial layer and the bottom epitaxial layer form the first conduction type epitaxial layer. Specifically, referring to fig. 16, in step S2d, the topmost epitaxial layer 10b may be grown by the same process as the topmost epitaxial layer 105 in step S1d, and the detailed process is not described in detail herein. The topmost epitaxial layer 10b and the bottom epitaxial layer 10a constitute the first conductivity type epitaxial layer 10.
S2e, forming a second conductive type region connected with the top end of the corresponding second conductive type column in the topmost epitaxial layer by a method of forming a shallow trench in the topmost epitaxial layer and filling the topmost epitaxial layer with a second conductive type epitaxial layer or a method of performing second conductive type ion implantation on the topmost epitaxial layer. Specifically, referring to fig. 16 and 17, in step S2e, a fourth patterned photoresist layer 40 may be first formed on the topmost epitaxial layer 10b through a corresponding photolithography process, the fourth patterned photoresist layer 40 exposing regions where main junction and second conductive type regions are to be formed; then, with the fourth patterned photoresist layer 40 as a mask, etching the topmost epitaxial layer 10b to form a shallow trench 105b and a plurality of shallow trenches 121, wherein at least one second conductive type column 11 is spaced between at least part of adjacent openings 121, and the ratio of the line width of each opening 121 to the line width of the second conductive type column directly below the opening 121 is 0.8-1.2; next, the main junction 13 filled in the shallow trench 105b and the second conductive type region 12 filled in each shallow trench 121 are formed through the second conductive type epitaxial layer deposition and the top planarization process after the deposition. Thus, the main junction 13 and the second conductive type region 12 have the same conductive type and are formed using the same process. At this time, the top surfaces of the second conductive type pillars 11 are flush with the bottom surface of the topmost epitaxial layer 10b, and the bottom surfaces of the second conductive type pillars 11 protrude into a partial depth of the bottom epitaxial layer 10 a. In addition, the doping concentration ratio of the second conductive type ions in the second conductive type region 12 and the second conductive type column 11 is 1-50.
In this embodiment, after step S2e, please refer to fig. 5 and fig. 18, step S1g to step S1j are performed to complete the preparation of the surface VDMOS portion, so that the super junction termination structure is formed in the termination region, and the specific process may refer to the above description and is not repeated herein.
According to the manufacturing method of the super junction device, the groove can be formed by etching the first conduction type bottom epitaxial layer with enough thickness, and the second conduction type column is formed by filling the second conduction type epitaxial layer in the groove, so that the process of multiple times of ion implantation is avoided, and the process is relatively simplified.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
Claims (10)
1. A super junction device comprising a first conductivity type epitaxial layer having a core region and a termination region located at a periphery of the core region, wherein the super junction device is provided with a super junction termination structure within the first conductivity type epitaxial layer of the termination region, the super junction termination structure comprising:
a plurality of first conductive type pillars and second conductive type pillars arranged alternately;
a main junction proximate the core region and formed on a top end of at least one first and/or second conductivity type pillar;
and the second conductive type regions are positioned at the periphery of the main junction and are respectively formed on the top ends of the corresponding second conductive type columns, and at least one second conductive type column is arranged between at least part of adjacent second conductive type regions.
2. The superjunction device of claim 1, wherein the first conductivity type epitaxial layer is a multi-layer epitaxial layer stack structure, the main junction and the second conductivity type region are located in a topmost epitaxial layer of the first conductivity type epitaxial layer, and both conductivity type and depth are the same.
3. The superjunction device of claim 1, wherein a ratio of a line width of the second conductivity type region to a line width of the second conductivity type pillar directly thereunder is 0.8 to 1.2.
4. The superjunction device of claim 1, wherein a ratio of a doping concentration of the second conductivity type region to a doping concentration of the second conductivity type pillar is 1 to 50.
5. The superjunction device of claim 1, wherein the second conductivity type regions are uniformly distributed or the distribution density of the second conductivity type regions gradually decreases in a direction from the main junction toward the boundary of the termination region.
6. The superjunction device of claim 5, wherein the second conductivity-type pillars are uniformly distributed in the termination region, but a number of the second conductivity-type pillars of a space between adjacent second conductivity-type regions is gradually increased such that a distribution density of the second conductivity-type regions is gradually decreased in a direction of the main junction toward the termination region boundary; or, the number of the second conductive type pillars of the interval between the adjacent second conductive type regions is the same, but the distribution density of the second conductive type pillars in the termination region is gradually reduced along the direction from the main junction to the boundary of the termination region, so that the distribution density of the second conductive type regions is gradually reduced along the direction from the main junction to the boundary of the termination region.
7. A method of manufacturing a super junction device, comprising:
providing a substrate having a core region and a termination region;
forming a first conductive type epitaxial layer on the substrate, forming a plurality of first conductive type pillars and second conductive type pillars which are alternately arranged in the first conductive type epitaxial layer of the terminal region, and forming a main junction and a plurality of second conductive type regions, wherein the main junction is close to the core region and is formed on the top end of at least one first conductive type pillar and/or second conductive type pillar, each second conductive type region is located at the periphery of the main junction and is respectively formed on the top end of the corresponding second conductive type pillar, and at least one second conductive type pillar is arranged between at least part of adjacent second conductive type regions.
8. The method of manufacturing a superjunction device of claim 7,
the step of forming a first conductive type epitaxial layer having a plurality of second conductive type pillars and the second conductive type regions on the substrate includes:
(a) growing a bottom epitaxial layer on the substrate;
(b) carrying out first ion implantation on a partial region of the bottom epitaxial layer by adopting second conductive type ions;
(c) circularly executing the steps (a) to (b) until the number of circulation reaches the required number;
(d) growing a topmost epitaxial layer, and performing second ion implantation on a partial region of the topmost epitaxial layer by adopting second conductive type ions, wherein the region subjected to the second ion implantation is aligned to the corresponding region subjected to the first ion implantation;
(e) annealing, so that the diffusion regions corresponding to the first ion implantation are connected in two bottom epitaxial layers which are adjacent up and down to form second conductive type columns and first conductive type columns which are alternately arranged, and the diffusion regions corresponding to the second ion implantation are connected with the top ends of the corresponding second conductive type columns to form second conductive type regions;
or, the step of forming the first conductive type epitaxial layer having the second conductive type pillars and the second conductive type regions on the substrate includes:
(a) growing a bottom epitaxial layer having a first conductivity type on the substrate;
(b) etching the bottom epitaxial layer with partial thickness to form a plurality of deep grooves;
(c) filling a second conductive type epitaxial layer in the deep groove to form second conductive type columns and first conductive type columns which are alternately arranged in the bottom epitaxial layer;
(d) growing a topmost epitaxial layer on the bottom epitaxial layer, wherein the topmost epitaxial layer and the bottom epitaxial layer form the first conduction type epitaxial layer;
(e) and forming a second conductive type region in the topmost epitaxial layer.
9. The method of manufacturing a superjunction device of claim 7, wherein the main junction and the second conductivity type region are of the same conductivity type and are formed using the same process.
10. The method for manufacturing a super junction device according to claim 7, wherein a ratio of a line width of the second conductivity type region formed to a line width of the second conductivity type pillar directly below the second conductivity type region is 0.8 to 1.2; and/or the ratio of the doping concentration of the formed second conductive type region to the doping concentration of the formed second conductive type column is 1-50.
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| CN115148791B (en) * | 2022-09-05 | 2022-12-02 | 深圳市威兆半导体股份有限公司 | Super junction MOSFET |
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