CN111725319B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN111725319B CN111725319B CN202010579365.XA CN202010579365A CN111725319B CN 111725319 B CN111725319 B CN 111725319B CN 202010579365 A CN202010579365 A CN 202010579365A CN 111725319 B CN111725319 B CN 111725319B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/086—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof, the device includes: substrate, epitaxial layer, source end region, drain terminal region, grid structure and side wall, this source end region includes: a P-type well region; at least one first implanted region; at least one second implanted region; a first lightly doped region; a second shallow doped region; and a third injection region formed in the whole source region and covering all the first injection region, the second injection region, the first shallow doping region and the second shallow doping region, wherein the third injection region is an N-type injection region, and the doping concentration of the third injection region is greater than that of the first and second shallow doping regions and less than that of the first and second injection regions. According to the invention, the N-type injection region with higher concentration than that of the shallow doped region is added in the source end region, so that the on-resistance between the source end and the drain end is effectively reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
With the widespread use of Lateral Double Diffused MOS transistors (LDMOS) in integrated circuits, the performance requirements for LDMOS are also increasing, as devices capable of having a higher off-breakdown voltage (off-BV) and a lower on-resistance (Rdson) are generally required.
Generally, a method for reducing the on-resistance of the LDMOS device is to use various RESURF (Reduced SURface Field) theories to fully deplete the LDMOS device while continuously increasing the concentration of the drift region, so as to obtain a low on-resistance and maintain a high breakdown voltage. But the device size can be reduced, so that the device area is smaller, and the on-resistance is further reduced.
Fig. 1 shows a top view of a source region of an LDMOS device, and fig. 2 shows a cross-sectional view of the source region of the LDMOS device shown in fig. 1. As shown in fig. 1 and fig. 2, the LDMOS device structure mainly includes a substrate 10, an epitaxial layer 20, a source region, a drain region, a polysilicon gate 41, a gate dielectric layer 42, and sidewalls 43, where the source region includes a P-type body 30 and a plurality of implantation regions 31 (including an N + implantation region and a P + implantation region) located in the P-type body 30 and arranged laterally along a side surface of the gate structure. The N + injection region and the P + injection region of the source end region are formed through photoetching injection and limited by photoetching capability, and the sizes of the formed N + injection region and the formed P + injection region are not too small. Taking an NLDMOS (N-type lateral double-diffused transistor) with a 180nm technology as an example, the N + implantation region and the P + implantation region of the source end region are both about 0.4um, as shown in fig. 1 and 2, and the spacing between the polysilicon gates of the gate structure portions of the source ends is about 1.2 um. On the basis of the structure, the on-resistance between the source end and the drain end of the LDMOS device is very large, so that the performance of the LDMOS device is reduced, and the application prospect of the LDMOS device is influenced.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the above technical problem, the present invention provides a semiconductor device and a manufacturing method thereof, which can reduce the on-resistance of a source end region, prevent the increase of the overall effective resistance caused by the lengthening of a current path in a channel from a drain end to the source end and the concentration of current at the boundary of a source end injection region, and effectively reduce the on-resistance between the source end and the drain end.
According to the present invention, there is provided a semiconductor device comprising: the epitaxial layer is formed on the substrate; a source region, a drain region and a gate structure formed on the epitaxial layer, wherein the gate structure partially covers the source region and the drain region; the side wall formed on the side face of the grid structure is characterized in that the source end region comprises: a P-type well region; at least one first injection region formed in the P-type well region; at least one second injection region formed outside the at least one first injection region in the P-type well region; first shallow doped regions formed in the at least one first implanted region and on both sides of each first implanted region; second shallow doped regions formed in the at least one second implanted region and on both sides of each second implanted region; and a third implantation region formed in the entire source region and covering all of the first implantation region, the second implantation region, the first shallow doping region and the second shallow doping region, wherein the third implantation region is an N-type implantation region, and the doping concentration of the third implantation region is greater than the doping concentrations of the first shallow doping region and the second shallow doping region and less than the doping concentrations of the at least one first implantation region and the at least one second implantation region.
Preferably, the at least one first implanted region and the at least one second implanted region are arranged longitudinally along a side of the gate structure.
Preferably, the gate structure includes: and the polysilicon gate and the gate dielectric layer are formed on the upper surface of the epitaxial layer.
Preferably, the at least one first implantation region is a P + implantation region, and the at least one second implantation region is an N + implantation region.
Preferably, the first shallow doped region is a PLDD region or a PDD region, wherein the PDD region is a lightly doped P-type region formed by a large-angle oblique implantation of a side wall in the first implantation region P + implantation and having a lower concentration than that of the first implantation region, and the PLDD region is a P-type lightly doped region implanted after the polysilicon gate is etched and before the side wall is formed.
Preferably, the second shallow doped region is an NDD region, wherein the NDD region is a lightly doped N-type region formed by the sidewall through a large-angle oblique implantation that is increased during the N + implantation of the second implantation region and has a lower concentration than the second implantation region.
According to the invention, the manufacturing method of the semiconductor device comprises the following steps: forming a substrate; forming an epitaxial layer on the upper part of the substrate; forming a field oxide layer on the epitaxial layer; forming a polysilicon gate and a gate dielectric layer which are positioned on the surface of the epitaxial layer and cover part of the source end region; forming a drain terminal region and a source terminal region which are positioned on the upper part of the epitaxial layer and are mutually separated; forming a side wall on the side face of the polysilicon gate, wherein the forming of the source end region comprises: forming a P-type well region on the epitaxial layer; forming at least one first injection region and at least one second injection region in the P-type well region; forming first shallow doped regions in the at least one first injection region and on two sides of each first injection region; forming second shallow doped regions in the at least one second injection region and on two sides of each second injection region; and forming a third injection region which is positioned in the whole source region and covers all of the first injection region, the second injection region, the first shallow doping region and the second shallow doping region, wherein the third injection region is an N-type injection region, and the doping concentration of the third injection region is greater than that of the first shallow doping region and that of the second shallow doping region and is less than that of the at least one first injection region and that of the at least one second injection region.
Preferably, the at least one first implant region and the at least one second implant region are arranged longitudinally along a side of the polysilicon gate.
Preferably, the at least one first implantation region is a P + implantation region, and the at least one second implantation region is an N + implantation region.
Preferably, the first shallow doping region is a PLDD region or a PDD region, and the second shallow doping region is an NDD region.
Preferably, the third implantation region is formed after the polysilicon gate is formed.
The invention has the beneficial effects that: the invention discloses a semiconductor device and a manufacturing method thereof, wherein an N-type injection region (namely a third injection region) which has higher concentration than a first shallow doping region and a second shallow doping region beside an injection region (comprising at least one first injection region and at least one second injection region) of a source end of the device and lower concentration than the injection region of the source end is directly injected into the source end after a polysilicon gate of the device is etched, so that the current can be ensured to directly flow from a drain end to the source end no matter whether the injection region of the source end is an N + injection region or a P + injection region, meanwhile, the N-type injection regions (third injection regions) on two sides of the edge of the P + injection region in the injection region of the source end can ensure that the current in a channel does not need to be forced to turn, the phenomena of current path lengthening in the channel and current concentration at the edge of the injection region of the source end are prevented, and the integral effective resistance of the device is further reduced, so that the source and drain ends of the device have lower on-resistance.
The at least one first injection region and the at least one second injection region are arranged longitudinally along the side face of the grid structure, so that the space of the polysilicon grid of the device is reduced, and the on-resistance between the source and the drain of the device is further reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a top view of a source terminal region of an LDMOS device;
FIG. 2 is a cross-sectional view of the structure of the source region of the LDMOS device of FIG. 1;
fig. 3 is a schematic diagram showing a drain-to-source current path of an NLDMOS device under different source injection regions according to the prior art;
fig. 4 shows a schematic cross-sectional structure of the source end region of the NLDMOS device along the AA' direction in fig. 3;
fig. 5 shows a schematic cross-sectional structure of a source end region of the NLDMOS device of fig. 3 along the BB' direction;
fig. 6 is a schematic diagram illustrating drain-to-source current paths of an LDMOS device under different source injection regions according to an embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view of the source region of the LDMOS device of FIG. 6 along the CC' direction;
FIG. 8 is a schematic cross-sectional view of the source region of the LDMOS device of FIG. 6 along the DD' direction;
fig. 9 is a schematic cross-sectional structure diagram of a source end region of a conventional ldmos device in which a shallow doped region is an NLDD region;
fig. 10 is a schematic cross-sectional structure diagram of a source end region of an LDMMOS device provided in an embodiment of the present invention;
fig. 11a to 11f show schematic cross-sectional views of stages in a method of manufacturing a source end region structure of an LDMMOS device according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
When a layer, a region, or a region is referred to as being "on" or "over" another layer, another region, or a region may be directly on or over the other layer, the other region, or another layer or a region may be included between the layer and the other layer or the other region. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.
Unless otherwise specified below, various layers or regions of a semiconductor device may be composed of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, InP, GaN, SiC, and group IV semiconductors such as Si, Ge. The gate conductor, electrode layer may be formed of various materials that are electrically conductive, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other electrically conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the various conductive materials.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed. The term "laterally extending" refers to extending in a direction substantially perpendicular to the depth direction of the trench.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 3 shows a schematic diagram of a drain-to-source current path of an NLDMOS device under different source injection regions according to a conventional NLDMOS device, fig. 4 shows a schematic diagram of a cross-sectional structure of a source region of the NLDMOS device along an AA 'direction in fig. 3, and fig. 5 shows a schematic diagram of a cross-sectional structure of a source region of the NLDMOS device along a BB' direction in fig. 3.
Referring to fig. 3 to 5, it can be known that the NLDMOS device structure includes: the semiconductor structure comprises a substrate 10, an epitaxial layer 20, a source end region, a drain end region, a polysilicon gate 41, a gate dielectric layer 42 and a side wall 43, wherein the source end region comprises a P-type main body 30 and a plurality of injection regions 31 (comprising at least one N + injection region and at least one P + injection region) which are positioned in the P-type main body 30 and are longitudinally arranged along the side surface of the gate structure. As shown in fig. 3, for example, a 5V NLDMOS device manufactured by a CMOS process is used, in order to reduce the on-resistance Rdson between the source and drain terminals of the device, the pitch of the polysilicon gate can be reduced to the minimum size of only one row of holes, about 0.5um, and a plurality of laterally arranged implantation regions 31 are changed to be longitudinally arranged along the side surface of the gate structure, so as to reduce the on-resistance between the source and drain terminals of the device.
Further, the cross-sectional structures of the NLDMOS device shown in fig. 3 as viewed along AA 'and BB' are shown in fig. 4 and 5, respectively. In fig. 4, for the case that the source terminal implantation region is the N + implantation region 311, a lightly doped region 32 (an NLDD region or an NDD region) is under the sidewall 43 on both sides of the source terminal, where the NLDD region is an N-type lightly doped drain implanted after the polysilicon gate 41 is etched and before the sidewall 43 is formed, and the NDD region is a lightly doped N-type region formed by a large-angle oblique implantation added when the sidewall is subjected to the N + implantation and having a concentration lower than that of N +. In fig. 5, for the case that the source side implantation region is a P + implantation region 312, a shallow doped region 32 (which is a PLDD region or a PDD region; where the definitions of the PLDD region and the PDD region are similar to those of the NLDD region and the NDD region) is below the sidewall 43 on both sides of the source side.
As can be seen from the above description, in the conventional semiconductor structure, the drain-to-source channel current of the device is shown by the solid/dashed line in fig. 3. For the N + injection region in the source end injection region of the device, the current in the corresponding channel is shown by the solid line, and the current can directly flow from the drain end to the source end and is collected by the N + injection region of the source end. For the P + injection region in the source end injection region of the device, the corresponding current in the channel is shown by a dotted line, and the current turns from the drain end of the device to flow to the nearest source end N + injection region. This results in an increased current path in the drain-to-source channel, and a concentration of the edge current in the source N + implant region also results in an increase in the effective resistance. Therefore, in the outgoing solution, although the spacing between the polysilicon gates at the source end is significantly reduced, the P + implantation region is limited by the absence of the N-type implantation region on both sides, and the current collection capability is lacking, so that the overall reduction effect on the on-resistance is limited.
Therefore, the source terminal region structure of the LDMOS device is improved again to form the device structure shown in fig. 6 to 10, so that the on-resistance between the drain terminal and the source terminal of the device can be effectively reduced no matter whether the source terminal injection region (corresponding to the first injection region hereinafter) of the LDMOS device is an N + injection region or a P + injection region. Fig. 6 shows a schematic diagram of a current path from a drain terminal to a source terminal of an LDMOS device provided by an embodiment of the present invention under different source terminal injection regions, fig. 7 shows a schematic diagram of a cross-sectional structure of a source terminal region of the LDMOS device in a CC 'direction in fig. 6, fig. 8 shows a schematic diagram of a cross-sectional structure of a source terminal region of the LDMOS device in a DD' direction in fig. 6, fig. 9 shows a schematic diagram of a cross-sectional structure of a shallow doped region of a source terminal region of an LDMOS device of an existing LDMOS device being an NLDD region, and fig. 10 shows a schematic diagram of a cross-sectional structure of a source terminal region of an LDMOS device provided by an embodiment of the present invention.
As can be seen from fig. 6 to 10, in the present embodiment, the LDMOS device structure includes: the semiconductor structure includes a substrate 210, an epitaxial layer 220 formed on the substrate 210, a source region, a drain region and a gate structure formed on the epitaxial layer 220, wherein the gate structure partially covers the source region and the drain region, and a sidewall 243 formed on a side surface of the gate structure. Wherein, the source end region of the LDMOS device further comprises: a P-well 230, at least one first implanted region 2312 formed in the P-well 230, at least one second implanted region 2311 formed outside the at least one first implanted region 2312 in the P-well 230, and first lightly doped regions formed in the at least one first implanted region 2312 and on both sides of each first implanted region 2312; the second shallow doping regions formed in the at least one second implantation region 2311 and at both sides of each second implantation region 2311 are the third implantation regions 233 formed in the entire source region and covering all of the first implantation region 2312, the second implantation region 2311, the first shallow doping region and the second shallow doping region.
At least one of the first implantation regions 2312 is a P + implantation region, at least one of the second implantation regions 2311 is an N + implantation region, and the third implantation region 233 is an N-type implantation region. Thus, whether the source region of the LDMOS device is an N + injection region or a P + injection region, the channel edge of the LDMOS device has an N-type region so that the source terminal can collect current in the channel. Meanwhile, the doping concentration of the third implant region 233 is greater than the doping concentrations of the first and second shallow dopant regions and less than the doping concentrations of the at least one first implant region 2312 and the at least one second implant region 2311. And with reference to fig. 6, wherein the corresponding drain-to-source in-channel current is shown by the solid line for the N + implant in the source region of the device and by the dashed line for the P + implant in the source region of the device. It can be further understood that, for both the N + implantation region and the P + implantation region in the source region of the device, an N-type region (i.e., the third implantation region 233) is formed on both sides of each implantation region, and the N-type region can ensure that the current in the channel flows from the drain to the source directly. And the current collected by the N-type regions on both sides of the P + implant region (i.e., the first implant region 2312) in the source region flows along the N-type region to the N + implant region (i.e., the second implant region 2311) in the source region and is finally collected by the N + implant region. As the current in the channel from the drain end to the source end does not need to be forced to turn, the P + injection region in the source end region of the LDMOS device can be ensured, the extraction of the P + injection region is not influenced, the P-type concentration of the first shallow doped region (PLDD region or PDD region) on two sides of the P + injection region can be covered, an N-type source end region (namely, the third injection region 233) with smaller on-resistance is formed, the current in the channel is better collected, the phenomena that the current path in the channel is lengthened and the current concentration occurs on the boundary of the source end injection region are prevented, the integral effective resistance of the device is further reduced, and the lower on-resistance is formed between the source end and the drain end of the device.
In this embodiment, the at least one first implantation region 2312 and the at least one second implantation region 2311 in the source region of the LDMOS device are longitudinally aligned along the side of the gate structure (the longitudinal alignment can be understood with reference to fig. 6, specifically, the extending direction of the side of the gate structure is regarded as the longitudinal direction). Therefore, the space between the polysilicon gates of the devices is reduced, and the on-resistance between the source and the drain of the devices is further reduced.
Further, the gate structure of the LDMOS device includes: a polysilicon gate 241 and a gate dielectric layer 242 formed on the upper surface of the epitaxial layer 220. The gate dielectric layer 242 is, for example, a gate oxide layer.
Referring to fig. 7 to 10, in the present embodiment, the second shallow doped regions formed in the at least one second implantation region 2311 and at two sides of each second implantation region 2311 are NDD regions. In other words, for the second implantation region 2311 in the source region, when the implantation process of NLDD is applied to both sides thereof, after the formation of the polysilicon gate 241 of the device, the NLDD implantation (i.e. the lightly doped region 32 in the conventional technology) as shown in fig. 9, which should be performed, is changed to the more concentrated N-type implantation as shown in fig. 10, thereby forming the third implantation region 233. At this time, the source end region of the device has no shallow doped region, and the drain end region of the device still needs to remain the NLDD region, so as to ensure the HCI characteristics of the device. When the NDD implantation process is used on both sides of the device, after the polysilicon gate 241 of the device is formed and before the sidewall 243 of the device is formed, the third implantation region 233 may be formed by adding the N-type implantation region with the above concentration requirement to the source end region. The source region of the device now has a shallow doped region of NDD type and also has a third implanted region 233 of higher concentration than the second shallow doped region but lower concentration than the second implanted region 2311. The NDD region is a lightly doped N-type region formed by increasing a large angle oblique implantation of the sidewall 243 during the P + implantation in the second implantation region 231, and having a lower concentration than the second implantation region 231; the NLDD is an N-type lightly doped region implanted after the polysilicon gate 241 is etched and before the formation of the sidewall 243.
As shown in fig. 8, in the present embodiment, the first shallow doped regions formed in the at least one first implantation region 2312 and at both sides of each first implantation region 2312 are PDD regions or PLDD regions. In other words, for the first implantation region 2312 in the source region, no matter what implantation process of PLDD or PDD is adopted at both sides of the first implantation region 2312, it is only necessary to add the N-type implantation region with the above concentration requirement at the corresponding position of the source region after the polysilicon gate 241 of the device is formed. At this time, the source region of the device has a shallow doped region of PDD type or PLDD type, and a third implanted region 233 having a higher concentration than the first shallow doped region but a lower concentration than the first implanted region 2312 is also present. The PDD region is a lightly doped P-type region with a lower concentration than the first implantation region 231, and is formed by increasing a large-angle oblique implantation of the sidewall 243 during the P + implantation in the first implantation region 231; the PLDD region is a P-type lightly doped region implanted after the polysilicon gate 241 is etched and before the formation of the sidewall 243.
It should be noted that, in the above-described magnitude relationship among the concentrations of the first, second, third, and third implanted regions 233, 2312, and 2311, the difference between the higher concentration and the lower concentration should be at least one order of magnitude. For example, in the case of a 5V NMOS device, the concentration of the first and second shallow doped regions in the source region is generally about 18 th power of 10 per cubic centimeter, the concentration of the first and second implanted regions 2312 and 2311 in the source region is generally about 20 th power of 10 per cubic centimeter, and the concentration of the third implanted region 233 in the source region is preferably about 19 th power of 10 per cubic centimeter. Therefore, the first injection region 2312 and the second injection region 2311 of the source end of the device can be ensured not to be influenced, the concentration of the first and second shallow doping regions (especially for the P + injection region in the source end region) can be better covered, and after the third injection region 233 is formed, the resistance value is far smaller than the channel resistance value, so that the on-resistance between the source end and the drain end of the device can be better reduced.
It should be noted that, the above description of the present invention mainly refers to the structure of the source end region of the device, and the structure of the drain end region of the device can be understood by referring to the structure of the source end region or the common knowledge, which is not described in detail herein. Meanwhile, it can be understood that a field oxide layer is further disposed between the source region and the drain region on the upper surface of the epitaxial layer of the device to isolate the source region from the drain region.
The semiconductor device structure shown in fig. 6 to 10 is fabricated through the process steps of fig. 11a to 11f to effectively reduce the on-resistance between the source terminal and the drain terminal of the device, and the following description of the fabrication method is made.
Fig. 11a to 11f are schematic cross-sectional views illustrating stages of a method for manufacturing a source end region structure of an LDMMOS device according to an embodiment of the present invention, and a manufacturing flow of a structure of a semiconductor device (e.g., an NMOS device) according to an embodiment of the present invention is described below with reference to fig. 11a to 11 f.
As shown in fig. 11a, a substrate 210 and an epitaxial layer 220 on top of the substrate 210 are first formed. A small amount of ions are implanted into the semiconductor substrate 210 and the well is pushed down at a high temperature to form a lightly doped N-type region, i.e., the epitaxial layer 220. This step is accomplished using conventional techniques. The substrate 210 is, for example, a silicon substrate.
Further, a plurality of field oxide layers are formed on the surface of the substrate 210. And performing field oxide isolation on the surface of the substrate 210, i.e. forming a plurality of field oxide layers isolated from each other. The field oxide layer is formed by a conventional process, such as depositing an oxide layer on the surface of the substrate 210, then depositing a hard mask, etching by using the mask, finally growing field oxide at a high temperature, and then removing the hard mask. The specific process is not limited in detail.
Further, as shown in fig. 11b, a polysilicon gate 241 and a gate dielectric layer 242 are formed on the surface of the epitaxial layer 220. A polysilicon gate 241 and a gate dielectric layer 242 are formed over the epitaxial layer 220 to control the formation of the channel. Preferably, the gate dielectric layer 242 is a gate oxide layer, and the formation process of the gate dielectric layer 242 and the polysilicon gate 241 is a conventional process, which is not limited herein in detail, and the polysilicon gate 241 is formed by, for example, chemical vapor deposition.
Next, a drain region and a source region spaced apart from each other on the upper portion of the epitaxial layer 220 are formed by photolithography, ion implantation, and the like, and the polysilicon gate 241 and the gate dielectric layer 242 on a portion of the source region (hereinafter referred to as a first implantation region) are removed by an etching process to expose the surface of the first implantation region. That is, the polysilicon gate 241 and the gate dielectric layer 242 partially cover the drain region and the source region. Further, the source terminal region and the drain terminal region are separated by a field oxide layer.
Further, the formation steps of the source end region of the device include fig. 11c to 11 e.
As shown in fig. 11c, a P-type well region 230 is formed on the epitaxial layer 220. P-type doping is performed along the surface of the epitaxial layer 220, and a P-type well region 230 is formed in the upper portion of the epitaxial layer 220.
As shown in fig. 11d, at least one first implant region 2312 and at least one second implant region 2311 located in the P-type well region 230 are formed. Respective N-type and P-type ion implantations are performed in the P-type well region 230 to form at least one first implantation region 2312 and at least one second implantation region 2311.
In this embodiment, the at least one first implantation region 2312 and the at least one second implantation region 2311 are arranged longitudinally along the side of the polysilicon gate 241. Therefore, the space between the polysilicon gates of the devices is reduced, and the on-resistance between the source and the drain of the devices is further reduced.
It should be noted that fig. 11d is a cross-sectional view only illustrating the device, and the structure of at least one first implantation region 2312 and at least one second implantation region 2311 formed in the longitudinal direction along the side of the gate structure can be understood by referring to fig. 6.
Further, the method further includes forming first shallow doped regions in and on both sides of the at least one first implanted region 2312 and forming second shallow doped regions in and on both sides of the at least one second implanted region 2311. N-type and P-type ion implantations of light concentration are performed at corresponding locations in the P-type well region 230 to form a first lightly doped region and a second lightly doped region. The second shallow doping region is an NDD region, and the first shallow doping region is a PDD region or a PLDD region.
As shown in fig. 11e, a third implanted region 233 is formed which is located in the entire source region and covers all of the first implanted region, the second implanted region, the first shallow doped region and the second shallow doped region. Third implanted regions 233 are formed by performing N-type ion implantation at the edges of the first, second, first and second shallow doped regions in the P-type well region 230, with a lower concentration of implanted ions than the first and second implanted regions, but with a higher concentration of implanted ions than the first and second shallow doped regions. Wherein each third implantation region 233 is an N-type implantation region.
Specifically, for the second implantation region 2311 in the source region, when NLDD implantation processes are adopted on both sides thereof, after the polysilicon gate 241 of the device is formed, N-type ion implantation with higher concentration (higher concentration than that of the lightly doped region) is performed at the edges of the first implantation region, the second implantation region, the first lightly doped region and the second lightly doped region in the P-type well region 230, so as to form the third implantation region 233. Or when the NDD implantation process is adopted on both sides of the second implantation region, after the polysilicon gate 241 of the device is formed and before the side wall 243 of the device is formed, N-type ion implantation meeting the preset concentration requirement is performed on the edges of the first implantation region, the second implantation region, the first shallow doping region and the second shallow doping region in the P-type well region 230, so as to form the third implantation region 233. For the first implantation region 2312 in the source region, no matter the implantation process of PLDD or the implantation process of PDD is adopted on both sides thereof, after the polysilicon gate 241 of the device is formed, N-type ion implantation meeting the preset concentration requirement is performed on the edges of the first implantation region, the second implantation region, the first shallow doping region and the second shallow doping region in the P-type well region 230, so as to form the third implantation region 233. After the polysilicon gate 241 is etched, an N-type doped region which is thicker than the PDD region or the PLDD region is directly added to the source end of the device, so that even for the first injection region 2312 in the source end region, N-type regions are formed under the side walls 243 on both sides of the first injection region 2312, and the current collection capability of the source end of the device is improved.
Optionally, the doping impurity for P-type doping is boron, and the implantation impurity for N-type ion implantation is arsenic or phosphorus.
Preferably, the doping concentration of the third implantation region 233 is greater than the doping concentrations of the first and second shallow doping regions and less than the doping concentrations of the first implantation region 2312 and the second implantation region 2311.
Finally, as shown in fig. 11f, sidewalls 243 are formed on the sides of the polysilicon gate 241. Preferably, the sidewall 2432 is formed by depositing a silicon oxide layer by LPTEOS process and then performing a blanket etching process.
It should be noted that, the above description of the present invention mainly refers to the structure of the source end region of the device, and the structure of the drain end region of the device can be understood by referring to the structure of the source end region or the common knowledge, which is not described in detail herein.
It can be understood that the technical solutions described in the embodiments of the present invention are equally applicable to NMOS devices, NLDMOS devices with P-type body-region P-body structures, or PMOS and PLDMOS semiconductor devices. The same applies to processes without epitaxial layers. Meanwhile, the above description is given by taking a process of 180nm as an example, but the same is true for other process nodes.
In summary, after the polysilicon gate of the device is etched, an N-type implantation region (i.e. a third implantation region) with a higher concentration than that of the first lightly doped region and the second lightly doped region beside the source end implantation region (including at least one first implantation region and at least one second implantation region) of the device is directly filled at the source end, the source end injection region is an N + injection region or a P + injection region, the current in the channel can be ensured to directly flow from the drain end to the source end, meanwhile, the N-type injection regions (third injection regions) on two sides of the edge of the P + injection region in the source end injection region can also ensure that the current in the channel does not need to be forced to turn, prevent the current path in the channel from being lengthened and the current concentration phenomenon at the edge of the source end injection region from occurring, and further, the overall effective resistance of the device is reduced, and the source and drain ends of the device have lower on-resistance.
The at least one first injection region and the at least one second injection region are arranged longitudinally along the side face of the grid structure, so that the space of the polysilicon grid of the device is reduced, and the on-resistance between the source and the drain of the device is further reduced.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (8)
1. A semiconductor device, comprising:
the epitaxial layer is formed on the substrate;
a source region, a drain region and a gate structure formed on the epitaxial layer, wherein the gate structure partially covers the source region and the drain region;
a side wall formed on the side surface of the gate structure,
wherein the source end region comprises:
a P-type well region;
at least one first injection region formed in the P-type well region;
at least one second injection region formed outside the at least one first injection region in the P-type well region;
the first shallow doping regions are formed in the at least one first injection region and on two sides of each first injection region, and the doping type of the first shallow doping regions is the same as that of the first injection regions;
second shallow doped regions formed in the at least one second injection region and on two sides of each second injection region, wherein the doping type of the second shallow doped regions is the same as that of the second injection regions;
a third implantation region formed in the entire source region and covering all of the first implantation region, the second implantation region, the first shallow doping region and the second shallow doping region,
wherein the third implantation region is an N-type implantation region,
the doping concentration of the third implantation region is greater than the doping concentrations of the first and second shallow doping regions and less than the doping concentrations of the at least one first and second implantation regions;
the at least one first implant region and the at least one second implant region are arranged longitudinally along a side of the gate structure.
2. The semiconductor device of claim 1, wherein the gate structure comprises: and the polysilicon gate and the gate dielectric layer are formed on the upper surface of the epitaxial layer.
3. The semiconductor device of claim 1, wherein the at least one first implant region is a P + implant region and the at least one second implant region is an N + implant region.
4. The semiconductor device according to claim 3, wherein the first shallow doped region is a PLDD region or a PDD region,
wherein the PDD region is a lightly doped P-type region which is formed by increasing large-angle oblique injection of the side wall during the injection of the first injection region P + and has lower concentration than the first injection region,
the PLDD area is a P-type lightly doped area which is injected after the polysilicon gate is etched and before the side wall is formed.
5. The semiconductor device according to claim 3, wherein the second shallow doped region is an NDD region,
and the NDD region is a lightly doped N-type region which is formed by injecting the side wall in a large-angle oblique manner and is increased during the injection of the second injection region N + and has lower concentration than the second injection region.
6. A method of manufacturing a semiconductor device, comprising:
forming a substrate;
forming an epitaxial layer on the upper part of the substrate;
forming a field oxide layer on the epitaxial layer;
forming a polysilicon gate and a gate dielectric layer which are positioned on the surface of the epitaxial layer and cover part of the source end region;
forming a drain terminal region and a source terminal region which are positioned on the upper part of the epitaxial layer and are mutually separated;
forming a side wall on the side surface of the polysilicon gate,
wherein forming the source end region comprises:
forming a P-type well region on the epitaxial layer;
forming at least one first injection region and at least one second injection region in the P-type well region;
forming first shallow doped regions in the at least one first injection region and on two sides of each first injection region, wherein the doping type of the first shallow doped regions is the same as that of the first injection regions;
forming second shallow doped regions in the at least one second injection region and on two sides of each second injection region, wherein the doping type of the second shallow doped regions is the same as that of the second injection regions;
forming a third implanted region located in the entire source region and covering all of the first implanted region, the second implanted region, the first shallow doped region and the second shallow doped region,
wherein the third implantation region is an N-type implantation region,
the doping concentration of the third implantation region is greater than the doping concentrations of the first and second shallow doping regions and less than the doping concentrations of the at least one first and second implantation regions;
the at least one first implant region and the at least one second implant region are arranged longitudinally along a side of the polysilicon gate.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the at least one first implanted region is a P + implanted region and the at least one second implanted region is an N + implanted region.
8. The method for manufacturing a semiconductor device according to any one of claims 6 to 7, wherein the first shallow doping region is a PLDD region or a PDD region, and the second shallow doping region is an NDD region.
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| US6835627B1 (en) * | 2000-01-10 | 2004-12-28 | Analog Devices, Inc. | Method for forming a DMOS device and a DMOS device |
| CN104037223A (en) * | 2013-03-04 | 2014-09-10 | 上海华虹宏力半导体制造有限公司 | Radio frequency (RF) N-type LDMOS device and manufacture method thereof |
| CN105390543A (en) * | 2014-08-25 | 2016-03-09 | 联发科技股份有限公司 | High-voltage metal-oxide-semiconductor transistor device |
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| US20090283843A1 (en) * | 2008-05-13 | 2009-11-19 | Micrel, Inc. | NMOS Transistor Including Extended NLDD-Drain For Improved Ruggedness |
| TWI635617B (en) * | 2017-05-11 | 2018-09-11 | 立錡科技股份有限公司 | High voltage metal oxide semiconductor device and manufacturing method thereof |
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| US6835627B1 (en) * | 2000-01-10 | 2004-12-28 | Analog Devices, Inc. | Method for forming a DMOS device and a DMOS device |
| CN104037223A (en) * | 2013-03-04 | 2014-09-10 | 上海华虹宏力半导体制造有限公司 | Radio frequency (RF) N-type LDMOS device and manufacture method thereof |
| CN105390543A (en) * | 2014-08-25 | 2016-03-09 | 联发科技股份有限公司 | High-voltage metal-oxide-semiconductor transistor device |
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