CN114023649A - Method for manufacturing super junction device - Google Patents
Method for manufacturing super junction device Download PDFInfo
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- CN114023649A CN114023649A CN202111209250.2A CN202111209250A CN114023649A CN 114023649 A CN114023649 A CN 114023649A CN 202111209250 A CN202111209250 A CN 202111209250A CN 114023649 A CN114023649 A CN 114023649A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The invention discloses a manufacturing method of a super junction device, which comprises the following steps: step one, forming a grid structure, wherein the grid structure is a trench grid, in the forming process of the trench grid, after filling the grid groove with a polysilicon grid, carrying out first planarization to enable the surface of a first epitaxial layer on which the trench grid is formed to be a flat surface, and the width of the grid groove at the leading-out position of the grid structure meets the requirement of forming a contact hole; step two, forming a cap layer on the top of the trench gate under the condition that a gate oxide layer outside the gate trench is reserved; and step three, forming a super junction in the first epitaxial layer with the flat surface and the cap gate and carrying out secondary planarization. The method can prevent the doped impurities of the polysilicon gate from expanding outwards and prevent the gate oxide layer from being damaged on the basis of realizing the full-flat process.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a super junction device.
Background
The super junction is composed of alternately arranged P-type thin layers, also called P-type pillars (pilar), and N-type thin layers, also called N-type pillars, formed in a semiconductor substrate, and the device employing the super junction is a super junction device such as a super junction MOSFET. The technology of reducing the surface electric field (Resurf) in a body by utilizing the charge balance of the P-type thin layer and the N-type thin layer can improve the reverse breakdown voltage of the device and simultaneously keep smaller on-resistance.
The PN-spaced Pillar structure of the super junction is the biggest characteristic of the super junction. The conventional method for manufacturing the p-n spaced pilar structure mainly comprises two methods, one is obtained by multiple times of epitaxy and ion implantation, and the other is manufactured by deep trench etching and Epitaxy (EPI) filling. The latter method is to fabricate the super junction device by a trench process, in which a trench with a certain depth and width is first etched on an N-type doped epitaxial layer on the surface of a semiconductor substrate, such as a silicon substrate, and then a P-type doped silicon epitaxy is filled on the etched trench by an epitaxial Filling (EPI Filling) method.
With the continuous reduction of the step (Pitch) of the super junction, the problem caused by the counter doping (counter dope) formed by the mutual diffusion of the P-type doping and the N-type doping of the P-type column and the N-type column in the thermal process is more and more serious, and the device performance is seriously affected.
FIG. 1 is a schematic diagram of the interdiffusion structure of a conventional super junction; the super junction mainly comprises:
the super junction structure comprises an N-type epitaxial layer 102 formed on the surface of an N-type semiconductor substrate such as a silicon substrate 101, a super junction groove 103 formed in the N-type epitaxial layer 102, grooves corresponding to super junctions are called super junction grooves in the application, a P-type epitaxial layer is filled in the super junction groove 103, P-type columns 104 are formed by the P-type epitaxial layer filled in the super junction groove 103, N-type columns are formed by the N-type epitaxial layer 102 between the P-type columns 104, and the P-type columns 104 and the N-type columns are alternately arranged to form the super junctions. In general, the impurities of the P-type column 104 and the N-type column of the super junction may diffuse into each other in a thermal process, for example, the P-type impurity in the P-type column 104 may diffuse into the N-type column, and a region 105 in fig. 1 corresponds to a region where the P-type impurity in the P-type column 104 diffuses into the N-type column. In an N-type super junction device, an N-type column is usually used as a component of a drift region during conduction, and after the doping concentration of the N-type column is reduced and the width of the N-type column is narrowed, the on-resistance of the device is reduced.
As the step size of the super junction decreases, the ratio of the width range of the super junction affected by the interdiffusion of P-type and N-type impurities generated by the thermal process, such as the width of the region 105 in fig. 1, to the total width of the step, which is the sum of the width and the pitch of the super junction trenches 103, increases, thus seriously affecting the performance of the device.
FIG. 2 is a flow chart of a method for fabricating a conventional super junction device; fig. 2 illustrates a flow of a method for manufacturing a super junction device by using photolithography steps, wherein a Mask (Mask) is used for each photolithography step. The manufacturing method of the prior super junction device comprises the following steps:
and forming a zero layer alignment mark by a first layer of photoetching process. And on the scribing way formed by the alignment mark of the zeroth layer, the alignment mark of the zeroth layer is required to be adopted for alignment in the subsequent second-layer photoetching process corresponding to the formed body region. The zeroth layer alignment mark is defined by a zeroth layer Mask (ZM), and the Mask1 is also used to indicate the zeroth layer Mask.
Second layer photolithography process, body implantation and drive-in. The sampling of the body implant needs to be defined with Mask 2.
And a third layer of photoetching process, and etching and filling the super junction groove. The forming area of the super structure groove needs to be defined by Mask 3.
And a fourth layer photoetching process, and depositing and etching field oxygen. The etched area of the field oxide needs to be defined by Mask 4. The field oxygen is generally formed on the surface of the termination region, which surrounds the periphery of the device cell region, i.e., the current flow region, i.e., the active region. The field oxide of the device cell region needs to be removed before the structure of the device cell region is formed.
And a fifth layer of photoetching process, etching the grid groove and forming a grid oxide layer and a polysilicon grid. In the invention, the trench corresponding to the trench gate is called a gate trench, and the gate trench needs to be defined by Mask 5.
And a sixth layer of photoetching process, polysilicon photoetching and etching, and body region injection and propulsion. The Mask6 is adopted to define the etching area of the polysilicon, and after the polysilicon is photoetched and etched, the extraction structure of the polysilicon gate of the trench gate can be formed. The extraction structure of the polysilicon gate is usually located in the termination region, so the polysilicon of the extraction structure needs to climb over the slope between the field oxide and the active region.
The body implant here does not require lithographic definition.
And a seventh layer of photoetching process, and injecting and advancing a source region. The implantation area of the source region is defined by Mask 7.
And an eighth layer of photoetching process, interlayer film deposition and contact hole (CT) etching, and injection and propulsion of a body region lead-out region. The etching area of the contact hole is defined by Mask 8.
And a ninth layer of photoetching process, and depositing and etching the front metal layer. The etched area of the front metal layer is defined by Mask 9.
A tenth layer of photoetching process, deposition and etching of a Contact PAD (CP); the etched area of the contact pad is defined using Mask 10.
As can be seen from the above, in the conventional method, 10 photolithography processes are required, and many thermal processes are further included after the super junction is formed, so that the super junction formed by the conventional method is easily affected by the thermal processes and generates large interdiffusion, thereby reducing the performance of the device.
In the patent application No. 2020104754925, the applicant proposed an All flat (al flat) planarization process to achieve the goal of reducing the thermal history after the super junction formation and thus reducing the interdiffusion of the impurities of the super junction and thus improving the device performance, while also reducing the number of photolithography process levels. In the method, the polysilicon gate is formed before the super junction structure, so that the surface of the polysilicon gate can be directly exposed after the first planarization, the polysilicon gate is usually a heavily doped structure such As an N-type heavily doped structure, and at the moment, Doping impurities such As phosphorus or arsenic of the polysilicon gate are easy to expand (Out Doping) at high temperature; in addition, the top surfaces of the gate dielectric layers on the two sides of the polysilicon gate are exposed, so that the gate dielectric layers are easily damaged.
An improved method is characterized in that a polysilicon gate is etched in advance to form a groove after the polysilicon gate is formed, then in a second hard mask layer for forming and defining a super junction groove, a bottom oxide layer in an ONO structure of the second hard mask layer is adopted to fill the groove and is used as a cap layer at the top of the polysilicon gate, the bottom oxide layer in the method is usually formed by a thermal oxidation process, the impurities of the polysilicon gate can be outwards expanded by the thermal process in the forming process of the bottom oxide layer, and at the moment, the impurities outwards expanded by the polysilicon gate can not be prevented from being accumulated on the surface of the silicon, so that a good protection effect cannot be formed.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for manufacturing a super junction device, which can reduce the thermal process after the super junction is formed, thereby reducing the mutual diffusion of impurities of the super junction and improving the performance of the device, and simultaneously preventing the doped impurities of a polysilicon gate from expanding outwards and preventing a gate oxide layer from being damaged.
In order to solve the technical problem, the method for manufacturing the super junction device provided by the invention is realized by adopting a full-flat process, so that the forming process of the gate structure is positioned before the forming process of the super junction, and the method comprises the following steps of:
step one, forming the grid structure, wherein the grid structure is a groove grid, and the forming process of the groove grid comprises the following steps:
providing a first epitaxial layer with a first conductivity type, and performing a photolithography process to define a formation region of a gate trench.
And etching the first epitaxial layer to form the gate trench, wherein the width of the gate trench at the leading-out position of the gate structure meets the requirement of forming a contact hole.
And forming a gate oxide layer by adopting a thermal oxidation process, wherein the gate oxide layer is formed on the side surface and the bottom surface of the gate groove and the surface of the first epitaxial layer outside the gate groove at the same time.
Depositing polysilicon to form a polysilicon gate, wherein the polysilicon gate completely fills the gate trench and extends out of the gate trench; the polysilicon gate has a heavily doped structure.
And carrying out first planarization to remove the polysilicon gate outside the gate groove and level the surface of the polysilicon gate in the gate groove with the surface of the first epitaxial layer, wherein the gate oxide layer formed in the gate groove and the polysilicon gate form the groove gate.
Step two, forming a cap layer on the top of the trench gate, including:
and etching the polysilicon gate to form a groove.
Filling a dielectric layer in the groove to form the cap layer, wherein the forming process of the dielectric layer of the cap layer has a thermal process; in the thermal process of the forming process of the dielectric layer of the cap layer, the impurities of the polysilicon gate can expand outwards, and the gate oxide layer outside the gate groove is used for preventing the impurities expanded outwards of the polysilicon gate from accumulating on the surface of the first epitaxial layer.
Performing a first chemical mechanical polishing process stopped on the surface of the first epitaxial layer to remove the gate oxide layer outside the gate trench and to level the top surface of the cap layer with the top surface of the first epitaxial layer; and overlapping the trench gate and the cap layer to form a cap gate.
Step three, performing a super junction forming process, comprising:
and carrying out a photoetching process on the flat surface of the first epitaxial layer on which the cap gate is formed to define a forming area of the super junction groove.
And etching the first epitaxial layer to form a super junction groove.
And filling a second epitaxial layer of a second conductivity type in the super junction trench, forming second conductivity type columns by the second epitaxial layer filled in the super junction trench, forming first conductivity type columns by the first epitaxial layer between the second conductivity type columns, and alternately arranging the first conductivity type columns and the second conductivity type columns to form the super junction.
And carrying out second planarization to enable the surface of the first epitaxial layer formed with the super junction to be a flat surface.
The further improvement is that, in the first step, before the photolithography process for defining the gate trench, a step of forming a first hard mask layer on the surface of the first epitaxial layer is further included, and then, the first hard mask layer is etched first and then the first epitaxial layer is etched to form the gate trench;
and removing the first hard mask layer.
In a further improvement, in the step one, after the gate trench is etched and before the gate oxide layer is formed, a step of rounding the gate trench is further included, and the rounding includes:
forming a first sacrificial oxide layer by adopting a thermal oxidation process;
and removing the first sacrificial oxide layer.
In a further improvement, in the second step, the depth of the groove is
The further improvement is that the dielectric layer of the cap layer is an oxide layer.
In a further improvement, the forming process of the dielectric layer of the cap layer comprises the following steps:
performing a thermal oxidation process to oxidize the top surface of the polysilicon gate to form a first oxide layer;
carrying out a deposition process to form a second oxide layer, wherein the second oxide layer can completely fill the groove and extend to the surface of the gate oxide layer outside the groove;
and simultaneously removing the second oxide layer and the gate oxide layer outside the groove by the first chemical mechanical grinding process, and overlapping the first oxide layer and the second oxide layer remained in the groove to form the cap layer.
In a further improvement, the thickness of the gate oxide layer outside the gate trench is
In a further improvement, the first planarization is realized by a back etching process or a chemical mechanical polishing process.
The further improvement is that the method also comprises the following steps: and forming a body region by adopting an ion implantation and annealing advancing process, wherein the forming region of the body region is defined by photoetching.
In a further improvement, the formation process of the body region is arranged before the third step.
In a further improvement, the forming process of the body region is arranged before the first step, and the method further comprises the step of performing photolithography by using a zeroth layer of photomask and forming a zeroth layer of alignment mark before forming the body region.
In a further improvement, the formation process of the body region is arranged after the first step.
The further improvement is that the method also comprises the following steps: and forming a source region by adopting an ion implantation and annealing advancing process, wherein the forming region of the source region is defined by photoetching, and the source region is self-aligned with the side surface of the corresponding grid structure in the device unit region.
In a further improvement, the forming process of the source region is arranged after the first step and before the third step; or, the forming process of the source region is arranged after the third step.
The further improvement is that after the third step is completed, the method further comprises the following steps:
forming field oxide, an interlayer film and a contact hole, wherein the forming area of the contact hole is defined by photoetching, and the corresponding contact hole is formed at the leading-out position of the grid structure;
forming a front metal layer, and patterning the front metal layer by adopting a photoetching definition and etching process, wherein an electrode formed by the patterned front metal layer comprises a gate electrode structure, and the gate electrode structure is contacted with the polysilicon gate through the contact hole at the leading-out position of the gate electrode structure;
forming a contact pad, wherein a forming area of the contact pad is defined by photoetching;
and finishing the back process of the super junction device.
In a further improvement, the field oxygen has a flat structure without climbing, and the interlayer film covers the flat surface of the field oxygen;
the interlayer film is formed by a USG oxidation process or a TEOS oxidation process.
The further improvement is that in the third step, a second hard mask layer is adopted in the super junction forming process, the second hard mask layer is formed by overlapping a bottom oxide layer, a middle nitride layer and a top oxide layer, and the super junction forming process comprises the following steps when the second hard mask layer is adopted:
forming the second hard mask layer;
defining a forming area of the super junction groove by adopting a photoetching process;
sequentially etching the second hard mask layer and the first epitaxial layer to form the super junction groove;
removing the top oxide layer of the second hard mask, forming a second sacrificial oxide layer by adopting a thermal oxidation process, and then removing the second sacrificial oxide layer;
removing the intermediate nitride layer of the second hard mask;
carrying out epitaxial filling in the super junction groove to form the second epitaxial layer;
performing a chemical mechanical polishing process on the second epitaxial layer to achieve the second planarization, so that the second epitaxial layer is only filled in the super junction trench;
and removing the bottom oxide layer of the second hard mask layer completely or only partially.
In a further improvement, the first epitaxial layer is formed on a semiconductor substrate, and the back process of the super junction device comprises:
thinning the back of the semiconductor substrate;
directly taking the thinned semiconductor substrate as the drain region, or performing back injection of first conductivity type heavy doping on the thinned semiconductor substrate to form the drain region;
and forming a back metal layer on the back of the drain region.
The further improvement is that the first conductive type is N type, the second conductive type is P type, and the polysilicon gate has an N type heavily doped structure.
In a further improvement, the doping impurities of the polysilicon gate comprise phosphorus or arsenic, and the doping concentration is 1e20cm-3The above.
The invention can form the cap layer at the top of the groove gate under the condition that the gate oxide outside the gate groove is exposed after the first planarization of the gate structure is finished on the basis of the full flat process, the cap layer forming process comprises the steps of etching the polysilicon gate to form a groove and filling the groove with a dielectric layer, a thermal process can be realized when the groove is filled with the dielectric layer, the thermal process has an outward expansion effect on the polysilicon gate, but because the surface of the first epitaxial layer outside the gate groove is covered by the gate oxide, a protection effect can be formed, and thus the outward expansion impurities of the polysilicon gate can be prevented from being accumulated on the surface of the first epitaxial layer.
After the cap layer is formed, the trench gate at the bottom can be protected from the top on the cap layer, so that the doped impurities of the polysilicon gate can be prevented from expanding outwards, and the gate oxide layer can be prevented from being damaged.
The full-flat process of the invention can reduce the thermal process after the super junction is formed, thereby reducing the mutual diffusion of impurities of the super junction and improving the performance of the device.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of the structure of the interdiffusion of a conventional superjunction;
FIG. 2 is a flow chart of a method of fabricating a prior art super junction device;
FIG. 3 is a flow chart of a method of fabricating a super junction device according to an embodiment of the present invention;
fig. 4A-4N are schematic views of device structures in various steps of a method for manufacturing a super junction device according to an embodiment of the present invention.
Detailed Description
FIG. 3 is a flow chart of a method of fabricating a super junction device according to an embodiment of the present invention; FIG. 3 is a diagram illustrating a photolithography process level, where a photolithography process level includes a plurality of specific process steps and a photolithography process level only performs a photolithography process corresponding to a reticle; as shown in fig. 4A to 4N, which are schematic device structure diagrams in each step of the method for manufacturing a super junction device according to the embodiment of the present invention, the method for manufacturing a super junction device according to the embodiment of the present invention is implemented by using an all-flat process, and a process for forming a gate structure is located before a process for forming a super junction, and includes the following steps:
step one, as shown in fig. 4A, forming the gate structure, where the gate structure is a trench gate, and the trench gate forming process includes:
a first epitaxial layer 2 having a first conductivity type is provided, and a photolithography process is performed to define a formation region of the gate trench 201.
As shown in fig. 4B, the first epitaxial layer 2 is etched to form the gate trench 201, and the width of the gate trench 201 at the leading position of the gate structure meets the requirement of forming the contact hole 10.
In the embodiment of the present invention, before performing the photolithography process for defining the gate trench 201, the method further includes a step of forming a first hard mask layer on the surface of the first epitaxial layer 2, and then etching the first hard mask layer first and then etching the first epitaxial layer 2 to form the gate trench 201;
and removing the first hard mask layer.
The method also comprises the step of rounding the gate trench 201 after the etching of the gate trench 201 is completed and before the subsequent formation of the gate oxide layer 3, wherein the rounding comprises the following steps:
forming a first sacrificial oxide layer by adopting a thermal oxidation process;
and removing the first sacrificial oxide layer.
And forming a gate oxide layer 3 by adopting a thermal oxidation process, wherein the gate oxide layer 3 is formed on the side surface and the bottom surface of the gate trench 201 and the surface of the first epitaxial layer 2 outside the gate trench 201 at the same time.
As shown in fig. 4C, polysilicon deposition is performed to form a polysilicon gate 4, where the polysilicon gate 4 completely fills the gate trench 201 and extends out of the gate trench 201; the polysilicon gate 4 has a heavily doped structure.
And carrying out first planarization to remove the polysilicon gate 4 outside the gate trench 201, and to level the surface of the polysilicon gate 4 in the gate trench 201 with the surface of the first epitaxial layer 2, wherein the gate oxide layer 3 and the polysilicon gate 4 formed in the gate trench 201 form the trench gate.
The first planarization is realized by a back etching process or a chemical mechanical polishing process.
In the embodiment of the present invention, the first conductivity type is an N-type conductivity, the second conductivity type is a P-type conductivity, and the polysilicon gate 4 has an N-type heavily doped structure. As shown in fig. 4A, the first epitaxial layer 2 is also denoted by nepi, the first epitaxial layer 2 is formed on a heavily N-doped semiconductor substrate 1, the semiconductor substrate 1 is typically a silicon substrate, the first epitaxial layer 2 is typically a silicon epitaxial layer, and the semiconductor substrate 1 is also denoted by N +.
The doping impurities of the polysilicon gate 4 comprise phosphorus or arsenic, and the doping concentration is 1e20cm-3The above.
Step two, forming a cap layer 302 on the top of the trench gate, including:
fig. 4C1 is an enlarged view of one of the gate structures in fig. 4C, and as shown in fig. 4C1, the polysilicon gate 4 is etched to form a groove 301.
As shown in fig. 4C2, the capping layer 302 is formed by filling a dielectric layer in the groove 301, and the formation process of the dielectric layer of the capping layer 302 has a thermal process; in the thermal process of the formation process of the dielectric layer of the cap layer 302, the impurities of the polysilicon gate 4 may be expanded outwards, and the gate oxide layer 3 outside the gate trench 201 is used for preventing the expanded impurities of the polysilicon gate 4 from accumulating on the surface of the first epitaxial layer 2. The thickness of the gate oxide layer 3 outside the gate trench 201 is
As shown in fig. 4D, performing a first chemical mechanical polishing process stopping on the surface of the first epitaxial layer 2 to remove the gate oxide layer 3 outside the gate trench 201 and to level the top surface of the cap layer 302 with the top surface of the first epitaxial layer 2; the trench gate and the cap layer 302 are stacked to form a cap gate 4 a. Fig. 4D1 is an enlarged view of one of the gate structures in fig. 4D, and fig. 4D1 shows a layered structure of the cap gate 4a, i.e., a stacked structure of the polysilicon gate 4 and the cap layer 302.
The process of forming the trench gate and the cap layer 302 corresponds to the first photolithography process in fig. 3.
In the embodiment of the present invention, the depth of the groove 301 is
The dielectric layer of the cap layer 302 is an oxide layer.
The forming process of the dielectric layer of the cap layer 302 includes:
performing a thermal oxidation process to oxidize the top surface of the polysilicon gate 4 to form a first oxide layer;
carrying out a deposition process to form a second oxide layer, wherein the second oxide layer can completely fill the groove 301 and extend to the surface of the gate oxide layer 3 outside the groove 301;
the first chemical mechanical polishing process simultaneously removes the second oxide layer and the gate oxide layer 3 outside the groove 301, and the cap layer 302 is formed by overlapping the first oxide layer and the second oxide layer remained in the groove 301.
Further comprising the steps of: as shown in fig. 4E, the body region 5 is formed by ion implantation and an annealing advancement process, and a formation region of the body region 5 is defined by photolithography. The formation step of the body region 5 corresponds to the second level lithography process in fig. 3. Compared with the prior art shown in fig. 2, in the embodiment of the present invention, since the gate structure forming process is performed before the body region 5 forming process, the zero-th layer alignment mark forming process shown in fig. 2 is not required, which can save a layer of photomask and corresponding photolithography process.
Step three, performing a super junction forming process, comprising:
as shown in fig. 4F, a photolithography process is performed on the planar surface of the first epitaxial layer 2 on which the cap gate 4a is formed to define a formation region of the super junction trench 205.
As shown in fig. 4F, the first epitaxial layer 2 is etched to form a super junction trench 205.
As shown in fig. 4G, the super junction trench 205 is filled with a second epitaxial layer 7 of the second conductivity type; second conductive type columns are formed by the second epitaxial layer 7 filled in the super junction grooves 205, first conductive type columns are formed by the first epitaxial layer 2 between the second conductive type columns, and the first conductive type columns and the second conductive type columns are alternately arranged to form the super junctions.
As shown in fig. 4H, the second planarization is performed to make the surface of the first epitaxial layer 2 on which the super junction is formed a flat surface.
Preferably, a second hard mask layer is adopted in the super junction forming process, and the super junction forming process includes the following steps when the second hard mask layer is adopted:
as shown in fig. 4F, the second hard mask layer is formed by stacking a bottom oxide layer 202, an intermediate nitride layer 203, and a top oxide layer 204.
The formation region of the super junction trench 205 is defined by a photolithography process.
And etching the second hard mask layer and the first epitaxial layer 2 in sequence to form the super junction trench 205.
As shown in fig. 4G, the top oxide layer 204 of the second hard mask is removed, a thermal oxidation process is used to form a second sacrificial oxide layer, and then the second sacrificial oxide layer is removed.
As shown in fig. 4G, the intermediate nitride layer 203 of the second hard mask is removed.
As shown in fig. 4G, the second epitaxial layer 7 is formed by epitaxial filling in the super junction trench 205.
As shown in fig. 4H, the second planarization is performed by performing a chemical mechanical polishing process on the second epitaxial layer 7, so that the second epitaxial layer 7 is only filled in the super junction trench 205. Fig. 4H1 is an enlarged view of one of the gate structures in fig. 4H, and it can be seen that the polysilicon gate 4 is always sealed by the capping layer 302 during the process of forming the super junction structure.
The bottom oxide layer 202 of the second hard mask layer is removed entirely or only partially.
Step three corresponds to the third layer photolithography process in fig. 3.
Further comprising the steps of: as shown in fig. 4I, an ion implantation and an annealing advancement process are used to form a source region 6, a formation region of the source region 6 is defined by photolithography, and the source region 6 and the corresponding side surface of the gate structure in the device cell region are self-aligned. The source region 6 is not formed in the termination region, so the source region 6 needs to be defined by using a layer of photomask, and the forming process of the source region 6 corresponds to the fourth layer of photolithography process in fig. 3.
As shown in fig. 4J, field oxygen 8 is formed. In the embodiment of the present invention, after the field oxide 8 is formed, the field oxide 8 does not need to be etched to open the device unit region, so a mask can be saved in the process for forming the field oxide 8, and in fig. 3, the process for forming the field oxide 8 is still classified into the fourth layer photolithography process in fig. 3. In addition, the field oxide 8 is not patterned by the photolithography process and the etching process, so that the field oxide 8 has a flat structure without climbing.
As shown in fig. 4K, an interlayer film 9 is formed. The interlayer film 9 covers the flat surface of the field oxide 8, and the field oxide 8 has a flat structure without climbing, so that a BPSG (binary pattern generator) reflow process required by the planarization of the interlayer film 9 is eliminated in the interlayer film 9 forming process, and the heat process can be saved by eliminating the BPSG reflow process. Since the BPSG reflow process is not required, the interlayer film 9 does not need to be formed by the BPSG oxidation process, and in the embodiment of the present invention, the interlayer film 9 is formed by the USG oxidation process or the TEOS oxidation process. In fig. 3, the process of forming the interlayer film 9 is still classified into the fourth photolithography process in fig. 3.
A contact hole 10, a forming region of the contact hole 10 being defined by photolithography. The forming process of the contact hole 10 comprises the following sub-steps:
as shown in fig. 4K, a photolithography process is used to define a formation region of the contact hole 10, and then the interlayer film 9 and the field oxide 8 are sequentially etched to form an opening 206 of the contact hole 10.
In fig. 4K, the openings 206 are only located on the top of the corresponding source regions 6 and body regions 5 in the device cell region. An opening 206a having a width larger than that of the opening 206 is further formed at the periphery of the device cell region, and the bottom of the opening 206a opens the corresponding second conductive type pillar and the body region 5.
In fig. 4K, the opening 206 of the contact hole 10 is not formed at the top of the polysilicon gate 4 of the gate structure of the device cell region. As shown in fig. 4L, fig. 4L shows the lead-out position region of the gate structure, and it can be seen that the width of the gate trench 201 at the lead-out position of the gate structure meets the requirement of forming the contact hole 10, so in fig. 4L, an opening 206 of the contact hole 10 is formed at the top of the polysilicon gate 4 at the lead-out position of the gate structure.
Generally, after the openings 206 and 206a are formed, a step of performing a body region extraction region implantation of heavily doped ions of the second conductivity type is further included, and the body region extraction region implantation forms a body region extraction region at the bottom of the openings 206 and 206a corresponding to the source regions 6 so as to realize the subsequent ohmic contact between the contact holes 10 and the body regions 5.
Then, the opening 206 and the opening 206a are filled with a metal such as tungsten to form the contact hole 10.
The above-described process of forming the contact hole 10 corresponds to the fifth layer photolithography process in fig. 3.
As shown in fig. 4M, a front metal layer 11 is formed, and the front metal layer 11 is patterned by using a lithography definition and etching process. The patterned front-side metal layer 11 typically forms a source electrode structure connected to the source regions 6 and the body regions 5 and a gate electrode structure connected to the polysilicon gate 4. The gate electrode structure is in contact with the polysilicon gate 4 through the contact hole 10 at the lead-out position of the gate electrode structure.
The formation process of the front metal layer 11 corresponds to the sixth photolithography process in fig. 3.
As shown in fig. 4M, a contact pad is formed, and a formation region of the contact pad is defined by photolithography. The contact pad is typically composed of the topmost front side metal layer 11. The contact pad includes a source electrode pad leading out the source electrode structure and a gate electrode pad leading out the gate electrode structure. The formation process of the contact pad corresponds to the seventh photolithography process in fig. 3.
And finishing the back process of the super junction device as shown in fig. 4N. The back process of the super junction device comprises the following steps:
and thinning the back of the semiconductor substrate 1.
Directly using the thinned semiconductor substrate 1 as the drain region, and then requiring the semiconductor substrate 1 to have the first conductivity type heavy doping. Can also be: and performing back injection of the first conductive type heavy doping on the thinned semiconductor substrate to form a drain region.
And forming a back metal layer 12 on the back of the drain region. In the embodiment of the present invention, the back process of the super junction device does not need to adopt the photolithography definition, so the back process of the super junction device is included in the seventh photolithography process in fig. 3.
In the embodiment of the invention, the super junction device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type. In other embodiments can also be: the super junction device is a P-type device, the first conduction type is a P-type device, and the second conduction type is an N-type device.
In the embodiment of the invention, the leading-out of the grid structure of the super junction device is also set to be led out through the contact hole at the top of the trench grid structure, so that the grid structure can be formed by adopting a trench grid process and can be well flattened; the characteristic of realizing flatness after the grid structure is formed enables the groove grid process of the invention to be conveniently arranged before the super junction forming process, and to be conveniently flattened after the super junction is formed, finally, the full flat process can be realized, and the process difficulty of the device can be greatly reduced; the trench gate process is arranged before the super junction forming process, so that a plurality of unexpected technical effects can be brought, and the technical effects comprise:
the method can eliminate the influence of the thermal process of the forming process of the grid structure on the super junction, the thermal process of the forming process of the grid structure mainly comprises the forming process of the sacrificial oxide layer and the forming process of the grid oxide layer 3, the thermal process of the grid structure is large, and the influence on the mutual diffusion of PN impurities of the super junction can be greatly reduced, so that the technical problem of the invention can be well solved, and finally the performance of the device is improved.
Secondly, because the forming process of the gate structure is positioned before the forming process of the super junction, the adverse effect of the thermal process on the super junction is not required to be considered in the forming process of the gate structure, so that the use of the thermal process of the forming process of the gate structure is not limited, and the gate structure with better quality can be obtained.
Thirdly, in the prior art, two times of body region 5 implantation and propulsion are adopted, and one time of body region 5 implantation and propulsion is arranged after the gate structure is formed, so that the thermal process of the next time of body region 5 propulsion still has adverse effects on the super junction, however, in the embodiment of the invention, the gate structure forming process is arranged before the super junction forming process, and the body region 5 implantation and propulsion process are both arranged before the super junction forming process, so that the embodiment of the invention can also prevent the adverse effects of the thermal process of body region 5 propulsion on the super junction, and further improve the performance of the device.
Thirdly, because the forming process of the grid structure is placed before the forming process of the super junction, the surface of the device unit area is originally exposed when the grid structure is formed, and the forming and etching processes of the field oxide 8 are not needed to expose the device unit area, so that the photoetching defining process of the field oxide 8 can be saved, and a layer of photomask related to the etching of the field oxide 8 can be saved.
Since the field oxide 8 on the top of the device unit region is not required to be removed, the edge of the device unit region and the terminal region is not provided with a climbing structure of the field oxide 8, the surface of the whole field oxide 8 is in a flat structure, and the interlayer film 9 is also in a flat structure after being formed on the field oxide 8, so that the interlayer film 9 is not required to be planarized by adopting a BPSG (band gap glass) reflow process, the adverse effect of the thermal process of the BPSG reflow process on the super junction can be further reduced, and the performance of the device can be further improved.
In addition, in the embodiment of the invention, because the gate structure is formed before the formation process of the super junction, the formation process of the source region 6 including the implantation and the annealing propulsion process can also be arranged before the formation process of the super junction, so that the adverse effect of the thermal process of the propulsion process of the source region 6 on the super junction can be further reduced, and the performance of the device can be further improved.
In the embodiment of the present invention, by setting the process sequence of the gate structure, in addition to obtaining the beneficial effects related to the reduction of the thermal process of the super junction, the embodiment of the present invention can also save the photomask, and the following specific descriptions are provided:
first, the above-described photolithographic definition process of the field oxide 8 can be saved.
Secondly, when a grid structure is formed on the wafer firstly and then the body region 5 is formed, the photoetching of the body region 5 can be directly aligned by adopting the grid structure without adopting a zero-level alignment mark, so that the zero-level photomask can be saved.
In the embodiment of the invention, the contact hole 10 can be directly formed at the top of the leading-out position of the gate structure to lead out the gate structure, the polysilicon gate 4 of the gate structure does not need to extend to the top of the field oxide 8 through climbing, and then the contact hole 10 is formed on the polysilicon at the top of the field oxide 8 to lead out the gate structure, so that the polysilicon climbing to the top of the field oxide 8 does not need to be defined by photoetching by adopting a photoetching process, and a photomask defined by photoetching of the polysilicon can be saved.
Therefore, the embodiment of the invention can save a plurality of layers of photomasks and can greatly reduce the process cost.
On the basis of the full-flat process, after the first planarization of the gate structure is completed, the step of forming the cap layer 302 at the top of the trench gate is performed under the condition that the gate oxide layer 3 outside the gate trench 201 is exposed, the cap layer 302 forming process comprises the steps of etching the polysilicon gate 4 to form a groove 301 and filling the groove 301 with a dielectric layer, a thermal process is performed when the groove 301 is filled with the dielectric layer, the thermal process has an outward expansion effect on the polysilicon gate 4, but because the surface of the first epitaxial layer 2 outside the gate trench 201 is covered by the gate oxide layer 3, a protection effect can be formed, and therefore, the outward expansion impurities of the polysilicon gate 4 can be prevented from being accumulated on the surface of the first epitaxial layer 2.
After the cap layer 302 is formed, the trench gate at the bottom can be protected from the top by the cap layer 302, which can prevent the doped impurities of the polysilicon gate 4 from expanding outwards and prevent the gate oxide layer 3 from being damaged.
The full-flat process of the embodiment of the invention can reduce the thermal process after the super junction is formed, thereby reducing the mutual diffusion of impurities of the super junction and improving the performance of the device.
Further embodiments are obtained by applying the phase-strain transduction to the method of the embodiments of the present invention, for example with the following transformations:
in an alternative embodiment, the process for forming the body region 5 is performed before the first step, and further includes a step of performing photolithography using a zero-level mask and forming a zero-level alignment mark before forming the body region 5.
In an alternative embodiment, the formation process of the source region 6 is arranged after step one and before step three.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (20)
1. A manufacturing method of a super junction device is characterized in that the manufacturing method is realized by adopting a full flat process, and a forming process of a grid structure is positioned before the forming process of a super junction, and the manufacturing method comprises the following steps:
step one, forming the grid structure, wherein the grid structure is a groove grid, and the forming process of the groove grid comprises the following steps:
providing a first epitaxial layer with a first conductivity type, and defining a forming region of a grid groove by a photoetching process;
etching the first epitaxial layer to form the gate trench, wherein the width of the gate trench at the leading-out position of the gate structure meets the requirement of forming a contact hole;
forming a gate oxide layer by adopting a thermal oxidation process, wherein the gate oxide layer is formed on the side surface and the bottom surface of the gate trench and the surface of the first epitaxial layer outside the gate trench at the same time;
depositing polysilicon to form a polysilicon gate, wherein the polysilicon gate completely fills the gate trench and extends out of the gate trench; the polysilicon gate is provided with a heavy doping structure;
carrying out first planarization to remove the polysilicon gate outside the gate trench and level the surface of the polysilicon gate in the gate trench with the surface of the first epitaxial layer, wherein the gate oxide layer formed in the gate trench and the polysilicon gate form the trench gate;
step two, forming a cap layer on the top of the trench gate, including:
etching the polysilicon gate to form a groove;
filling a dielectric layer in the groove to form the cap layer, wherein the forming process of the dielectric layer of the cap layer has a thermal process; in the thermal process of the forming process of the dielectric layer of the cap layer, impurities of the polysilicon gate can expand outwards, and the gate oxide layer outside the gate groove is used for preventing the impurities of the polysilicon gate expanding outwards from accumulating on the surface of the first epitaxial layer;
performing a first chemical mechanical polishing process stopped on the surface of the first epitaxial layer to remove the gate oxide layer outside the gate trench and to level the top surface of the cap layer with the top surface of the first epitaxial layer; forming a cap gate by overlapping the trench gate and the cap layer;
step three, performing a super junction forming process, comprising:
carrying out a photoetching process on the flat surface of the first epitaxial layer on which the cap gate is formed to define a forming area of a super junction groove;
etching the first epitaxial layer to form a super junction groove;
filling a second epitaxial layer of a second conductivity type in the super junction trench, forming a second conductivity type column by the second epitaxial layer filled in the super junction trench, forming a first conductivity type column by the first epitaxial layer between the second conductivity type columns, and alternately arranging the first conductivity type column and the second conductivity type column to form the super junction;
and carrying out second planarization to enable the surface of the first epitaxial layer formed with the super junction to be a flat surface.
2. The method of manufacturing a super junction device of claim 1, wherein: in the first step, before the photoetching process for defining the grid groove, a step of forming a first hard mask layer on the surface of the first epitaxial layer is also included, and then the first hard mask layer is etched firstly and then the first epitaxial layer is etched to form the grid groove;
and removing the first hard mask layer.
3. The method of manufacturing a super junction device of claim 1, wherein: in the first step, the method further comprises a step of rounding the gate trench after the gate trench is etched and before the gate oxide layer is formed, wherein the rounding comprises the following steps:
forming a first sacrificial oxide layer by adopting a thermal oxidation process;
and removing the first sacrificial oxide layer.
4. The method of manufacturing a super junction device of claim 1, wherein: in the second step, the depth of the groove is
5. The method of manufacturing a super junction device of claim 4, wherein: the dielectric layer of the cap layer is an oxide layer.
6. The method of manufacturing a super junction device of claim 5, wherein: the forming process of the dielectric layer of the cap layer comprises the following steps:
performing a thermal oxidation process to oxidize the top surface of the polysilicon gate to form a first oxide layer;
carrying out a deposition process to form a second oxide layer, wherein the second oxide layer can completely fill the groove and extend to the surface of the gate oxide layer outside the groove;
and simultaneously removing the second oxide layer and the gate oxide layer outside the groove by the first chemical mechanical grinding process, and overlapping the first oxide layer and the second oxide layer remained in the groove to form the cap layer.
7. The method of manufacturing a super junction device of claim 1, wherein: the thickness of the gate oxide layer outside the gate trench is
8. The method of manufacturing a super junction device of claim 1, wherein: the first planarization is realized by a back etching process or a chemical mechanical polishing process.
9. The method of manufacturing a super junction device of claim 1, further comprising the steps of: and forming a body region by adopting an ion implantation and annealing advancing process, wherein the forming region of the body region is defined by photoetching.
10. The method of manufacturing a super junction device of claim 9, wherein: and the forming process of the body region is arranged before the third step.
11. The method of manufacturing a super junction device of claim 10, wherein: the forming process of the body region is arranged before the first step, and the forming process further comprises the steps of carrying out photoetching by using a zero-layer photomask and forming a zero-layer alignment mark before the body region is formed.
12. The method of manufacturing a super junction device of claim 10, wherein: and the formation process of the body region is arranged after the first step.
13. The method of manufacturing a super junction device of claim 1, further comprising the steps of: and forming a source region by adopting an ion implantation and annealing advancing process, wherein the forming region of the source region is defined by photoetching, and the source region is self-aligned with the side surface of the corresponding grid structure in the device unit region.
14. The method of manufacturing a super junction device of claim 13, wherein: the forming process of the source region is arranged after the first step and before the third step; or, the forming process of the source region is arranged after the third step.
15. The method of manufacturing a super junction device of claim 1, wherein: after the third step is completed, the method further comprises the following steps:
forming field oxide, an interlayer film and a contact hole, wherein the forming area of the contact hole is defined by photoetching, and the corresponding contact hole is formed at the leading-out position of the grid structure;
forming a front metal layer, and patterning the front metal layer by adopting a photoetching definition and etching process, wherein an electrode formed by the patterned front metal layer comprises a gate electrode structure, and the gate electrode structure is contacted with the polysilicon gate through the contact hole at the leading-out position of the gate electrode structure;
forming a contact pad, wherein a forming area of the contact pad is defined by photoetching;
and finishing the back process of the super junction device.
16. The method of manufacturing a super junction device of claim 15, wherein: the field oxygen has a flat structure without climbing, and the interlayer film covers the flat surface of the field oxygen;
the interlayer film is formed by a USG oxidation process or a TEOS oxidation process.
17. The method of manufacturing a super junction device of claim 1, wherein: in the third step, a second hard mask layer is adopted in the super junction forming process, the second hard mask layer is formed by overlapping a bottom oxide layer, a middle nitride layer and a top oxide layer, and the super junction forming process comprises the following steps when the second hard mask layer is adopted:
forming the second hard mask layer;
defining a forming area of the super junction groove by adopting a photoetching process;
sequentially etching the second hard mask layer and the first epitaxial layer to form the super junction groove;
removing the top oxide layer of the second hard mask, forming a second sacrificial oxide layer by adopting a thermal oxidation process, and then removing the second sacrificial oxide layer;
removing the intermediate nitride layer of the second hard mask;
carrying out epitaxial filling in the super junction groove to form the second epitaxial layer;
performing a chemical mechanical polishing process on the second epitaxial layer to achieve the second planarization, so that the second epitaxial layer is only filled in the super junction trench;
and removing the bottom oxide layer of the second hard mask layer completely or only partially.
18. The method of manufacturing a super junction device of claim 15, wherein: the first epitaxial layer is formed on the semiconductor substrate, and the back process of the super junction device comprises the following steps:
thinning the back of the semiconductor substrate;
directly taking the thinned semiconductor substrate as the drain region, or performing back injection of first conductivity type heavy doping on the thinned semiconductor substrate to form the drain region;
and forming a back metal layer on the back of the drain region.
19. The method of manufacturing a super junction device of claim 1, wherein: the first conductive type is N type, the second conductive type is P type, and the polysilicon gate is provided with an N type heavily doped structure.
20. The method of manufacturing a super junction device of claim 19, wherein: the doping impurities of the polysilicon gate comprise phosphorus or arsenic, and the doping concentration is 1e20cm-3The above.
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| CN111900090A (en) * | 2020-08-26 | 2020-11-06 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction device |
| CN111900089A (en) * | 2020-08-26 | 2020-11-06 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction device |
| CN111986997A (en) * | 2020-08-26 | 2020-11-24 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116646251A (en) * | 2023-07-27 | 2023-08-25 | 北京智芯微电子科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
| CN116646251B (en) * | 2023-07-27 | 2023-09-19 | 北京智芯微电子科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
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