CN115579326A - Method for manufacturing semiconductor integrated circuit - Google Patents
Method for manufacturing semiconductor integrated circuit Download PDFInfo
- Publication number
- CN115579326A CN115579326A CN202211421804.XA CN202211421804A CN115579326A CN 115579326 A CN115579326 A CN 115579326A CN 202211421804 A CN202211421804 A CN 202211421804A CN 115579326 A CN115579326 A CN 115579326A
- Authority
- CN
- China
- Prior art keywords
- polysilicon
- silicon oxide
- ion implantation
- doped
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 67
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 103
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 83
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 10
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000000227 grinding Methods 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 163
- 229920005591 polysilicon Polymers 0.000 claims description 150
- 238000005468 ion implantation Methods 0.000 claims description 72
- 238000000137 annealing Methods 0.000 claims description 18
- 239000002019 doping agent Substances 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 229910052796 boron Inorganic materials 0.000 claims description 14
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 12
- 229910052698 phosphorus Inorganic materials 0.000 claims description 12
- 239000011574 phosphorus Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 230000036961 partial effect Effects 0.000 claims description 2
- 238000005260 corrosion Methods 0.000 claims 1
- 230000007797 corrosion Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 25
- 238000010586 diagram Methods 0.000 description 13
- 238000002955 isolation Methods 0.000 description 5
- 230000001413 cellular effect Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for manufacturing a semiconductor integrated circuit, which comprises the following steps: growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily-doped semiconductor substrate and a lightly-doped epitaxial layer, and the hard mask dielectric layer comprises first silicon oxide, silicon nitride and second silicon dioxide; forming a first groove and a second groove on the semiconductor substrate by using the hard mask dielectric layer as a barrier layer and adopting a photoetching and etching process; depositing third silicon oxide; removing the second silicon oxide and the third silicon oxide which are higher than the upper surface of the silicon nitride by adopting a chemical mechanical grinding process, and then removing the silicon nitride; the manufacturing method of the semiconductor integrated circuit disclosed by the invention has the advantages of completely eliminating the high step problem existing in the traditional manufacturing method and the like.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing, and more particularly, to a method for manufacturing a semiconductor integrated circuit.
Background
With the technical development of semiconductor integrated circuits, people have higher requirements on the performance of semiconductor devices, however, the electrostatic discharge phenomenon occurs in various links of packaging, transportation, use and the like of the semiconductor integrated circuits, so that the devices are broken down by static electricity to fail, and therefore, the electrostatic protection function of the semiconductor devices is very important.
For trench type semiconductor devices, such as trench MOSFET, SGT, IGBT, the typical fabrication method for the self-electrostatic protection function is to fabricate back-to-back diodes in the trench type semiconductor device. Taking a trench MOSFET as an example, a relatively thick dielectric layer is usually fabricated outside a cell region of the MOSFET, and then a polysilicon diode is fabricated above the dielectric layer, which is characterized by relatively simple process structure and the disadvantage of large height difference, i.e. very high steps, between the cell region and the polysilicon diode region, thereby increasing the difficulty of planarization process and contact hole process and reducing the integration level of the device.
Because of the above problems, a new manufacturing method is provided, that is, a polysilicon diode is manufactured in a trench, the top of the polysilicon diode is substantially equal to a silicon plane, the problem of height difference is solved, and the integration level of the device is greatly improved. Here, taking the granted patent 201310347156.2 as an example, there are at least the following problems:
(1) In patent claim 1, "silicon dioxide is deposited and etched back in the trench, and a thick gate oxide is formed at the bottom of the trench and used as an insulating layer between the electrostatic discharge protection circuit and the trench-type power device, so that the electrostatic discharge protection circuit can be placed in the trench, and the thickness of the thick gate oxide is 3000 to 4000 angstroms, this step cannot be realized in the practical process, because the area of the electrostatic discharge protection circuit usually exceeds 100 x 100 micrometers, that is, the size of the trench in which the electrostatic discharge protection circuit is located is greater than 100 x 100 micrometers, and after the silicon dioxide is deposited, the thickness of the silicon dioxide in the region outside the trench and the thickness of the silicon dioxide in the region at the bottom of the trench are the same, and the etching back is performed according to the step, so that all the silicon dioxide outside the trench cannot be selectively removed, and at the same time 3000 to 4000 angstroms of silicon dioxide remain in the trench.
(2) In the patent claim 1, "depositing undoped polysilicon, performing first poly implantation, coating photoresist on an area where an electrostatic discharge protection circuit is to be formed, performing second poly implantation, etching back to remove polysilicon above a trench, and forming gate polysilicon and electrostatic discharge protection circuit polysilicon respectively", which corresponds to the schematic diagrams 3C to 3F, there is a structural problem in the practical process, because boron ions of the second poly implantation are only distributed on the surface layer of polysilicon, in the step of etching back to remove polysilicon above the trench, polysilicon above the trench in the area not covered by the photoresist is all etched away (corresponding to the schematic diagram 3F), that is, the polysilicon surface layer doped with boron ions is all etched away, and thus the doping purpose of the gate polysilicon cannot be achieved, that is, the gate polysilicon remaining in the trench is not doped at all, and the MOSFET cannot work normally.
(3) In the patent claim 1, "back-etching to remove the polysilicon above the trench and form the gate polysilicon and the electrostatic discharge protection circuit polysilicon respectively", corresponding to fig. 3F, the electrostatic discharge protection circuit polysilicon forms a very high step in the trench, that is, the polysilicon surface in the trench has a very large height difference with the surface of the insulating layer, that is, this manufacturing method does not fundamentally solve the problem of height difference, but only transfers the step from the outside of the trench to the inside of the trench, which still has a very large difficulty for the subsequent planarization process and still has a metal residue risk at the step position.
In summary, the invention patent 201310347156.2 has no practical significance in practical production, and similarly, other published technical data and patent information have some problems, and the problem of high step in the manufacturing method of the trench type semiconductor device with the electrostatic protection function cannot be fundamentally solved.
In order to solve the problems, the scheme provides a novel manufacturing method.
Disclosure of Invention
The invention provides a method for manufacturing a semiconductor integrated circuit, which has the advantages of completely eliminating the high step problem existing in the traditional manufacturing method and the like and solves the high step problem existing in the original manufacturing method of a groove type semiconductor device.
According to the manufacturing method of the semiconductor integrated circuit provided by the embodiment of the application, the method comprises the following steps:
growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped semiconductor substrate and a lightly doped epitaxial layer, and the hard mask dielectric layer comprises first silicon oxide, silicon nitride and second silicon dioxide;
forming a first groove and a second groove on the semiconductor substrate by using the hard mask dielectric layer as a barrier layer and adopting a photoetching and etching process;
depositing third silicon oxide;
removing the second silicon oxide and the third silicon oxide which are higher than the upper surface of the silicon nitride by adopting a chemical mechanical grinding process, and then removing the silicon nitride;
removing the third silicon oxide and the first silicon oxide in the region outside the first trench by using a photoresist as a barrier layer by adopting a photoetching and etching process, retaining the third silicon oxide at the bottom and on the side wall of the first trench, and then removing the photoresist;
growing fourth silicon oxide by adopting a thermal oxidation process; then removing the fourth silicon oxide by adopting an etching method;
growing fifth silicon oxide (namely a gate oxide) by adopting a thermal oxidation process, depositing polycrystalline silicon, and carrying out first ion implantation doping on the polycrystalline silicon to form first doped polycrystalline silicon;
carrying out secondary ion implantation doping on the polysilicon in partial region by adopting a photoetching and ion implantation process and taking the photoresist as a barrier layer to form second doped polysilicon;
removing the photoresist, and annealing at high temperature to diffuse dopants of the first ion implantation doping and the second ion implantation doping to the bottom of the polysilicon to fully diffuse the polysilicon;
removing the first doped polysilicon and the second doped polysilicon which are higher than the upper surface of the fifth silicon oxide by adopting a chemical mechanical polishing process, and reserving polysilicon (first doped polysilicon) in the first groove and polysilicon (second doped polysilicon) in the second groove;
ion implantation followed by annealing forms a body region;
and forming a source region by adopting the technological methods of photoetching, ion implantation and annealing, and synchronously forming third doped polysilicon in the set region of the first doped polysilicon.
Preferably, before the high-temperature annealing, the first doped polysilicon and the second doped polysilicon are only distributed on the surface layer of the polycrystal, and after the high-temperature annealing, the dopant is distributed in the whole depth region from the surface to the bottom of the polycrystal; the first doped polysilicon is a subsequent polysilicon diode region, i.e., an electrostatic protection circuit region, and the second doped polysilicon is a polysilicon gate of the MOSFET.
Preferably, the thicknesses of the first silicon oxide and the silicon nitride are respectively 200-800 angstrom, and the thickness of the second silicon oxide is 1000-4000 angstrom.
Preferably, the depth of the first groove and the second groove is 0.8-1.6 microns, the width of the first groove is 100-400 microns, and the width of the second groove is 0.1-0.5 microns.
Preferably, the thickness of the third silicon oxide is 2000-5000 angstrom, in the deposition process, the second groove is filled with the third silicon oxide because of smaller width, the first groove is larger in width, and the third silicon oxide is uniformly covered at the bottom and the side wall of the second groove.
Preferably, the chemical mechanical polishing is top-down polishing and finally stays on the upper surface of the silicon nitride, because the chemical mechanical polishing is selective, the third silicon oxide on the bottom and the side wall of the first trench is retained, and the height of the upper surface of the third silicon oxide at the position of the side wall of the first trench is higher than the silicon surface and is equal to the sum of the thicknesses of the first silicon oxide and the silicon nitride.
Preferably, the thickness of the fourth silicon oxide is 200-1300 angstroms, and the thickness of the fourth silicon oxide is less than the sum of the thicknesses of the first silicon oxide and the silicon nitride.
Preferably, the doping type of the first ion implantation doping of the polysilicon is opposite to that of the second ion implantation doping of the polysilicon, and the dosage of the second ion implantation doping of the polysilicon is larger;
the first ion implantation doping of the polysilicon is boron with the dosage of 1E 14-5E 14/CM 2 The second ion implantation of polysilicon is doped with phosphorus in a dosage of 2E 15-2E 16/CM 2 The first doped polysilicon formed by the method is of a P type, and the second doped polysilicon is of an N type; alternatively, the first and second electrodes may be,
the first ion implantation doping of the polysilicon is phosphorus with the dosage of 1E 14-5E 14/CM 2 The second ion implantation doping of the polysilicon is boron with the dosage of 2E 15-2E 16/CM 2 The first doped polysilicon formed by the method is of an N type, and the second doped polysilicon is of a P type;
the area of the first doped polysilicon is completely covered and larger than the area of the first groove, and the area of the second doped polysilicon is completely covered and larger than the area of the second groove.
Preferably, the source region is formed by photoetching, ion implantation and annealing, the type of the dopant of the ion implantation in the step is the same as that of the dopant of the second ion implantation of the polysilicon, and is opposite to that of the dopant of the first ion implantation of the polysilicon, and the dosage of the ion implantation in the step is larger than that of the dopant of the first ion implantation of the polysilicon;
the first ion implantation doping of the polysilicon is boron with the dosage of 1E 14-5E 14/CM 2 The ion implantation of the source region is doped with phosphorus or arsenic, and the dosage is 2E 15-8E 15/CM 2 The third doped polysilicon formed by the method is N-type;
or, the first ion implantation doping of the polysilicon is phosphorus with the dosage of 1E 14-5E 14/CM 2 The ion implantation of the source region is doped with boron, and the dosage is 2E 15-8E 15/CM 2 The third doped polysilicon thus formed isAnd P type.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
the polycrystalline silicon diode formed by the invention is completely positioned in the groove, and the top of the polycrystalline silicon diode and the upper surface of the silicon substrate of the cellular area are positioned on the same horizontal plane, so that the problem of high step in the traditional manufacturing method is completely eliminated, the difficulty of the process steps such as planarization and the like can be reduced, the process risk is reduced, and the integration level of a chip is improved; the isolation layer manufactured between the polysilicon diode and the cellular region, namely the third silicon oxide on the side wall of the first groove, has the thickness of 2000-5000 angstroms, and is uniformly covered from the bottom to the top of the first groove, so that the isolation layer is very safe and reliable.
The manufacturing method disclosed by the invention is formed after all steps are repeatedly researched and demonstrated from practice, and is not a simple process combination performed by the aerial imagination.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1-A is a flow chart illustrating a method of fabricating a semiconductor integrated circuit according to the present invention;
FIG. 1-B is a schematic flow chart of a method for manufacturing a semiconductor integrated circuit according to the present invention;
FIG. 1 is a schematic structural diagram of step S1 according to the present invention;
FIG. 2 is a schematic structural diagram of step S2 according to the present invention;
FIG. 3 is a schematic structural diagram of step S3 according to the present invention;
FIGS. 4-5 are schematic structural views of step S4 according to the present invention;
FIGS. 6-8 are schematic structural views of step S5 according to the present invention;
FIGS. 9-10 are schematic structural views of step S6 according to the present invention;
FIGS. 11-13 are schematic structural views of step S7 according to the present invention;
FIG. 14 is a schematic structural diagram of step S8 according to the present invention;
FIG. 15 is a schematic diagram of step S9 according to the present invention;
FIG. 16 is a schematic structural diagram of step S10 according to the present invention;
FIG. 17 is a schematic structural diagram of step S11 according to the present invention;
FIG. 18 is a schematic structural diagram of step S12 according to the present invention;
fig. 19 is a schematic structural diagram of the present invention.
Fig. 20 is a top view of a polysilicon diode of the present invention.
Description of reference numerals:
100. a method of manufacturing a semiconductor integrated circuit; 1. a semiconductor substrate; 2. an epitaxial layer; 3. a first silicon oxide; 4. silicon nitride; 5. a second silicon dioxide; 6. a first trench; 7. a second trench; 8. a third silicon oxide; 9. photoresist; 10. a fourth silicon oxide; 11. a fifth silicon oxide; 12. polycrystalline silicon; 12.1, first doped polysilicon; 12.2, second doped polysilicon; 12.3, third doped polysilicon; 13. photoresist; w1, the width of the first groove; w2, the width of the second groove; 15. a source region; 16.1, a first contact hole; 16.2, a second contact hole.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Referring to fig. 1-a to 1-B, the present invention provides a method 100 for manufacturing a semiconductor integrated circuit, comprising the steps of:
step S1: growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped semiconductor substrate 1 and a lightly doped epitaxial layer 2, and the hard mask dielectric layer comprises first silicon oxide 3, silicon nitride 4 and second silicon oxide 5 (see figure 1);
step S2: forming a first trench 6 and a second trench 7 (refer to fig. 2) on the semiconductor substrate by using the hard mask dielectric layer as a barrier layer and adopting a photoetching and etching process;
and step S3: depositing a third silicon oxide 8 (see fig. 3);
and step S4: removing the second silicon oxide 5 and the third silicon oxide 8 (refer to fig. 4) higher than the upper surface of the silicon nitride 4 by using a chemical mechanical polishing process; subsequently removing the silicon nitride 4 (see fig. 5);
step S5: removing the third silicon oxide 8 and the first silicon oxide 3 in the region outside the first trench 6 by using the photoresist 9 as a barrier layer and by using a photolithography (see fig. 6) and etching process, and retaining the third silicon oxide 8 at the bottom and on the sidewall of the first trench 6 (see fig. 7); subsequently, the photoresist 9 is removed (see fig. 8);
step S6: growing fourth silicon oxide 10 (see fig. 9) by a thermal oxidation process; then, the fourth silicon oxide 10 is removed by etching (see fig. 10);
step S7: growing a fifth silicon oxide 11, namely a gate oxide layer, by adopting a thermal oxidation process (see fig. 11); depositing polysilicon 12 (see fig. 12); doping the polysilicon 12 by a first ion implantation to form a first doped polysilicon 12.1 (see fig. 13);
step S8: performing secondary ion implantation doping on the part of the polycrystalline silicon 12 by using the photoresist 13 as a barrier layer by adopting a photoetching and ion implantation process method to form second doped polycrystalline silicon 12.2 (see fig. 14);
step S9: removing the photoresist 13, and annealing at a high temperature to diffuse the dopants of the first ion implantation doping and the second ion implantation doping to the bottom of the polysilicon, so as to diffuse the polysilicon through (see fig. 15);
step S10: removing the first doped polysilicon 12.1 and the second doped polysilicon 12.2 higher than the upper surface of the fifth silicon oxide 11 by using a chemical mechanical polishing process, and retaining the polysilicon (the first doped polysilicon 12.1) in the first trench 6 and the polysilicon (the second doped polysilicon 12.2) in the second trench 7 (see fig. 16);
step S11: ion implantation followed by annealing forms body region 14 (see fig. 17);
step S12: by using the processes of photolithography, ion implantation, and annealing, the source region 15 is formed, and the third doped polysilicon 12.3 is simultaneously formed in the set region of the first doped polysilicon 12.1 (see fig. 18).
The subsequent process steps are conventional process steps and are not described herein. The first doped polysilicon 12.1 and the third doped polysilicon 12.3 are subsequent polysilicon diode regions, i.e., electrostatic protection circuit regions, and the second doped polysilicon 12.2 is a polysilicon gate of the MOSFET.
Before the high-temperature annealing, the first doped polysilicon 12.1 and the second doped polysilicon 12.2 are only distributed on the polycrystalline surface layer, and after the high-temperature annealing, the dopant is distributed in the whole depth region from the polycrystalline surface to the bottom.
It is understood that in this embodiment, the thicknesses of the first silicon oxide 3 and the silicon nitride 4 are 200 to 800 angstroms, respectively, and the thickness of the second silicon oxide 5 is 1000 to 4000 angstroms (the thicknesses of the first silicon oxide 3 and the silicon nitride 4 are thinner).
It is understood that, in the present embodiment, the depth of the first trench 6 and the second trench 7 is 0.8 to 1.6 micrometers, the width W1 of the first trench is 100 to 400 micrometers, and the width W2 of the second trench is 0.1 to 0.5 micrometers. (the area of the first trench is an area where a polysilicon diode is preset to be arranged, the area of the second trench is a preset MOSFET cell area, the cell area comprises a plurality of second trenches, and only two second trenches are shown in the schematic diagram).
It can be understood that, in this embodiment, the thickness of the third silicon oxide 8 is 2000 to 5000 angstrom (i.e. 0.2 to 0.5 μm), in this step of deposition process, the second trench 7 is filled with the third silicon oxide 8 because of its relatively small width, the first trench 6 is relatively large in width, and the third silicon oxide 8 uniformly covers the bottom and the sidewalls of the second trench.
It is understood that in the present embodiment, the cmp is performed from top to bottom and finally stays on the top surface of the silicon nitride 4, because the cmp is selective, the third silicon oxide 8 is retained at the bottom and the sidewall of the first trench 6, and the height of the top surface of the third silicon oxide 8 at the sidewall of the first trench 6 is higher than the silicon surface, and the height is equal to the sum of the thicknesses of the first silicon oxide 3 and the silicon nitride 4, as shown in fig. 4.
It is understood that in the present embodiment, the thickness of the fourth silicon oxide 10 is 200 to 1300 angstroms, it is required to ensure that the thickness of the fourth silicon oxide 10 is less than the sum of the thicknesses of the first silicon oxide 3 and the silicon nitride 4, otherwise, after the step of removing the fourth silicon oxide 10 by using the etching process is completed, the height of the upper surface of the third silicon oxide 8 at the position of the sidewall of the first trench 6 may be lower than the height of the silicon surface, which results in that there is not enough isolation layer between the polysilicon diode and the silicon substrate to be formed subsequently and the failure occurs. (see the effect of the subsequent formation, i.e., schematic diagram 16 and fig. 19, i.e., the process step of removing the fourth silicon oxide 10, intentionally pulling down the height of the upper surface of the third silicon oxide 8 but not below the silicon surface).
It can be understood that, in this embodiment, the doping types of the first ion implantation doping of the polysilicon and the second ion implantation doping of the polysilicon are opposite, and the dosage of the second ion implantation doping of the polysilicon is greater, specifically:
the first ion implantation doping of the polysilicon is boron with the dosage of 1E 14-5E 14/CM 2 The second ion implantation of polysilicon is doped with phosphorus in a dosage of 2E 15-2E 16/CM 2 The first doped polysilicon 12.1 thus formed is P-type, the second doped polysilicon 12.2 is N-type; alternatively, the first and second electrodes may be,
the first ion implantation doping of the polysilicon is phosphorus with the dosage of 1E 14-5E 14/CM 2 The second ion implantation doping of the polysilicon is boron with the dosage of 2E 15-2E 16/CM 2 The first doped polysilicon 12.1 thus formed is of N-type and the second doped polysilicon 12.2 is of P-type.
It is understood that in the present embodiment, the source region is formed by the lithography, ion implantation and annealing, the dopant of this step of ion implantation is the same as the dopant of the second ion implantation of the polysilicon, i.e. the opposite type of the dopant of the first ion implantation of the polysilicon, and the dosage of this step of ion implantation is greater than that of the first ion implantation of the polysilicon. The method specifically comprises the following steps:
the first ion implantation doping of the polysilicon is boron with the dosage of 1E 14-5E 14/CM 2 The ion implantation of the source region is doped with phosphorus or arsenic with the dosage of 2E 15-8E 15/CM 2 The third doped polysilicon 12.3 thus formed is of N type;
or, the first ion implantation doping of the polysilicon is phosphorus with the dosage of 1E 14-5E 14/CM 2 The ion implantation of the source region is doped with boron, and the dosage is 2E 15-8E 15/CM 2 The third doped polysilicon 12.3 thus formed is P-type.
And, there are the following important features:
the third doped polysilicon 12.3 is formed in a predetermined region, which is a plurality of regions distributed at intervals, and fig. 18 shows an example of three regions distributed at intervals and arranged in a central symmetry manner (corresponding to the schematic plan view 20); the area between the third doped polysilicon 12.3 distributed at intervals is the first doped polysilicon 12.1, the doping types of the first doped polysilicon and the second doped polysilicon are opposite, so that an npnpn.
After step S9, as shown in fig. 15, the area of the first doped polysilicon 12.1 completely covers and is larger than the area of the first trench 6, and the area of the second doped polysilicon 12.2 completely covers and is larger than the area of the second trench 7.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
the polycrystalline silicon diode formed by the invention is completely positioned in the groove, and the top of the polycrystalline silicon diode and the upper surface of the silicon substrate of the cellular area are positioned on the same horizontal plane, so that the problem of high step in the traditional manufacturing method is completely eliminated, the difficulty of the process steps such as planarization and the like can be reduced, the process risk is reduced, and the integration level of a chip is improved; the isolation layer manufactured between the polysilicon diode and the cellular region, namely the third silicon oxide on the side wall of the first groove, has the thickness of 2000-5000 angstroms, and is uniformly covered from the bottom to the top of the first groove, so that the isolation layer is very safe and reliable.
The manufacturing method disclosed by the invention is formed after all steps are repeatedly researched and demonstrated from practice, and is not a simple process combination performed by the aerial imagination.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A method for manufacturing a semiconductor integrated circuit, comprising the steps of:
growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily-doped semiconductor substrate and a lightly-doped epitaxial layer, and the hard mask dielectric layer comprises first silicon oxide, silicon nitride and second silicon dioxide;
forming a first groove and a second groove on the semiconductor substrate by using the hard mask dielectric layer as a barrier layer and adopting a photoetching and etching process;
depositing third silicon oxide;
removing the second silicon oxide and the third silicon oxide which are higher than the upper surface of the silicon nitride by adopting a chemical mechanical grinding process, and then removing the silicon nitride;
removing the third silicon oxide and the first silicon oxide in the area outside the first trench by using a photoresist as a barrier layer by adopting a photoetching and corrosion process method, retaining the third silicon oxide at the bottom and on the side wall of the first trench, and then removing the photoresist;
growing fourth silicon oxide by adopting a thermal oxidation process; then removing the fourth silicon oxide by adopting an etching method;
growing fifth silicon oxide (namely a gate oxide) by adopting a thermal oxidation process, depositing polycrystalline silicon, and doping the polycrystalline silicon by first ion implantation to form first doped polycrystalline silicon;
carrying out secondary ion implantation doping on the polysilicon in partial region by adopting a photoetching and ion implantation process and taking the photoresist as a barrier layer to form second doped polysilicon;
removing the photoresist, and annealing at high temperature to diffuse dopants of the first ion implantation doping and the second ion implantation doping to the bottom of the polysilicon to fully diffuse the polysilicon;
removing the first doped polysilicon and the second doped polysilicon which are higher than the upper surface of the fifth silicon oxide by adopting a chemical mechanical polishing process, and reserving polysilicon (first doped polysilicon) in the first groove and polysilicon (second doped polysilicon) in the second groove;
ion implantation followed by annealing forms a body region;
and forming a source region by adopting the technological methods of photoetching, ion implantation and annealing, and synchronously forming third doped polysilicon in the set region of the first doped polysilicon.
2. The method of claim 1, wherein the first doped polysilicon and the second doped polysilicon are distributed only on the surface of the polysilicon before the high temperature annealing, and the dopant is distributed in the entire depth region from the surface to the bottom of the polysilicon after the high temperature annealing; the first doped polysilicon is a subsequent polysilicon diode region, i.e., an electrostatic protection circuit region, and the second doped polysilicon is a polysilicon gate of the MOSFET.
3. The method according to claim 1, wherein the first silicon oxide and the silicon nitride each have a thickness of 200 to 800 angstroms, and the second silicon oxide has a thickness of 1000 to 4000 angstroms.
4. The method of claim 1, wherein the first trench and the second trench have a depth of 0.8 to 1.6 μm, the first trench has a width of 100 to 400 μm, and the second trench has a width of 0.1 to 0.5 μm.
5. The method according to claim 1, wherein the third silicon oxide has a thickness of 2000-5000 angstroms, and in the deposition process, the second trench is filled with the third silicon oxide because of its smaller width, and the first trench is filled with the third silicon oxide because of its larger width, so that the third silicon oxide uniformly covers the bottom and sidewalls of the second trench.
6. The method of claim 1, wherein the CMP is top-down polishing and eventually rests on the top surface of the silicon nitride, wherein the CMP is selective, the third silicon oxide remains on the bottom and sidewalls of the first trench, and the top surface of the third silicon oxide is higher than the silicon surface at the sidewalls of the first trench by a thickness equal to the sum of the thicknesses of the first silicon oxide and the silicon nitride.
7. The method according to claim 1, wherein the thickness of the fourth silicon oxide is 200 to 1300 angstroms, and the thickness of the fourth silicon oxide is smaller than the sum of the thicknesses of the first silicon oxide and the silicon nitride.
8. The method of claim 1, wherein the first ion implantation doping of polysilicon and the second ion implantation doping of polysilicon are of opposite doping types, and the second ion implantation doping of polysilicon has a higher doping dosage;
the first ion implantation doping of the polysilicon is boron with the dosage of 1E 14-5E 14/CM 2 The second ion implantation of polysilicon is doped with phosphorus in a dosage of 2E 15-2E 16/CM 2 The first doped polysilicon formed by the method is of a P type, and the second doped polysilicon is of an N type; alternatively, the first and second electrodes may be,
the first ion implantation doping of the polysilicon is phosphorus with the dosage of 1E 14-5E 14/CM 2 The second ion implantation doping of the polysilicon is boron with the dosage of 2E 15-2E 16/CM 2 The first doped polysilicon formed by the method is of an N type, and the second doped polysilicon is of a P type;
the area of the first doped polysilicon is completely covered and larger than the area of the first groove, and the area of the second doped polysilicon is completely covered and larger than the area of the second groove.
9. The method of claim 1, wherein the photolithography, ion implantation and annealing form a source region, the ion implantation step has a dopant of the same type as the second ion implantation dopant of the polysilicon and a dopant of the opposite type to the first ion implantation dopant of the polysilicon, and the ion implantation step has a dose greater than the dose of the first ion implantation dopant of the polysilicon;
the first ion implantation doping of the polysilicon is boron with the dosage of 1E 14-5E 14/CM 2 The ion implantation of the source region is doped with phosphorus or arsenic, and the dosage is 2E 15-8E 15/CM 2 The third doped polysilicon formed by the method is N-type;
or, the first ion implantation doping of the polysilicon is phosphorus with the dosage of 1E 14-5E 14/CM 2 The ion implantation of the source region is doped with boron, and the dosage is 2E 15-8E 15/CM 2 And the third doped polysilicon formed thereby is P-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211421804.XA CN115579326A (en) | 2022-11-14 | 2022-11-14 | Method for manufacturing semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211421804.XA CN115579326A (en) | 2022-11-14 | 2022-11-14 | Method for manufacturing semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115579326A true CN115579326A (en) | 2023-01-06 |
Family
ID=84588311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211421804.XA Pending CN115579326A (en) | 2022-11-14 | 2022-11-14 | Method for manufacturing semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115579326A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116387310A (en) * | 2023-04-01 | 2023-07-04 | 深圳市美浦森半导体有限公司 | Method for manufacturing semiconductor chip |
| CN116404002A (en) * | 2023-04-01 | 2023-07-07 | 深圳市美浦森半导体有限公司 | Method for manufacturing semiconductor chip |
-
2022
- 2022-11-14 CN CN202211421804.XA patent/CN115579326A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116387310A (en) * | 2023-04-01 | 2023-07-04 | 深圳市美浦森半导体有限公司 | Method for manufacturing semiconductor chip |
| CN116404002A (en) * | 2023-04-01 | 2023-07-07 | 深圳市美浦森半导体有限公司 | Method for manufacturing semiconductor chip |
| CN116387310B (en) * | 2023-04-01 | 2023-09-22 | 深圳市美浦森半导体有限公司 | Method for manufacturing semiconductor chip |
| CN116404002B (en) * | 2023-04-01 | 2023-12-01 | 深圳市美浦森半导体有限公司 | Method for manufacturing semiconductor chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9087856B2 (en) | Semiconductor device with buried bit line and method for fabricating the same | |
| JP4417962B2 (en) | Planarization method in the manufacture of superjunction devices | |
| CN115579326A (en) | Method for manufacturing semiconductor integrated circuit | |
| US8753937B2 (en) | Manufacturing method of power transistor device with super junction | |
| WO2001095391A1 (en) | Self-limiting polysilicon buffered locos for dram trench capacitor collar | |
| CN108400166B (en) | Power transistor with terminal trenches in terminal reduced surface electric field region | |
| CN111986997A (en) | Method for manufacturing super junction device | |
| US8492221B2 (en) | Method for fabricating power semiconductor device with super junction structure | |
| US20230020711A1 (en) | Semiconductor structure and method for manufacturing same | |
| CN111799161B (en) | Manufacturing method of low-voltage shielded gate field effect transistor | |
| TW201405819A (en) | Power MOSFET and methods for forming the same | |
| CN114361251A (en) | Preparation method of split gate power MOS device | |
| US10541241B2 (en) | Semiconductor device having thyristor and metal-oxide semiconductor transistor | |
| CN112820645B (en) | Power semiconductor device and preparation method thereof | |
| US9431286B1 (en) | Deep trench with self-aligned sinker | |
| CN111799332A (en) | Groove MOSFET device and preparation method | |
| US8754473B2 (en) | Power transistor device | |
| TW201440145A (en) | Method for fabricating semiconductor power device | |
| CN213601874U (en) | MOSFET device | |
| CN114023649A (en) | Method for manufacturing super junction device | |
| TWI517393B (en) | Semiconductor device and method of fabricating the same | |
| CN212587512U (en) | Groove MOSFET device | |
| CN116404002B (en) | Method for manufacturing semiconductor chip | |
| CN116544188A (en) | Method for manufacturing semiconductor integrated circuit | |
| CN114927465B (en) | Semiconductor device and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |