CN116544188A - Method for manufacturing semiconductor integrated circuit - Google Patents
Method for manufacturing semiconductor integrated circuit Download PDFInfo
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- CN116544188A CN116544188A CN202211422195.XA CN202211422195A CN116544188A CN 116544188 A CN116544188 A CN 116544188A CN 202211422195 A CN202211422195 A CN 202211422195A CN 116544188 A CN116544188 A CN 116544188A
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- polysilicon
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- 238000000034 method Methods 0.000 title claims abstract description 104
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 140
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 102
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 47
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 32
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 19
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000000903 blocking effect Effects 0.000 claims abstract description 13
- 238000001259 photo etching Methods 0.000 claims abstract description 13
- 239000000126 substance Substances 0.000 claims abstract description 11
- 238000007517 polishing process Methods 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 230000007797 corrosion Effects 0.000 claims abstract description 5
- 238000005260 corrosion Methods 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 153
- 229920005591 polysilicon Polymers 0.000 claims description 153
- 238000005468 ion implantation Methods 0.000 claims description 49
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 239000011800 void material Substances 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 6
- 210000000746 body region Anatomy 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000036961 partial effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 29
- 238000010586 diagram Methods 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 230000002829 reductive effect Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- JCALBVZBIRXHMQ-UHFFFAOYSA-N [[hydroxy-(phosphonoamino)phosphoryl]amino]phosphonic acid Chemical compound OP(O)(=O)NP(O)(=O)NP(O)(O)=O JCALBVZBIRXHMQ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a manufacturing method of a semiconductor integrated circuit, which comprises the following steps: growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped semiconductor substrate and a lightly doped epitaxial layer; forming a first groove and a second groove on the semiconductor substrate by taking the hard mask dielectric layer as a barrier layer and adopting a photoetching and etching process method; removing the hard mask dielectric layer, and growing second silicon dioxide, silicon nitride and third silicon oxide; removing third silicon oxide higher than the upper surface of the silicon nitride by adopting a chemical mechanical polishing process; removing the third silicon oxide in the area outside the first groove by adopting a photoetching and corrosion process method and taking photoresist as a blocking layer, reserving the third silicon oxide at the bottom and the side wall of the first groove, and then removing the photoresist; the manufacturing method of the semiconductor integrated circuit has the advantages of completely eliminating the high step problem in the traditional manufacturing method and the like.
Description
Technical Field
The present invention relates to the field of integrated circuit fabrication, and more particularly to a method of fabricating a semiconductor integrated circuit.
Background
With the development of semiconductor integrated circuits, there is a higher demand for performance of semiconductor devices, however, electrostatic discharge phenomenon occurs in various links of packaging, transportation, and use of semiconductor integrated circuits, which causes the devices to break down and fail by static electricity, so that the self-charging electrostatic protection function of semiconductor devices is important.
For trench type semiconductor devices, such as trench type MOSFET, SGT, IGBT, a typical fabrication method for self-charging electrostatic protection is to fabricate back-to-back diodes in the trench type semiconductor device. Taking a trench MOSFET as an example, a thicker dielectric layer is usually manufactured outside a cell region of the MOSFET, and then a polysilicon diode is manufactured above the dielectric layer.
Because of the above problems, a new manufacturing method is generated, that is, the polysilicon diode is manufactured in the trench, the top of the polysilicon diode is substantially level with the silicon plane, the problem of height difference is solved, the integration level of the device is greatly improved, but the method also faces a plurality of difficulties in technical aspects of the process, the main problem is the isolation problem between the polysilicon diode and the cell area, and various methods are proposed in the industry around the problems, but some defects still exist in practical application. Here, taking the issued patent 201310347156.2 as an example, at least the following problems exist:
(1) In the patent claim 1, a thick gate oxide is formed at the bottom of the trench and used as an insulating layer between the electrostatic discharge protection circuit and the trench power device formed later, so that the electrostatic discharge protection circuit can be placed in the trench, the thickness of the thick gate oxide is 3000-4000 a m, corresponding to the schematic diagram 3B, this step cannot be realized in practical process, because the area of the electrostatic discharge protection circuit is usually more than 100 x 100 m, that is, the size of the trench in which the electrostatic discharge protection circuit is located is more than 100 x 100 m, after the silicon dioxide is deposited, the thickness of the silicon dioxide in the area outside the trench and the area at the bottom of the trench is the same, and the etching is performed according to the step, so that all the silicon dioxide outside the trench cannot be selectively removed while the silicon dioxide with 3000-4000 a m remains in the trench.
(2) In the method, in claim 1, the first polysilicon is deposited, photoresist is coated on the region where the esd protection circuit is to be formed, the second polysilicon is deposited, polysilicon above the trench is etched back to remove polysilicon above the trench, and gate polysilicon and esd protection circuit polysilicon are formed respectively, corresponding to the schematic diagrams 3C-3F, which has a structural problem in practical process, because boron ions of the second polysilicon are only distributed on the surface layer of polysilicon, and polysilicon above the trench in the region not covered by photoresist is etched away (corresponding to the schematic diagram 3F) in the step of etching back polysilicon above the trench, that is, the surface layer of polysilicon doped with boron ions is etched away, so that the doping purpose of the gate polysilicon cannot be achieved, that is, the gate polysilicon remaining in the trench is not doped in fact, and the MOSFET cannot work normally.
(3) After the step of "etching back the polysilicon above the trench to form the gate polysilicon and the esd protection circuit polysilicon respectively" described in claim 1, corresponding to the schematic diagram of fig. 3F, the esd protection circuit polysilicon forms a very high step in the trench, i.e. the polysilicon surface in the trench has a very large height difference from the surface of the insulating layer, i.e. the manufacturing method does not fundamentally solve the problem of the height difference, but only transfers the step from outside the trench into the trench, which still has a very high difficulty for the subsequent planarization process, and there is still a risk of metal residue at the step position.
In summary, the invention patent 201310347156.2 has no practical significance in practical production, and similarly, other already-known technical data and patent information have some problems, and the problem of high steps in the manufacturing method of the trench semiconductor device with the electrostatic protection function is not fundamentally solved.
The scheme provides a new manufacturing method aiming at the problems.
Disclosure of Invention
The invention provides a manufacturing method of a semiconductor integrated circuit, which has the advantages of completely eliminating the high step problem existing in the traditional manufacturing method, and solving the high step problem existing in the original manufacturing method of a groove type semiconductor device.
The manufacturing method of the semiconductor integrated circuit provided by the embodiment of the application comprises the following steps:
growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped semiconductor substrate and a lightly doped epitaxial layer;
forming a first groove and a second groove on the semiconductor substrate by taking the hard mask dielectric layer as a barrier layer and adopting a photoetching and etching process method;
removing the hard mask dielectric layer, and growing second silicon dioxide, silicon nitride and third silicon oxide;
removing third silicon oxide higher than the upper surface of the silicon nitride by adopting a chemical mechanical polishing process;
removing the third silicon oxide in the area outside the first groove by adopting a photoetching and corrosion process method and taking photoresist as a blocking layer, reserving the third silicon oxide at the bottom and the side wall of the first groove, and then removing the photoresist;
removing silicon nitride in the area outside the first groove by adopting an etching process, removing second silicon dioxide in the area outside the first groove, and growing fourth silicon oxide, namely a gate oxide layer by adopting a thermal oxidation process;
depositing polysilicon, and performing first ion implantation doping on the polysilicon to form first doped polysilicon;
adopting photoetching and ion implantation process methods, taking photoresist as a blocking layer, and carrying out ion implantation doping on the polysilicon of the partial region for the second time to form second doped polysilicon;
removing the photoresist, and performing high-temperature annealing to diffuse the dopants doped by the first ion implantation and the second ion implantation to the bottom of the polysilicon, so as to diffuse the polysilicon;
removing the first doped polysilicon and the second doped polysilicon higher than the upper surface of the fourth silicon oxide by adopting a chemical mechanical polishing process, and reserving the polysilicon (first doped polysilicon) in the first groove and the polysilicon (second doped polysilicon) in the second groove;
ion implantation and then annealing to form a body region;
and forming a source region by adopting a photoetching, ion implantation and annealing process method, and synchronously forming third doped polysilicon in a set region of the first doped polysilicon.
Preferably, the depth of the first groove and the second groove is 0.8-1.6 micrometers, the width of the first groove is 100-400 micrometers, and the width of the second groove is 0.1-0.5 micrometers.
Preferably, the thickness of the second silicon oxide and the thickness of the silicon nitride are respectively 200-800 a m, and the thickness of the third silicon oxide is 1200-6000 a m, wherein the thickness of the third silicon oxide is far greater than the thickness of the second silicon oxide.
Preferably, the silicon nitride in the area outside the first trench is removed by an etching process, the etching process is selective, the silicon nitride at the bottom and the side wall of the first trench is not corroded due to the blocking of the third silicon oxide, and the silicon nitride in the area which is not blocked by the third silicon oxide is completely corroded.
Preferably, the etching process is used to remove the second silicon dioxide in the area outside the first trench, the etching process is selective, the second silicon dioxide at the bottom and the side wall of the first trench is not corroded due to the blocking of the silicon nitride, and the second silicon dioxide in the area not blocked by the silicon nitride is completely corroded.
Preferably, in the thermal oxidation process, the fourth silicon oxide is grown, the thickness of the fourth silicon oxide is greater than or equal to the thickness of the second silicon oxide, in the etching process, because of the isotropic characteristic of the etching process, the second silicon oxide at the top end position of the side wall of the first trench is easy to be etched away to form a small cavity, the width of the cavity is equal to the thickness of the second silicon oxide, and the thickness of the fourth silicon oxide is greater than or equal to the thickness of the second silicon oxide, so that the cavity can be repaired in the thermal oxidation process.
Preferably, the first ion implantation doping of the polysilicon and the second ion implantation doping of the polysilicon are opposite in doping type, and the second ion implantation doping of the polysilicon is larger in dosage, specifically:
the first ion implantation doping of polysilicon is boron with the dosage of 1E 14-5E 14/CM 2 The polysilicon is doped with phosphorus by the second ion implantation with the dosage of 2E 15-2E 16/CM 2 The first doped polysilicon formed by the method is of a P type, and the second doped polysilicon is of an N type; or,
the polysilicon is doped with phosphorus by ion implantation for the first time, and the dosage is 1E 14-5E 14/CM 2 The polysilicon is doped with boron by the second ion implantation with the dosage of 2E 15-2E 16/CM 2 The first doped polysilicon is N-type and the second doped polysilicon is P-type.
Preferably, after the first doped polysilicon and the second doped polysilicon higher than the upper surface of the fourth silicon oxide are removed by a chemical mechanical polishing process, a thermal oxidation process is used to grow fifth silicon oxide on the polysilicon surface.
Preferably, the thickness of the fifth silicon oxide is greater than the thickness of the silicon nitride.
The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:
1. the polysilicon diode formed by the invention is completely positioned in the groove, the top of the polysilicon diode and the upper surface of the silicon substrate of the cellular region are close to be in the same horizontal plane, and the problem of high steps in the traditional manufacturing method is completely eliminated, so that the difficulty of the process steps such as planarization and the like can be reduced, the process risk is reduced, and the integration level of the chip is improved.
2. The isolation layer manufactured between the polysilicon diode and the cell area, namely the second silicon dioxide, the silicon nitride and the third silicon oxide (the sum of the thicknesses of the second silicon dioxide, the silicon nitride and the third silicon oxide is more than 2000A/m) at the side wall and the bottom of the first groove, has uniform thickness and no cavity, and is a very safe and reliable isolation layer.
3. The manufacturing method disclosed by the invention is formed by repeatedly researching and repeatedly demonstrating all steps from the practical point of view, and is not a simple process combination which is performed by virtue of blank imagination, and has practical significance and feasibility compared with the manufacturing method for forming the polysilicon diode in the groove disclosed by the prior literature and patent.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for manufacturing a semiconductor integrated circuit according to the present invention;
FIG. 2 is a flow chart of a method for fabricating a semiconductor integrated circuit according to the present invention;
FIG. 3 is a schematic structural diagram of step S1 of the present invention;
FIG. 4 is a schematic structural diagram of step S2 of the present invention;
FIG. 5 is a schematic structural diagram of step S3 of the present invention;
FIG. 6 is a schematic structural diagram of step S4 of the present invention;
fig. 7 to 8 are schematic structural diagrams of step S5 of the present invention;
FIG. 9 is a schematic diagram of the structure of step S6 of the present invention;
FIG. 10 is a schematic diagram of the structure of step S7 of the present invention;
FIG. 11 is a schematic structural diagram of step S8 of the present invention;
fig. 12 to 13 are schematic structural views of step S9 of the present invention;
FIG. 14 is a schematic diagram of the structure of step S10 of the present invention;
FIG. 15 is a schematic diagram of the structure of step S11 of the present invention;
FIG. 16 is a schematic diagram of the structure of step S12 of the present invention;
FIG. 17 is a schematic diagram of the structure of the present invention;
FIG. 18 is a schematic diagram of the structure of step S13 of the present invention;
FIG. 19 is a schematic diagram of the structure of step S14 of the present invention;
FIG. 20 is a schematic diagram of a MOSFET integrated circuit structure according to the present invention;
fig. 21 is a schematic diagram of a MOSFET integrated circuit according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
Referring to fig. 1 to 2, the present invention provides a method 100 for manufacturing a semiconductor integrated circuit, comprising the steps of:
step S1: growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped semiconductor substrate 1 and a lightly doped epitaxial layer 2 (see fig. 3);
step S2: forming a first groove 4 and a second groove 5 on a semiconductor substrate by using a hard mask dielectric layer as a barrier layer and adopting a photoetching and etching process method (refer to fig. 4);
step S3: removing the hard mask dielectric layer; growing a second silicon oxide 6, a silicon nitride 7, a third silicon oxide 8 (see fig. 5);
step S4: removing a third silicon oxide 8 (see fig. 6) higher than the upper surface of the silicon nitride 7 by using a chemical mechanical polishing process;
step S5: removing the third silicon oxide 8 in the area outside the first groove 4 by adopting a photoetching (refer to fig. 7) and corrosion process method and taking the photoresist 9 as a blocking layer, reserving the third silicon oxide 8 at the bottom and the side wall of the first groove 4, and then removing the photoresist 9 (refer to fig. 8);
step S6: removing the silicon nitride 7 (see fig. 9) in the area outside the first trench 4 by an etching process;
step S7: removing the second silicon dioxide 6 (see fig. 10) in the area outside the first trench 4 by an etching process;
step S8: growing a fourth silicon oxide 10, i.e., a gate oxide layer, by a thermal oxidation process (see fig. 11);
step S9: depositing polysilicon 11 (see fig. 12), and performing first ion implantation doping on the polysilicon 11 to form first doped polysilicon 11.1 (see fig. 13);
step S10: using photoetching and ion implantation process methods, taking the photoresist 12 as a blocking layer, and carrying out ion implantation doping on the polysilicon 11 in a partial area for the second time to form second doped polysilicon 11.2 (see fig. 14);
step S11: removing the photoresist 12, and performing high-temperature annealing to diffuse the dopants of the first ion implantation doping and the second ion implantation doping to the bottom of the polysilicon, so as to diffuse the polysilicon (see fig. 15);
in said step S11, the first doped polysilicon 11.1 and the second doped polysilicon 11.2 are distributed only on the polysilicon surface layer before the high temperature anneal, and the dopants are distributed over the entire depth area from the polysilicon surface to the bottom after the high temperature anneal.
Step S12: the first doped polysilicon 11.1 and the second doped polysilicon 11.2 above the upper surface of the fourth silicon oxide 10 are removed by chemical mechanical polishing, the polysilicon in the first trench 4 (the first doped polysilicon 11.1) is reserved, and the polysilicon in the second trench 5 (the second doped polysilicon 11.2) is reserved (see fig. 16).
In step S12, the first doped polysilicon 11.1 is a subsequent polysilicon diode region, i.e. an electrostatic protection circuit region, and the second doped polysilicon 11.2 is a polysilicon gate of the MOSFET.
Step S13: the ion implantation is then annealed to form body regions 14 (see fig. 18).
Step S14: the source region 15 is formed by photolithography, ion implantation, and annealing, and the third doped polysilicon 11.3 is formed in the set region of the first doped polysilicon 11.1 simultaneously (see fig. 19).
The subsequent process steps are conventional process steps, and are not described herein.
It can be appreciated that in this embodiment, the hard mask dielectric layer is the first silicon oxide 3, and has a thickness of 2000 to 5000 a;
referring to fig. 4, it can be understood that in the present embodiment, the depth of the first trench 4 and the second trench 5 is 0.8-1.6 micrometers, the width W1 of the first trench is 100-400 micrometers, and the width W2 of the second trench is 0.1-0.5 micrometers. (the first trench region is a region where the polysilicon diode is arranged in advance, the second trench region is a preset MOSFET cell region, and the cell region includes a plurality of second trenches, and only two second trenches are shown in the schematic diagram).
It will be appreciated that in this embodiment, the thicknesses of the second silicon oxide 6 and the silicon nitride 7 are respectively 200 to 800 a/m, and the thickness of the third silicon oxide 8 is 1200 to 6000 a/m (i.e., 0.12 to 0.6 μm), wherein the thickness of the third silicon oxide 8 is much larger than the thickness of the second silicon oxide 6 (the thickness ratio is 5:1 or more).
It will be appreciated that in this embodiment, the process of growing the silicon nitride 7 and growing the third silicon oxide 8 is chemical vapor deposition, the second trench 5 is filled with the third silicon oxide 8 because of the smaller width, the first trench 4 is covered with the silicon nitride 7 and the third silicon oxide 8 uniformly at the bottom and the sidewall of the second trench because of the larger width.
Preferably, after the silicon nitride 7 and the third silicon oxide 8 are grown by adopting a chemical vapor deposition process, the silicon nitride and the third silicon oxide are densified by adopting a high-temperature annealing mode, so that the pressure resistance of the silicon nitride and the third silicon oxide is improved, the defects in the silicon nitride and the third silicon oxide are reduced, and the corrosion rate of the silicon nitride and the third silicon oxide is reduced. The high temperature annealing temperature is 950-1100 ℃.
It will be appreciated that in this embodiment, the cmp is performed from top to bottom, and finally stays on the upper surface of the silicon nitride 7, and since the cmp is selective, the third silicon oxide 8 at the bottom and the side walls of the first trench 4 is maintained as shown in fig. 6.
It will be appreciated that in this embodiment, the etching process is used to remove the silicon nitride 7 in the region outside the first trench 4: the etching process is selective, silicon nitride at the bottom and the side wall of the first trench 4 is not corroded due to the blocking of the third silicon oxide 8, and the silicon nitride at the area not blocked by the third silicon oxide 8 is completely corroded (therefore, photoresist is not needed to be used as a blocking layer in the etching process, namely, the photolithography process is not needed to be added, so that the cost is saved).
It will be appreciated that in this embodiment, the etching process is used to remove the second silicon oxide 6 in the region outside the first trench 4: the etching process is selective, the second silicon dioxide 6 at the bottom and the side wall of the first trench 4 is not corroded due to the blocking of the silicon nitride 7, and the second silicon dioxide 6 at the area not blocked by the silicon nitride 7 is completely corroded (therefore, the etching process does not need to take photoresist as a blocking layer, namely, the photolithography process is not added, so that the cost is saved).
In this etching process, a part of the third silicon oxide 8 at the bottom and the side wall of the first trench 4 is etched away, but since the thickness of the third silicon oxide 8 is far greater than the thickness of the second silicon oxide 6 (the thickness ratio is 5:1 or more), the third silicon oxide 8 at the bottom and the side wall of the first trench 4 is mostly preserved as long as the process time of this etching process is reasonably controlled (the over etching is increased by about 15% on the basis of ensuring that the second silicon oxide 6 at the area outside the first trench 4 is just completely etched away); it is generally required that the sum of the thicknesses of the second silicon oxide 6, the silicon nitride 7 and the third silicon oxide 8 at the bottom (and the sidewalls) of the first trench 4 after this process is greater than 2000 a/m to safely and effectively isolate the polysilicon diode from the cell region.
It will be appreciated that in the present embodiment, the thermal oxidation process is used to grow the fourth silicon oxide 10, i.e., the gate oxide layer: the thickness of the fourth silicon oxide 10 is greater than or equal to the thickness of the second silicon oxide 6. In the process step of step S7 (corresponding to fig. 10), because of the isotropic nature of the etching process, the second silicon oxide 6 at the top end of the sidewall of the first trench 4 is easily etched away to form a small cavity, the width of which is equal to the thickness of the second silicon oxide 6, and if the process thickness of the fourth silicon oxide 10 is greater than or equal to the thickness of the second silicon oxide 6, it is ensured that the cavity is repaired in the thermal oxidation process (i.e., the oxide layer grown on the trench sidewall at the cavity position may be filled up).
It can be understood that in this embodiment, the doping type of the first ion implantation doping of the polysilicon is opposite to the doping type of the second ion implantation doping of the polysilicon, and the dosage of the second ion implantation doping of the polysilicon is larger, specifically:
the first ion implantation doping of polysilicon is boron with the dosage of 1E 14-5E 14/CM 2 The polysilicon is doped with phosphorus by the second ion implantation with the dosage of 2E 15-2E 16/CM 2 The first doped polysilicon 11.1 formed thereby is P-type and the second doped polysilicon 11.2 is N-type; or,
the polysilicon is doped with phosphorus by ion implantation for the first time, and the dosage is 1E 14-5E 14/CM 2 The polysilicon is doped with boron by the second ion implantation with the dosage of 2E 15-2E 16/CM 2 The first doped polysilicon 11.1 thus formed is of N-type and the second doped polysilicon 11.2 is of P-type.
After step S11, as shown in fig. 15, the region of the first doped polysilicon 11.1 completely covers and is larger than the region of the first trench 4, and the region of the second doped polysilicon 11.2 completely covers and is larger than the region of the second trench 5.
Preferably, after the first doped polysilicon 11.1 and the second doped polysilicon 11.2 above the upper surface of the fourth silicon oxide 10 are removed by chemical mechanical polishing, a thermal oxidation process is used to grow the fifth silicon oxide 13 on the polysilicon surface, corresponding to the schematic diagram 17.
On the one hand, in the process of growing silicon oxide by adopting a thermal oxidation process, silicon atoms on the surface layer of the polysilicon are oxidized to generate silicon oxide, and in the process, the interface between the top (mainly focusing on the top of the first doped polysilicon 11.1) and the silicon oxide is gradually moved downwards, so that the interface is slightly lower than the silicon plane (for example, 300-1500A. Lower).
On the other hand, in step S6 (corresponding to fig. 9), because of the isotropic nature of the etching process, the silicon nitride 7 at the top end position of the sidewall of the first trench 4 is easily etched away to form a small void, the width of which is equal to the thickness of the silicon nitride, which remains after the completion of step S8 (corresponding to fig. 11), in step S9 (corresponding to fig. 12), the void is filled with the deposited polysilicon, and because the location of the void is lower than the upper surface of the fourth silicon oxide 10, it is difficult to polish the polysilicon in the void by chemical mechanical polishing in step S12, i.e., polysilicon residues are formed at the location of the void, as shown in fig. 16; in this thermal oxidation process, the polysilicon remaining in the voids is oxidized simultaneously to form silicon oxide, as shown in fig. 17.
Preferably, the thickness of the fifth silicon oxide 13 is greater than the thickness of the silicon nitride 7, in such a way that the cavities are completely filled with the silicon oxide produced in this step.
From the results of the above two aspects, it can be seen that the first doped polysilicon 11.1 finally remaining in the first trench 4 has a bottom and a lateral direction which form an effective isolation from the silicon region, in particular, a double protection is provided at the top end of the sidewall of the first trench 4:
1. the cavities at the top end positions of the side walls of the first grooves 4 (and the vicinity thereof) are completely filled with silicon oxide, and no electric conductors (such as polysilicon residues) exist, so that no leakage channel exists;
2. the top plane of the first doped polysilicon 11.1 in the first trench 4 moves down below the silicon plane and the horizontal direction avoids the topmost area where voids are most likely to occur, reducing the risk of leakage from the sides to the cell area.
It will be appreciated that in this embodiment, the source region is formed by photolithography, ion implantation, and annealing, and the dopant of this step is the same type as the dopant of the second ion implantation of polysilicon, i.e., the opposite type of the first ion implantation of polysilicon, and the dose of this step is greater than the dose of the first ion implantation of polysilicon. The method comprises the following steps:
the first ion implantation doping of polysilicon is boron with the dosage of 1E 14-5E 14/CM 2 The ion implantation of the source region is doped with phosphorus or arsenic, and the dosage is 2E 15-8E 15/CM 2 The third doped polysilicon 11.3 thus formed is of N-type;
alternatively, the polysilicon is doped with phosphorus by ion implantation for the first time, and the dosage is 1E 14-5E 14/CM 2 The source region is ion-implanted and doped with boron, and the dosage is 2E 15-8E 15/CM 2 The third doped polysilicon 11.3 thus formed is P-type.
And, there are the following important features:
the third doped polysilicon 11.3 is formed in a preset area, and is a plurality of areas distributed at intervals, and the example shown in fig. 19 is three areas distributed at intervals in a central symmetry arrangement (corresponding to the schematic plan view 21); the region between the third doped polysilicon 11.3 which is distributed at intervals is the first doped polysilicon 11.1, the doping types of the first doped polysilicon 11.1 and the second doped polysilicon are opposite, and an NPNPNPN or PNPNP staggered structure is formed, namely, a back-to-back polysilicon diode (the polysilicon diode connected in series by a forward PN junction and a reverse PN junction) is formed, and in the subsequent process steps, the first contact hole 16.1 and the second contact hole 16.2 are manufactured to lead out the two ends of the back-to-back polysilicon diode, as shown in the figures 20 and 21, and are respectively connected to the grid electrode and the source electrode of the MOSFET, namely, the MOSFET integrated circuit with the self-static protection function is formed.
The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:
1. the polysilicon diode formed by the invention is completely positioned in the groove, the top of the polysilicon diode and the upper surface of the silicon substrate of the cellular region are close to be in the same horizontal plane, and the problem of high steps in the traditional manufacturing method is completely eliminated, so that the difficulty of the process steps such as planarization and the like can be reduced, the process risk is reduced, and the integration level of the chip is improved.
2. The isolation layer manufactured between the polysilicon diode and the cell area, namely the second silicon dioxide, the silicon nitride and the third silicon oxide (the sum of the thicknesses of the second silicon dioxide, the silicon nitride and the third silicon oxide is more than 2000A/m) at the side wall and the bottom of the first groove, has uniform thickness and no cavity, and is a very safe and reliable isolation layer.
3. The manufacturing method disclosed by the invention is formed by repeatedly researching and repeatedly demonstrating all steps from the practical point of view, and is not a simple process combination which is performed by virtue of blank imagination, and has practical significance and feasibility compared with the manufacturing method for forming the polysilicon diode in the groove disclosed by the prior literature and patent.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (9)
1. A method for manufacturing a semiconductor integrated circuit, comprising the steps of:
growing a hard mask dielectric layer on a semiconductor substrate, wherein the semiconductor substrate comprises a heavily doped semiconductor substrate and a lightly doped epitaxial layer;
forming a first groove and a second groove on the semiconductor substrate by taking the hard mask dielectric layer as a barrier layer and adopting a photoetching and etching process method;
removing the hard mask dielectric layer, and growing second silicon dioxide, silicon nitride and third silicon oxide;
removing third silicon oxide higher than the upper surface of the silicon nitride by adopting a chemical mechanical polishing process;
removing the third silicon oxide in the area outside the first groove by adopting a photoetching and corrosion process method and taking photoresist as a blocking layer, reserving the third silicon oxide at the bottom and the side wall of the first groove, and then removing the photoresist;
removing silicon nitride in the area outside the first groove by adopting an etching process, removing second silicon dioxide in the area outside the first groove, and growing fourth silicon oxide, namely a gate oxide layer by adopting a thermal oxidation process;
depositing polysilicon, and performing first ion implantation doping on the polysilicon to form first doped polysilicon;
adopting photoetching and ion implantation process methods, taking photoresist as a blocking layer, and carrying out ion implantation doping on the polysilicon of the partial region for the second time to form second doped polysilicon;
removing the photoresist, and performing high-temperature annealing to diffuse the dopants doped by the first ion implantation and the second ion implantation to the bottom of the polysilicon, so as to diffuse the polysilicon;
removing the first doped polysilicon and the second doped polysilicon higher than the upper surface of the fourth silicon oxide by adopting a chemical mechanical polishing process, and reserving the polysilicon (first doped polysilicon) in the first groove and the polysilicon (second doped polysilicon) in the second groove;
ion implantation and then annealing to form a body region;
and forming a source region by adopting a photoetching, ion implantation and annealing process method, and synchronously forming third doped polysilicon in a set region of the first doped polysilicon.
2. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the depth of the first trench and the second trench is 0.8 to 1.6 μm, the width W1 of the first trench is 100 to 400 μm, and the width W2 of the second trench is 0.1 to 0.5 μm.
3. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the thickness of the second silicon oxide and the thickness of the silicon nitride are respectively 200 to 800 a m, and the thickness of the third silicon oxide is 1200 to 6000 a m, wherein the thickness of the third silicon oxide is substantially larger than the thickness of the second silicon oxide.
4. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the silicon nitride in the region outside the first trench is removed by an etching process which is selective, and the silicon nitride in the bottom and side walls of the first trench is not etched due to the barrier of the third silicon oxide, and the silicon nitride in the region not blocked by the third silicon oxide is entirely etched.
5. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the second silicon oxide in the region outside the first trench is removed by an etching process which is selective, the second silicon oxide in the bottom and side walls of the first trench is not etched due to the barrier of silicon nitride, and the second silicon oxide in the region not blocked by silicon nitride is entirely etched.
6. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the thermal oxidation process is used to grow a fourth silicon oxide having a thickness greater than or equal to that of the second silicon oxide, and wherein in the etching process, the second silicon oxide at a top end position of the sidewall of the first trench is easily etched away to form a small void having a width equal to that of the second silicon oxide due to an isotropic feature of the etching process, and wherein the fourth silicon oxide has a process thickness greater than or equal to that of the second silicon oxide, the repair of the void in the thermal oxidation process is ensured.
7. The method according to claim 1, wherein the polysilicon first ion implantation doping and the polysilicon second ion implantation doping are opposite in doping type, and the polysilicon second ion implantation doping is larger in dosage, specifically:
the first ion implantation doping of polysilicon is boron with the dosage of 1E 14-5E 14/CM 2 The polysilicon is doped with phosphorus by the second ion implantation with the dosage of 2E 15-2E 16/CM 2 The first doped polysilicon formed by the method is of a P type, and the second doped polysilicon is of an N type; or,
the polysilicon is doped with phosphorus by ion implantation for the first time, and the dosage is 1E 14-5E 14/CM 2 The polysilicon is doped with boron by the second ion implantation with the dosage of 2E 15-2E 16/CM 2 The first doped polysilicon is N-type and the second doped polysilicon is P-type.
8. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein after removing the first doped polysilicon and the second doped polysilicon higher than the upper surface of the fourth silicon oxide by a chemical mechanical polishing process, a thermal oxidation process is used to grow fifth silicon oxide on the polysilicon surface.
9. The method for manufacturing a semiconductor integrated circuit according to claim 8, wherein a thickness of the fifth silicon oxide is larger than a thickness of the silicon nitride.
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