CN112820645B - Power semiconductor device and preparation method thereof - Google Patents
Power semiconductor device and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
The embodiment of the application provides a power semiconductor device and a preparation method thereof, wherein the preparation method of the power semiconductor device comprises the following steps: forming a trench gate type MOS structure in a semiconductor substrate, wherein the trench gate type MOS structure comprises a body region, a first trench, a second trench, a first insulating layer, a second insulating layer, a third insulating layer, first polycrystalline silicon, second polycrystalline silicon, a source region, a fourth insulating layer and a fifth insulating layer; depositing a stop layer; depositing an interlayer dielectric layer on the surface of the stop layer; etching the interlayer dielectric layer, the stop layer, the third insulating layer and the fifth insulating layer; etching the body region around the first groove and the second polysilicon; and doping the surface of the body region around the first groove. By adopting the scheme in the application, the conducting layer can be uniformly manufactured in the main unit area to realize the leading-out of the electrode, so that the process control difficulty is reduced, the yield is improved, and the manufacturing cost is reduced.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a power semiconductor device and a preparation method thereof.
Background
The power Semiconductor device is a basic electronic component for energy conversion and control of a power electronic system, the continuous development of the power electronic technology opens up a wide application Field for the power Semiconductor device, and the power Semiconductor device marked by Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and Insulated Gate Bipolar Transistor (IGBT) is the mainstream in the Field of the power electronic device at present.
The gate structures of MOSFETs and IGBTs include a trench type and a planar type. The trench gate is usually formed by growing a gate oxide layer on the sidewall of the trench and filling polysilicon, and this gate structure improves the utilization efficiency of the planar area of the power semiconductor device, so that the available channel width and current density per unit area are larger, and the device obtains larger current conduction capability, therefore, the power semiconductor device with the trench gate has been widely applied to various fields such as motor speed regulation, inverters, power supplies, electronic switches, audio devices, automobile electric appliances, and the like.
The mainstream power semiconductor device with a trench gate adopts a design that a plurality of cells are repeated at a certain step pitch and are finally connected in parallel. Driven by moore's law, the number of cells per unit area ultimately determines the performance of the device, and thus it is necessary to reduce the size of the trenches and contact holes as much as possible to reduce the size of the cells as much as the fabrication capability allows. The smaller step size places higher demands on the equipment, such as the use of a deep ultraviolet lithography tool with a 248nm or shorter wavelength light source to etch process-sized trenches and contact holes when etching trenches and contact holes. In addition, the step pitch is reduced, and the two-time photoetching patterns for preparing the grooves and the contact holes are required to have higher alignment precision, so that the problems of high process control difficulty, reduced yield, high manufacturing cost and the like are caused.
Disclosure of Invention
The embodiment of the application provides a power semiconductor device and a preparation method thereof, which are used for solving the problems of high process control difficulty, yield reduction and high manufacturing cost of the power semiconductor device.
According to a first aspect of embodiments of the present application, there is provided a method for manufacturing a power semiconductor device, including:
forming a trench-gate MOS structure in a semiconductor substrate, the trench-gate MOS structure comprising: a body region of a first doping type extending from the surface of the semiconductor substrate into the semiconductor substrate; a first trench and a second trench penetrating the body region, a width of the second trench being greater than a width of the first trench; a first insulating layer located on the inner wall of the first trench; the second insulating layer is positioned on the inner wall of the second groove; a third insulating layer on the surface of the body region; first polysilicon filled in the first trench; the second polycrystalline silicon is filled in the second groove, and the surface of the first polycrystalline silicon and the surface of the second polycrystalline silicon are lower than the surface of the body region; the source region of the second doping type is positioned on the surface of the body region around the first groove and on the side face of the body region, and the second doping type is opposite to the first doping type; the fourth insulating layer is positioned on the surface of the first polycrystalline silicon; a fifth insulating layer on the second polysilicon surface;
depositing a stop layer to completely fill the first trench and partially fill the second trench to form a third trench in the second trench;
depositing an interlayer dielectric layer on the surface of the stop layer, wherein the interlayer dielectric layer completely fills the third groove;
etching the interlayer dielectric layer, the stop layer, the third insulating layer and the fifth insulating layer to expose the body surface around the first trench, reserving the stop layer in the first trench as a covering structure, forming a side wall structure in the second trench and exposing a part of the surface of the second polysilicon;
etching the body region around the first groove and the second polysilicon to remove the source region on the surface of the body region around the first groove and form a groove structure on the second polysilicon;
and doping the surface of the body region around the first groove to form a contact region of the first doping type.
Further, forming a trench-gate type MOS structure in a semiconductor substrate includes:
doping the semiconductor substrate to form a body region;
etching the body region to form a first groove and a second groove;
growing a first insulating layer, a second insulating layer and a third insulating layer;
filling and etching back the first trench and the second trench with polysilicon to form first polysilicon and second polysilicon correspondingly;
doping the surface of the body region and the side face of the body region around the first groove to form a source region;
and growing a fourth insulating layer and a fifth insulating layer.
Further, doping the surface and the side face of the body region around the first trench to form a source region comprises: and carrying out ion implantation on the body region, wherein the included angle between the ion incidence direction and the normal of the body region is 30-45 degrees.
Further, etching the interlayer dielectric layer, the stop layer, the third insulating layer and the fifth insulating layer includes:
etching the interlayer dielectric layer to expose the stop layer positioned right above the first groove and the stop layer positioned in the second groove;
and etching the stop layer, the third insulating layer and the fifth insulating layer to expose the surface of the body region around the first trench, reserving the stop layer in the first trench as a covering structure, forming a side wall structure in the second trench and exposing part of the surface of the second polysilicon.
Further, after doping the surface of the body region around the first trench, the method further includes:
sequentially depositing a barrier metal layer and a front metal layer on the surface of the whole device;
and etching the front metal layer and the barrier metal layer to form a first electrode structure and a second electrode structure, wherein the first electrode structure at least covers the first groove, the source region and the contact region, and the second electrode structure at least covers the second groove.
Further, the preparation method further comprises the following steps:
thinning the semiconductor substrate;
and depositing a back metal layer on the back of the thinned semiconductor substrate.
According to a second aspect of embodiments of the present application, there is provided a power semiconductor device, including:
a semiconductor substrate;
a body region extending from a surface of the semiconductor substrate into the semiconductor substrate, the body region including a first region and a second region;
the first groove penetrates through the first area, a first insulating layer is arranged on the inner wall of the first groove and exceeds the surface of the first area, first polycrystalline silicon, a fourth insulating layer and a covering structure are sequentially arranged in the first groove from bottom to top, the surface of the fourth insulating layer is lower than the surface of the first area, a source area is arranged on the side face of a body area around the first groove, the doping type of the source area is opposite to that of the body area, a contact area is arranged on the surface of the body area around the first groove, and the doping type of the contact area is the same as that of the body area;
a second groove penetrating through the second area, wherein the width of the second groove is larger than that of the first groove, a second insulating layer is arranged on the inner wall of the second groove, and second polycrystalline silicon with a groove structure, a fifth insulating layer positioned on the top surface of the groove structure and a side wall structure positioned on the surface of the fifth insulating layer are sequentially arranged in the second groove from bottom to top;
a third insulating layer on the surface of the second region;
a stop layer located on the surface of the third insulating layer;
and the interlayer dielectric layer is positioned on the surface of the stop layer.
Further, the surface of the first area is lower than the surface of the second area, and the surface of the covering structure and the surface of the second area are in the same plane.
Furthermore, the ratio of the height of the covering structure exceeding the surface of the first area to the width of the source area is 1: 1-10: 1.
Further, the aforementioned power semiconductor device further includes:
the first electrode structure at least covers the first groove, the source region and the contact region, and comprises a first barrier metal layer and a first front metal layer positioned on the surface of the first barrier metal layer;
and the second electrode structure at least covers the second groove, the second electrode structure comprises a second barrier metal layer and a second front metal layer positioned on the surface of the second barrier metal layer, and the second electrode structure is not contacted with the first electrode structure.
By using the power semiconductor device and the preparation method thereof provided by the embodiment of the application, the stop layer in the first trench in the main cell region is reserved as the covering structure, and the source region is formed on the side surface of the body region around the first trench, so that the body region around the first trench can be connected with the front metal layer not through a plurality of small-sized contact holes, but the leading-out of the electrode is realized by uniformly manufacturing the conductive layer. Because small-sized contact holes do not need to be manufactured independently, the harsh requirements of device preparation on high-end semiconductor equipment, particularly high-precision photoetching machines, are reduced, or the dependence on the high-precision photoetching machines is reduced. Moreover, the process requirement of the large-size contact hole on the metalized filling hole is reduced, and high-cost manufacturing processes such as metal plugs, CMP planarization and the like are not needed; the reliability of a single large-sized contact hole is much higher than that of a plurality of small-sized contact holes. Therefore, the power semiconductor device and the preparation method thereof provided by the embodiment of the application can reduce the process control difficulty, improve the yield and reduce the manufacturing cost.
On the basis, the distance between the front metal layer and the polycrystalline silicon in the first groove is increased by reserving the stop layer in the first groove as a covering structure, so that the gate-source capacitance can be reduced, namely the input capacitance is reduced, and the switching speed of the power semiconductor device can be increased. In addition, when the contact region is formed by injection, the doping concentration on the surface of the polysilicon gate can be prevented from being reduced due to the influence of inversion injection doping by utilizing the isolation effect of the covering structure, and the abnormal rise of the resistance of the gate can be further prevented, so that the performance of a device can be improved, and the stability of parameters of the device can be guaranteed. In addition, because the covering structure is higher than the source region on the side face of the body region around the first groove, when the source region is formed by injection, the shadow effect of the covering structure is utilized, the phenomenon that the doping concentration of the source region is reduced by inversion injection doping can be avoided, the abnormal rise of the source resistance is avoided, the performance of the device can be further improved, and the stability of the parameters of the device is ensured.
And, through forming the side wall structure in the second slot, can avoid taking place contact offset, avoid the grid short circuit.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 to 18 are schematic device structures in steps of a method for manufacturing a power semiconductor device according to an embodiment of the present application;
fig. 19 is a schematic diagram of a partial layout of a power semiconductor device in the prior art;
fig. 20 is a schematic diagram of a partial layout of a power semiconductor device according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present application clearer, the following describes exemplary embodiments of the present application in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all the embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
In a first aspect, embodiments of the present application provide a method for manufacturing a power semiconductor device, where the power semiconductor device may specifically be a power semiconductor device having a trench gate, such as a MOSFET and an IGBT. The preparation method of the semiconductor device comprises the following steps:
step S11, forming a trench gate MOS structure in the semiconductor substrate, the trench gate MOS structure including: a body region of a first doping type extending from the surface of the semiconductor substrate into the semiconductor substrate; a first trench and a second trench penetrating the body region, a width of the second trench being greater than a width of the first trench; a first insulating layer on the inner wall of the first trench; the second insulating layer is positioned on the inner wall of the second groove; a third insulating layer on the surface of the body region; first polysilicon filled in the first trench; the second polycrystalline silicon is filled in the second groove, and the surface of the first polycrystalline silicon and the surface of the second polycrystalline silicon are lower than the surface of the body region; the source region of the second doping type is positioned on the surface of the body region around the first groove and on the side face of the body region, and the second doping type is opposite to the first doping type; the fourth insulating layer is positioned on the surface of the first polycrystalline silicon; a fifth insulating layer on the second polysilicon surface;
step S12, depositing a stop layer to completely fill the first trench and partially fill the second trench to form a third trench in the second trench;
step S13, depositing an interlayer dielectric layer on the surface of the stop layer, wherein the interlayer dielectric layer completely fills the third groove;
step S14, etching the interlayer dielectric layer, the stop layer, the third insulating layer and the fifth insulating layer to expose the body surface around the first trench, and reserving the stop layer in the first trench as a covering structure to form a side wall structure in the second trench and expose part of the surface of the second polysilicon;
step S15, etching the body region around the first groove and the second polysilicon to remove the source region on the surface of the body region around the first groove and form a groove structure on the second polysilicon;
step S16, doping the surface of the body region around the first trench to form a contact region of the first doping type.
Fig. 1 to 18 are schematic device structure diagrams in steps of a method for manufacturing a power semiconductor device according to an embodiment of the present application, and the method for manufacturing a power semiconductor device according to the embodiment of the present application is described in detail with reference to fig. 1 to 18.
The choice of semiconductor substrate is also different for different types of power semiconductor devices. If the MOSFET is prepared, an epitaxial wafer can be used as a semiconductor substrate; for the preparation of an IGBT, an epitaxial wafer or a single wafer can be used as a semiconductor substrate. Referring to fig. 1, taking an epitaxial wafer as an example of a semiconductor substrate, the epitaxial wafer includes a substrate 11 and an epitaxial layer 12 on a surface of the substrate 11. The epitaxial wafer may be obtained commercially, or may be obtained by depositing the epitaxial layer 12 on the surface of the substrate 11 by a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process.
In the embodiments of the present application, the doping types of the substrate 11 and the epitaxial layer 12 are not particularly limited. Generally, if the power semiconductor device is a MOSFET, the doping types of the substrate 11 and the epitaxial layer 12 are the same, for example, both the substrate 11 and the epitaxial layer 12 are doped N-type or both are doped P-type; if the power semiconductor device is an IGBT, the doping types of the substrate 11 and the epitaxial layer 12 may be different, for example, the substrate 11 is doped P-type, and the epitaxial layer 12 is doped N-type. The embodiments of the present application are not limited thereto, and the doping types of the two can be controlled according to the actual device type and parameter requirements.
In the power semiconductor device, the doping concentration of the substrate 11 is generally controlled to be greater than that of the epitaxial layer 12. The present invention is not limited thereto and the doping concentrations of both may be controlled according to the actual device type and parameter requirements.
In addition, the larger the thickness of the epitaxial layer 12, the more favorable the breakdown voltage of the device, especially in an IGBT, but the less favorable the miniaturization of the device. The thickness of the substrate 11 and the epitaxial layer 12 can be determined by those skilled in the art according to actual requirements. In this embodiment, the thickness of the epitaxial layer 12 is greater than the depth of the subsequently fabricated trench; in other embodiments, the thickness of the epitaxial layer 12 may be less than or equal to the depth of the subsequently formed trench.
Referring to fig. 2, the semiconductor substrate is doped to form a body region 13.
Specifically, the body region 13 is formed by implanting impurities into the epitaxial layer 12 and then annealing. In particular practice, the junction depth of the body region 13 is also increased by the subsequent thermal processing, so that the annealing after the ion implantation is not an essential step, and whether to perform the annealing or not and the annealing process can be adjusted according to actual process conditions. Of course, the junction depth of body region 13 should be less than the thickness of epitaxial layer 12. The doping impurities and the doping concentration used for doping the epitaxial layer 12 can be set according to actual requirements. In the specific implementation of the present invention, P-type impurities such as boron of an order of E12 or more are implanted into epitaxial layer 12 to form a P-type doped region as body region 13.
The conventional semiconductor process for manufacturing a power semiconductor device with a trench gate usually performs ion implantation and annealing after the trench gate structure is manufactured to form a body region, and this process easily causes that the device performance cannot reach the expectation, which may be due to: the ion implantation for manufacturing the P-type doped region can enable the oxide layer formed on the side wall of the groove to be implanted with certain impurities, and if the impurities are not properly processed, oxide layer fixed charges can be formed, so that the gate oxide function is degraded and the channel is induced to be pre-opened; when annealing is carried out after injection, due to the existence of the oxide layer on the side wall of the groove, the PN junction surface is bent by the segregation effect, and further, electric field concentration and channel shortening are caused. In the embodiment of the present application, the body region 13 is formed by performing ion implantation before the trench gate structure is fabricated, so that the above-mentioned problem can be avoided.
Referring to fig. 3, the body region 13 is etched to form a first trench 141 and a second trench 142.
Specifically, the body region 13 includes a Main Cell region (Main Cell region) and a Gate region (Gate region). A mask (not shown) is disposed on the surface of the body region 13 to define a trench formation region, and the body region 13 is anisotropically etched through a window in the mask to form a plurality of first trenches 141 in the main cell region and a plurality of second trenches 142 in the gate region. Wherein, the width of the first trench 141 is smaller than the width of the second trench 142.
In the implementation of the present application, the first trench 141 and the second trench 142 are both U-shaped trenches. The etching solution can be obtained by anisotropic etching means such as ion milling etching, plasma etching, reactive ion etching, laser ablation and the like, and is not particularly limited. The depth of the trench can be specifically adjusted by controlling the etching time and the etching rate.
Further, in order to avoid a tip problem of a subsequently formed trench gate structure, Rounding etching (Rounding Etch) may be performed on the first trench 141 and the second trench 142, so that inner walls of the first trench 141 and the second trench 142 are rounded.
The depth of the first trench 141 and the second trench 142 is greater than the junction depth of the body region 13. The depths of the first trench 141 and the second trench 142 are sufficiently increased to allow for the junction depth of the P-type doped region to be increased in a subsequent thermal process. In the present embodiment, the first trenches 141 and the second trenches 142 extend into the epitaxial layer 12 through the body region 13. In other embodiments, the depth of the first trench 141 and the second trench 142 may be set by those skilled in the art according to actual needs, for example, the bottom of the first trench 141 and the second trench 142 may reach the surface of the substrate 11 through the epitaxial layer 12 and even extend into the substrate 11.
Referring to fig. 4, a first insulating layer 151, a second insulating layer 152, and a third insulating layer 153 are grown.
Specifically, a thermal oxidation process, a chemical vapor deposition process, or the like may be employed to form the first insulating layer 151 on the inner wall of the first trench 141, the second insulating layer 152 on the inner wall of the second trench 142, and the third insulating layer 153 on the surface of the body region 13.
In an embodiment of the present application, the material of the insulating layer may include one of silicon oxide, silicon nitride, silicon oxynitride, and a high-K gate dielectric material. The thickness of the insulating layer can be set according to the threshold voltage requirement.
Referring to fig. 5, the first trench 141 and the second trench 142 are polysilicon-filled.
Specifically, the polysilicon may be formed by a CVD process, and may be doped by thermal diffusion, annealing after ion implantation, or the like. The doping to the polysilicon can adopt an in-situ doping process, namely the doping is completed simultaneously in the growth process of the polysilicon. The thickness of the polysilicon may be set according to actual requirements, as long as it is ensured that the first trench 141 and the second trench 142 are completely filled. Generally, the thickness of the polysilicon needs to be no less than half the width of the trench at its widest point. In addition, Chemical Mechanical Polishing (CMP) may also be performed on the polysilicon.
Referring to fig. 6, the polysilicon is etched back to form a first polysilicon 161 and a second polysilicon 162.
Specifically, a dry etching process, a wet etching process, or a dry-wet combined etching process may be used to perform polysilicon etching to expose the third insulating layer 153 on the surface of the body region 13, and to control the polysilicon surfaces in the first trench 141 and the second trench 142 to be lower than the surface of the body region 13. In the embodiment of the present application, the surface of the first polysilicon 161 and the surface of the second polysilicon 162 are in the same plane, and the distance between the surface of the body region 13 and the surface of the first polysilicon is greater than 1000 angstroms, which can be controlled to be about 4500 angstroms, for example. Note that, due to the presence of the first insulating layer 151 and the second insulating layer 152, the side surfaces of the body region 13 around the first trench 141 and the second trench 142 can be protected from etching back.
Referring to fig. 7, the surface of body region 13 around first trench 141 and the side of body region 13 are doped to form source region 17.
Specifically, a photoresist layer is formed on the surface of the gate region as a mask, and ion implantation is performed on the main cell region to form the source region 17. In the embodiment of the present application, N-type impurities such as arsenic with an order of magnitude of E15 or more are implanted into the body region 13 by a large-angle implantation method, and an included angle between an ion incident direction and a normal line of the body region 13 is 30 to 45 degrees. After the ion implantation is completed, the photoresist is removed, thereby forming source regions 17 on the surface of body region 13 around first trenches 141 and on the sides of body region 13. Note that, when the power semiconductor device to be formed is an IGBT, the source region 17 functions as an emitter region of the IGBT.
Referring to fig. 8, a fourth insulating layer 154 and a fifth insulating layer 155 are grown.
Specifically, after the ion implantation is completed, annealing or silicon oxide deposition is performed to form the fourth insulating layer 154 on the surface of the first polysilicon 161 and the fifth insulating layer 155 on the surface of the second polysilicon 162. The material of the fourth insulating layer 154 and the fifth insulating layer 155 may include one of silicon oxide, silicon nitride, silicon oxynitride, and a high-K gate dielectric layer.
Referring to fig. 9, a stop layer 18 is deposited on the surface of the third insulating layer 153, the surface of the fourth insulating layer 154, and the surface of the fifth insulating layer 155 to completely fill the first trench 141 and partially fill the second trench 142, thereby forming a third trench 143 in the second trench 142.
Specifically, the stop layer 18 may be deposited using an LPCVD process, which is characterized by the simultaneous growth of thin films on the sidewalls and bottom surface. The thickness of the stop layer 18 can be set according to actual requirements, as long as it is ensured that the first trench 141 is completely filled and the second trench 142 is partially filled. Generally, the thickness of the stop layer 18 is larger than half of the maximum width of the first trench 141 and smaller than half of the maximum width of the second trench 142. Since the width of the second trench 142 is generally enlarged during layout design to ensure sufficient registration margin for contact, the stop layer 18 deposited in the second trench 142 will not close, but will form a third trench 143.
In the embodiment of the present application, the material of the stop layer 18 is SiN. SiN is used as an etch stop layer to improve the tolerance of the subsequent hole etch process.
Referring to fig. 10, an interlayer dielectric layer 19 is deposited on the surface of the stop layer 18, and the interlayer dielectric layer 19 completely fills the third trench 143.
Specifically, a dielectric material that is flowable at a predetermined temperature (e.g., 800 ℃ to 1200 ℃) may be coated on the surface of the stop layer 18 by a sputtering deposition, a chemical vapor deposition, or a spin-on deposition, and the third trench 143 is filled with the fluidity of the dielectric material. The dielectric material may be any material capable of flowing at a certain temperature and serving as an insulating medium in the art, such as at least one of silicate glass, tetraethoxysilane, spin-on glass (SOG), and polymer material, wherein the silicate glass may include at least one of phosphosilicate glass (PSG), borosilicate glass (BSG), and borophosphosilicate glass (BPSG). By using the above dielectric material as a raw material for deposition, SiO can be formed2The layer serves as an interlevel dielectric layer 19.
Referring to fig. 11, the interlayer dielectric layer 19 is etched to expose the stop layer 18 directly above the first trench 141 and the stop layer 18 in the second trench 142.
Specifically, the interlayer dielectric layer 19 on the surface of the main cell region and a portion of the interlayer dielectric layer 19 in the gate region are fully etched by using a photoresist (not shown) as a mask and the stop layer 18 as an etching stop layer, so as to form openings with larger areas in the main cell region and the gate region, respectively, wherein the openings in the main cell region expose the stop layer 18 directly above the first trench 141 and on the surface of the surrounding body region 13, and the openings in the gate region expose at least the stop layer 18 on the sidewalls of the second trench 142 and on the surface of the fifth insulating layer 155.
Compared with the traditional process, the etching process does not need to use a DUV mask to manufacture hundreds of thousands or even millions of independent small holes in the main unit area to manufacture the metal plug, but uses a common photoetching machine to manufacture a large-area opening in the main unit area, and does not need to consider the alignment precision too much, so that the process difficulty of the device is reduced. Moreover, the opening of the gate region is larger than the width of the third trench 143, for example, the opening of the gate region is close to or the same as the maximum width of the second trench 142, and specifically may be about 0.5 μm or even larger, without considering the overlay accuracy too much.
Referring to fig. 12, the stop layer 18, the third insulating layer 153 and the fifth insulating layer 155 are etched to expose the surface of the body region 13 around the first trench 141, so as to leave the stop layer 18 in the first trench 141 as the capping structure 20, to form the sidewall structures 21 in the second trench 142, and to expose a portion of the surface of the second polysilicon 162.
Specifically, the etching of the stop layer 18 is continued to remove the stop layer 18 on the surface of the main cell region, exposing the surface of the body region 13 around the first trench 141, and the stop layer 18 in the first trench 141 serves as the covering structure 20 to protect the underlying first polysilicon 161. Due to the anisotropic etching, the etching rate along the etching direction (i.e. the vertical direction in the figure) is much higher than the lateral etching rate, so that the stop layer 18 on the sidewall of the second trench 142 is partially remained to form the sidewall structure 21, and the stop layer 18 on the surface of the fifth insulating layer 155 and the exposed fifth insulating layer 155 are completely etched, so as to correspondingly expose a portion of the second polysilicon 162. And after the etching is finished, removing the photoresist.
Because of the existence of the sidewall, the contact hole of the gate region forms a self-aligned structure, that is, when the contact hole layer (lithography) and the previous layer have registration deviation, the sidewall structure 21 protects the other regions of the gate region except the contact hole, prevents the etching atmosphere from damaging the semiconductor substrate, and only exposes part of the surface of the second polysilicon 162 to form the contact hole of the gate region.
Referring to fig. 13, the body region 13 around the first trench 141 and the second polysilicon 162 are etched to remove the source region 17 on the surface of the body region 13 around the first trench 141 and form a groove structure 22 on the second polysilicon 162.
Specifically, the interlayer dielectric layer 19 and the sidewall structures 21 are respectively used as hard masks, the body region 13 located in the main cell region and the second polysilicon 162 located in the gate region are etched, the etching depth is not less than the junction depth of the annealed source region 17, only the source region 17 on the side of the body region 13 around the first trench 141 is reserved, and the groove structures 22 are formed in the second polysilicon 162. After this etching, the surface of the first trench 142 is higher than the surface of the body region 13 around the first trench, i.e. the source region 17 of the cap structure 20 is higher than the side of the body region 13.
Referring to fig. 14, the surface of the body region 13 around the first trench 141 is doped to form a contact region 23 of the first doping type.
Specifically, the contact region 23 is located on a P-type doped region with a relatively low doping concentration, and therefore, in order to ensure ohmic contact and reduce contact resistance, boron implantation is generally performed at a dose of the order of E14. In the embodiment of the present application, the angle between the ion incidence direction and the normal of the body region 13 is not less than 7 degrees, for example, a large angle ion implantation is used, so that the concentration of the P-type lightly doped region on the exposed sidewall of the body region 13 is supplemented. Since the second polysilicon 162 is heavily N-doped, the effect of the boron implant on the order of E14 is negligible.
In order to form a complete power semiconductor device, after the contact region 23 is formed, an electrode structure also needs to be fabricated.
Referring to fig. 15, a barrier metal layer 24 is deposited over the entire device surface such that the recess 22 is partially filled. In the embodiment of the present application, the barrier metal layer 24 employs a combination of Ti and TiN. Wherein, Ti can form metal silicide with Si to reduce contact resistance, and TiN can block sharp pricks caused by alloy process.
Referring to fig. 16, a front metal layer 25 is deposited on the surface of the barrier metal layer 24 such that the recess 22 is completely filled. Due to the large area of the main cell region, it is easy to achieve sufficient contact of the barrier metal layer 24 with the source region 17, respectively the contact region 23. The gate region is typically located at the edge of the die where the design rules are broad, and the width of the trench and contact may be artificially increased to ensure that the metal filling the second trench 142 and the contact with the second polysilicon 162 are sufficient.
Referring to fig. 17, the front metal layer 25 and the barrier metal layer 24 are etched to form a first electrode structure and a second electrode structure, which are not in contact with each other. The first electrode structure covers at least the first trench 141, the source region 17 and the contact region 23, and the second electrode structure covers at least the second trench 142. When the formed power semiconductor device is an MOSFET, the electrode structures formed on the front surface are a source electrode and a grid electrode; when the formed power semiconductor device is an IGBT, the electrode structures formed on the front surface are an emitter and a gate. And after the patterning of the front metallization is finished, alloy treatment is carried out, a passivation layer covering the surface of the device can be manufactured according to the requirement, and the process for manufacturing the passivation layer is a conventional process and is not repeated.
Referring to fig. 18, when the formed power semiconductor device is a MOSFET, after forming an electrode structure on the front surface, the substrate 11 may be thinned, and a back metal layer 26 may be deposited on the back surface of the substrate 11, where the back metal layer 26 serves as a drain.
When the formed power semiconductor device is an IGBT, after an electrode structure is formed on the front surface, the substrate 11 is thinned, a PN junction is formed in the substrate 11, and finally, a back metal layer 26 is deposited on the back surface of the substrate 11, and the back metal layer 26 serves as a collector.
Fig. 19 is a schematic diagram of a partial layout of a power semiconductor device with a trench gate manufactured by a conventional semiconductor process, which is shown as a plurality of square cell arrays, wherein a trench gate structure is formed between adjacent cells, each cell has an independent small-sized contact hole, and all source contact holes and all gate contact holes are connected in parallel by metal electrodes that are not connected to each other; fig. 20 is a schematic layout diagram of a power semiconductor device with a trench gate, which is manufactured by using the process provided in the embodiment of the present application. Comparing fig. 19 and fig. 20, with the method for manufacturing a power semiconductor device according to the embodiment of the present application, by retaining the stop layer in the first trench 141 as the capping structure 20 and forming the source region 17 at the side of the body region 13 around the first trench 141, the body region 13 around the first trench 141 may not be connected to the front metal layer 25 through a plurality of small-sized contact holes, but the leading-out of the electrode may be realized by uniformly manufacturing a conductive layer.
Because small-sized contact holes do not need to be manufactured independently, the harsh requirements of device preparation on high-end semiconductor equipment, particularly high-precision photoetching machines, are reduced, or the dependence on the high-precision photoetching machines is reduced. For example, a conventional semiconductor process is used to manufacture a power semiconductor device having a trench gate, and if the size of the contact hole is 350nm to 250nm, a DUV-KrF lithography machine is generally used, and the wavelength of the light source is 248 nm; if the size of the contact hole is 250nm to 180nm, a DUV-ArF lithography machine is generally used, and the wavelength of the light source is 193 nm. By adopting the preparation method of the power semiconductor device provided by the embodiment of the application, only an i-Line photoetching machine is needed, the wavelength of a light source is 365nm, and the size of a processing key feature is more than 0.4 mu m.
Moreover, the process requirement of the large-size contact hole on the metalized filling hole is reduced, and high-cost manufacturing processes such as metal plugs, CMP planarization and the like are not needed; furthermore, the reliability of a single large-sized contact hole is much higher than that of a plurality of small-sized contact holes. Therefore, the preparation method of the power semiconductor device provided by the embodiment of the application can reduce the difficulty of process control, improve the yield and reduce the manufacturing cost.
Further, the front metal layer 25 and the first polysilicon 161 are equivalent to two plates of a capacitor, and when the connection mode of the source is changed, the distance between the source and the first polysilicon 161 is inevitably shortened, which may cause the increase of the gate-source parasitic capacitance. In the embodiment of the present invention, the stop layer in the first trench 141 is reserved as the capping structure 20, so that the distance between the two plates of the capacitor is increased in a phase-change manner, and the gate-source parasitic capacitance is reduced. The power semiconductor device is mostly applied as a switch, and for a switching element, the size of the capacitor directly affects the switching speed. The input capacitance of the device is the sum of the grid source capacitance and the grid drain capacitance, and the grid drain capacitance cannot be changed in the embodiment of the application, so that the input capacitance is reduced by reducing the grid source capacitance, and the switching speed of the device is further improved.
In addition, when the contact region 23 is formed by implantation, the isolation effect of the capping structure 20 can prevent the doping concentration on the surface of the polysilicon gate (i.e., the first polysilicon 161) from being reduced due to the influence of the inversion implantation doping, thereby preventing the gate resistance from being abnormally increased, and thus improving the device performance and ensuring the stability of the device parameters.
Moreover, since the cover structure 20 is higher than the source region 17 on the side of the body region 13 around the first trench 141, when the contact region 23 is formed by injection, the shadow effect of the cover structure 20 can be used to prevent the doping concentration of the source region 17 from being reduced by inversion injection doping, thereby preventing the abnormal rise of the source resistance, further improving the performance of the device, and ensuring the stability of the parameters of the device. Through further research and practice, the height a of the capping structure 20 above the surface of the source region 17 is preferably greater than or equal to the width b of the source region 17 (as shown in fig. 14), but if the capping structure 20 is too high above the surface of the source region 17, the shadow effect is too significant, which results in discontinuity of the contact region 23, resulting in increased contact resistance and impaired device performance. Therefore, in the implementation of the present application, the ratio of the height a of the capping structure 20 beyond the surface of the source region 17 to the width b of the source region 17 is generally controlled to be 1:1 to 10:1, so as to optimize the device performance.
In a second aspect, embodiments of the present application provide a semiconductor device, which may be a power semiconductor device having a trench gate, such as a MOSFET or an IGBT. Fig. 18 is a schematic structural diagram of a power semiconductor device provided in an embodiment of the present application, where the power semiconductor device includes:
a semiconductor substrate;
a body region 13 extending from the semiconductor substrate surface into the semiconductor substrate, the body region 13 including a first region and a second region;
a first groove penetrating through the first region, wherein a first insulating layer 151 is arranged on the inner wall of the first groove, the first insulating layer 151 exceeds the surface of the first region, first polycrystalline silicon 161, a fourth insulating layer 154 and a covering structure 20 are sequentially arranged in the first groove from bottom to top, the surface of the fourth insulating layer 154 is lower than the surface of the first region, a source region 17 is arranged on the side surface of a body region 13 around the first groove, the doping type of the source region 17 is opposite to that of the body region 13, a contact region 23 is arranged on the surface of the body region 13 around the first groove, and the doping type of the contact region 23 is the same as that of the body region 13;
a second groove penetrating through the second region, wherein the width of the second groove is greater than that of the first groove, a second insulating layer 152 is arranged on the inner wall of the second groove, and a second polysilicon 162 with a groove structure, a fifth insulating layer 155 positioned on the top surface of the groove structure and a sidewall structure 21 positioned on the surface of the fifth insulating layer 155 are sequentially arranged in the second groove from bottom to top;
a third insulating layer 153 on the surface of the second region;
a stop layer 18 on the surface of the third insulating layer 153;
and an interlayer dielectric layer 19 on the surface of the stop layer 18.
Specifically, different types of power semiconductor devices correspond to different semiconductor substrates. If the power semiconductor device provided by the embodiment of the application is the MOSFET, the semiconductor substrate can be an epitaxial wafer; if the power semiconductor device provided in the embodiment of the present application is an IGBT, the semiconductor substrate may be an epitaxial wafer or a single wafer. Taking an epitaxial wafer as an example of a semiconductor substrate, the epitaxial wafer includes a substrate 11 and an epitaxial layer 12 on a surface of the substrate 11. The epitaxial wafer may be obtained commercially, or may be obtained by depositing the epitaxial layer 12 on the surface of the substrate 11 by using a chemical vapor deposition process, a physical vapor deposition process, or the like.
The doping types of the substrate 11 and the epitaxial layer 12 are not particularly limited in the embodiments of the present application. Generally, if the power semiconductor device is a MOSFET, the doping types of the substrate 11 and the epitaxial layer 12 are the same, for example, both the substrate 11 and the epitaxial layer 12 are doped N-type or both are doped P-type; if the power semiconductor device is an IGBT, the doping types of the substrate 11 and the epitaxial layer 12 may be different, for example, the substrate 11 is doped P-type, and the epitaxial layer 12 is doped N-type. The embodiments of the present application are not limited thereto, and the doping types of the two can be controlled according to the actual device type and parameter requirements.
In the power semiconductor device, the doping concentration of the substrate 11 is generally controlled to be greater than that of the epitaxial layer 12. The present invention is not limited thereto and the doping concentrations of both may be controlled according to the actual device type and parameter requirements.
In addition, the larger the thickness of the epitaxial layer 12, the more favorable the breakdown voltage of the device, especially in an IGBT, but the less favorable the miniaturization of the device. The thickness of the substrate 11 and the epitaxial layer 12 can be determined by those skilled in the art according to actual requirements. In this embodiment, the thickness of the epitaxial layer 12 is greater than the depth of the trench; in other embodiments, the thickness of the epitaxial layer 12 may also be less than or equal to the trench depth.
The doping type and doping concentration of the body region 13 can be set according to actual requirements. In the embodiment of the present application, the body region 13 is doped P-type. The junction depth of the body region 13 can be set according to actual requirements, as long as the junction depth of the body region 13 is ensured to be smaller than the thickness of the epitaxial layer 12. The first region of the body region 13 is a main cell region, the second region of the body region 13 is a gate region, and the surface of the first region is lower than the surface of the second region.
The first trench is a trench of the main cell region, and the second trench is a trench of the gate region. In the present embodiment, the depth of the first and second trenches is greater than the junction depth of body region 13, i.e. the first and second trenches extend through body region 13 into epitaxial layer 12. Of course, the embodiments of the present application do not limit this, and those skilled in the art may make other settings on the depths of the first trench and the second trench according to actual needs, for example, the bottoms of the first trench and the second trench may reach the surface of the substrate 11 through the epitaxial layer 12, and even extend into the substrate 11. Further, the bottoms of the first groove and the second groove are of smooth structures.
In the embodiment of the present application, the materials of the first insulating layer 151, the second insulating layer 152, the third insulating layer 153, the fourth insulating layer 154, and the fourth insulating layer 154 may be the same, and may be selected from one of silicon oxide, silicon nitride, silicon oxynitride, and a high-K gate dielectric layer, for example.
In the embodiment of the present application, the material of the capping structure 20, the sidewall structure 21 and the stop layer 18 may be the same, and may be SiN, for example. The height of the cover structure 20 can be set according to actual requirements, and in the embodiment of the present application, the surface of the cover structure 20 and the surface of the second area are in the same plane. Further, the ratio of the height of the covering structure 20 beyond the surface of the first region to the width of the source region 17 is 1: 1-10: 1.
In the embodiment of the present application, the material of the interlayer dielectric layer 19 may be SiO2。
Further, the power semiconductor device provided by the embodiment of the present application further includes: a first electrode structure at least covering the first trench, the source region 17 and the contact region 23, the first electrode structure including a first barrier metal layer 241 and a first front metal layer 251 on the surface of the first barrier metal layer 241; and a second electrode structure at least covering the second trench, the second electrode structure including a second barrier metal layer 242 and a second front metal layer 252 on the surface of the second barrier metal layer 242, the second electrode structure and the first electrode structure not contacting each other.
Specifically, if the power semiconductor device provided in the embodiment of the present application is a MOSFET, the first electrode structure and the second electrode structure are a source and a gate, respectively; if the power semiconductor device provided by the embodiment of the application is an IGBT, the first electrode structure and the second electrode structure are an emitter and a gate, respectively. In the embodiment of the present application, the first barrier metal layer 241 and the second barrier metal layer 242 use a combination of Ti and TiN.
Further, the power semiconductor device provided by the embodiment of the present application further includes: a back metal layer 26 on the back side of the semiconductor substrate. If the power semiconductor device provided by the embodiment of the present application is a MOSFET, the back metal layer 26 serves as a drain; if the power semiconductor device provided in the embodiment of the present application is an IGBT, the back metal layer 26 serves as a collector. In addition, for the IGBT, the device structure thereof further includes a PN junction located in the semiconductor substrate.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A method for manufacturing a power semiconductor device, comprising:
forming a trench gate MOS structure in a semiconductor substrate, the trench gate MOS structure comprising: a body region of a first doping type extending into the semiconductor substrate from the semiconductor substrate surface; a first trench and a second trench penetrating the body region, a width of the second trench being greater than a width of the first trench; the first insulating layer is positioned on the inner wall of the first groove; the second insulating layer is positioned on the inner wall of the second groove; a third insulating layer on the surface of the body region; first polysilicon filled in the first trench; a second polysilicon filled in the second trench, the first polysilicon surface and the second polysilicon surface being lower than the body region surface; a source region of a second doping type located on the surface of the body region and on the side face of the body region around the first trench, wherein the second doping type is opposite to the first doping type; a fourth insulating layer on the surface of the first polysilicon; a fifth insulating layer on the second polysilicon surface;
depositing a stop layer to completely fill the first trench and partially fill the second trench to form a third trench within the second trench;
depositing an interlayer dielectric layer on the surface of the stop layer, wherein the interlayer dielectric layer completely fills the third groove;
etching the interlayer dielectric layer, the stop layer, the third insulating layer and the fifth insulating layer to expose the body region surface around the first trench, so as to reserve the stop layer in the first trench as a covering structure, to form a side wall structure in the second trench and to expose part of the surface of the second polysilicon;
etching the body region around the first groove and the second polysilicon to remove the source region on the surface of the body region around the first groove and form a groove structure on the second polysilicon;
and doping the surface of the body region around the first groove to form a contact region of a first doping type.
2. The method of claim 1, wherein forming a trench-gate MOS structure in a semiconductor substrate comprises:
doping the semiconductor substrate to form the body region;
etching the body region to form the first trench and the second trench;
growing the first insulating layer, the second insulating layer, and the third insulating layer;
filling and etching back the first trench and the second trench with polysilicon to form the first polysilicon and the second polysilicon correspondingly;
doping the surface and the side face of the body region around the first groove to form the source region;
growing the fourth insulating layer and the fifth insulating layer.
3. The method of claim 2, wherein doping the body surface and the body side around the first trench to form the source region comprises:
and carrying out ion implantation on the body region, wherein an included angle between the ion incidence direction and the normal of the body region is 30-45 degrees.
4. The method according to claim 1, wherein etching the interlayer dielectric layer, the stop layer, the third insulating layer, and the fifth insulating layer comprises:
etching the interlayer dielectric layer to expose the stop layer positioned right above the first groove and the stop layer positioned in the second groove;
and etching the stop layer, the third insulating layer and the fifth insulating layer to expose the surface of the body region around the first trench, reserving the stop layer in the first trench as a covering structure, forming a side wall structure in the second trench, and exposing part of the surface of the second polysilicon.
5. The method according to any one of claims 1 to 4, further comprising, after doping the surface of the body region around the first trench:
sequentially depositing a barrier metal layer and a front metal layer on the surface of the whole device;
and etching the front metal layer and the barrier metal layer to form a first electrode structure and a second electrode structure, wherein the first electrode structure at least covers the first groove, the source region and the contact region, and the second electrode structure at least covers the second groove.
6. The method of manufacturing according to claim 5, further comprising:
thinning the semiconductor substrate;
and depositing a back metal layer on the back of the thinned semiconductor substrate.
7. A power semiconductor device, comprising:
a semiconductor substrate;
a body region extending from the semiconductor substrate surface into the semiconductor substrate, the body region including a first region and a second region;
a first groove penetrating through the first area, wherein a first insulating layer is arranged on the inner wall of the first groove, the first insulating layer exceeds the surface of the first area, first polycrystalline silicon, a fourth insulating layer and a covering structure are sequentially arranged in the first groove from bottom to top, the surface of the fourth insulating layer is lower than the surface of the first area, a source area is arranged on the side surface of a body area around the first groove, the doping type of the source area is opposite to that of the body area, a contact area is arranged on the surface of the body area around the first groove, and the doping type of the contact area is the same as that of the body area;
a second groove penetrating through the second region, wherein the width of the second groove is larger than that of the first groove, a second insulating layer is arranged on the inner wall of the second groove, and a second polycrystalline silicon with a groove structure, a fifth insulating layer positioned on the top surface of the groove structure and a side wall structure positioned on the surface of the fifth insulating layer are sequentially arranged in the second groove from bottom to top;
a third insulating layer positioned on the surface of the second area;
the stop layer is positioned on the surface of the third insulating layer;
and the interlayer dielectric layer is positioned on the surface of the stop layer.
8. The power semiconductor device of claim 7, wherein the first area surface is lower than the second area surface, and wherein the surface of the cap structure and the second area surface are in the same plane.
9. The power semiconductor device according to claim 7 or 8, wherein the ratio of the height of the covering structure beyond the surface of the first region to the width of the source region is 1: 1-10: 1.
10. The power semiconductor device of claim 7, further comprising:
a first electrode structure at least covering the first trench, the source region and the contact region, the first electrode structure including a first barrier metal layer and a first front metal layer on the surface of the first barrier metal layer;
and the second electrode structure at least covers the second groove, the second electrode structure comprises a second barrier metal layer and a second front metal layer positioned on the surface of the second barrier metal layer, and the second electrode structure is not in contact with the first electrode structure.
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| CN114242596A (en) * | 2022-02-28 | 2022-03-25 | 深圳市美浦森半导体有限公司 | MOSFET device and manufacturing method thereof |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1536630A (en) * | 2003-04-03 | 2004-10-13 | 精工电子有限公司 | Method for mfg. vertical MOS transistor |
| CN103413765A (en) * | 2013-08-27 | 2013-11-27 | 矽力杰半导体技术(杭州)有限公司 | Groove MOSFET device and manufacturing method thereof |
| CN103730497A (en) * | 2012-10-16 | 2014-04-16 | 深圳市力振半导体有限公司 | Structure of chip scale package power device |
| CN104008975A (en) * | 2014-06-09 | 2014-08-27 | 苏州东微半导体有限公司 | Manufacturing method of groove-type power MOS transistor |
| CN107204372A (en) * | 2017-07-19 | 2017-09-26 | 无锡新洁能股份有限公司 | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure |
| CN107527944A (en) * | 2017-07-28 | 2017-12-29 | 上海华虹宏力半导体制造有限公司 | Groove power MOSFET and its manufacture method |
| CN109216193A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | Semiconductor devices and preparation method thereof |
| CN109830441A (en) * | 2019-01-30 | 2019-05-31 | 深圳市美浦森半导体有限公司 | A kind of preparation method of CFET technique MOSFET |
| EP3651202A1 (en) * | 2018-11-09 | 2020-05-13 | Infineon Technologies Austria AG | Semiconductor device with superjunction and oxygen inserted si-layers |
| CN111403282A (en) * | 2020-01-02 | 2020-07-10 | 杭州士兰微电子股份有限公司 | Trench gate MOSFET power semiconductor device and polysilicon filling method and manufacturing method thereof |
| CN112117332A (en) * | 2020-11-02 | 2020-12-22 | 上海华虹宏力半导体制造有限公司 | LDMOS device and technological method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100441682B1 (en) * | 2001-06-14 | 2004-07-27 | 삼성전자주식회사 | Semiconductor device having LDD-type source/drain regions and fabrication method thereof |
| GB0117949D0 (en) * | 2001-07-24 | 2001-09-19 | Koninkl Philips Electronics Nv | Trench-gate semiconductor devices and their manufacture |
| US7381603B2 (en) * | 2005-08-01 | 2008-06-03 | Semiconductor Components Industries, L.L.C. | Semiconductor structure with improved on resistance and breakdown voltage performance |
| US7786528B2 (en) * | 2009-01-14 | 2010-08-31 | Force Mos Technology Co., Ltd. | Metal schemes of trench MOSFET for copper bonding |
| US11049956B2 (en) * | 2019-06-17 | 2021-06-29 | Semiconductor Components Industries, Llc | Method of forming a semiconductor device |
-
2020
- 2020-12-31 CN CN202011637491.2A patent/CN112820645B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1536630A (en) * | 2003-04-03 | 2004-10-13 | 精工电子有限公司 | Method for mfg. vertical MOS transistor |
| CN103730497A (en) * | 2012-10-16 | 2014-04-16 | 深圳市力振半导体有限公司 | Structure of chip scale package power device |
| CN103413765A (en) * | 2013-08-27 | 2013-11-27 | 矽力杰半导体技术(杭州)有限公司 | Groove MOSFET device and manufacturing method thereof |
| CN104008975A (en) * | 2014-06-09 | 2014-08-27 | 苏州东微半导体有限公司 | Manufacturing method of groove-type power MOS transistor |
| CN109216193A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | Semiconductor devices and preparation method thereof |
| CN107204372A (en) * | 2017-07-19 | 2017-09-26 | 无锡新洁能股份有限公司 | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure |
| CN107527944A (en) * | 2017-07-28 | 2017-12-29 | 上海华虹宏力半导体制造有限公司 | Groove power MOSFET and its manufacture method |
| EP3651202A1 (en) * | 2018-11-09 | 2020-05-13 | Infineon Technologies Austria AG | Semiconductor device with superjunction and oxygen inserted si-layers |
| CN109830441A (en) * | 2019-01-30 | 2019-05-31 | 深圳市美浦森半导体有限公司 | A kind of preparation method of CFET technique MOSFET |
| CN111403282A (en) * | 2020-01-02 | 2020-07-10 | 杭州士兰微电子股份有限公司 | Trench gate MOSFET power semiconductor device and polysilicon filling method and manufacturing method thereof |
| CN112117332A (en) * | 2020-11-02 | 2020-12-22 | 上海华虹宏力半导体制造有限公司 | LDMOS device and technological method |
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|---|---|
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