CN213816161U

CN213816161U - Semiconductor device with groove type grid

Info

Publication number: CN213816161U
Application number: CN202023318337.7U
Authority: CN
Inventors: 周源; 方宇; 王超; 朱林迪; 常东旭; 梁维佳
Original assignee: Beijing Yandong Microelectronic Technology Co ltd
Current assignee: Beijing Yandong Microelectronic Technology Co ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-07-27
Anticipated expiration: 2030-12-31

Abstract

The embodiment of the present application provides a semiconductor device having a trench gate, the semiconductor device including: a semiconductor substrate; the semiconductor substrate comprises a body area in the semiconductor substrate, wherein the body area comprises a first area and a second area, and a first insulating layer, a stop layer and an interlayer dielectric layer are sequentially arranged on the surface of the second area; the first groove penetrates through the first area and extends into the semiconductor substrate, a second insulating layer is arranged on the inner wall of the first groove, and first polycrystalline silicon, a fourth insulating layer and a covering structure are sequentially arranged in the first groove from bottom to top; a second trench sequentially penetrating through the first insulating layer and the second region and extending into the semiconductor substrate, the second trench being completely filled with second polysilicon; sequentially penetrates through the interlayer dielectric layer, the stop layer and the fifth insulating layer and extends to the contact hole in the second polysilicon. By adopting the scheme in the application, the electrodes are led out through one conducting layer, so that the process control difficulty can be reduced, the yield is improved, and the manufacturing cost is reduced.

Description

Semiconductor device with groove type grid

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to a semiconductor device having a trench gate.

Background

The power Semiconductor device is a basic electronic component for energy conversion and control of a power electronic system, the continuous development of the power electronic technology opens up a wide application Field for the power Semiconductor device, and the power Semiconductor device marked by Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and Insulated Gate Bipolar Transistor (IGBT) is the mainstream in the Field of the power electronic device at present.

The gate structures of MOSFETs and IGBTs include a trench type and a planar type. The trench gate is usually formed by growing a gate oxide layer on the sidewall of the trench and filling polysilicon, and this gate structure improves the utilization efficiency of the planar area of the power semiconductor device, so that the available channel width and current density per unit area are larger, and the device obtains larger current conduction capability, therefore, the power semiconductor device with the trench gate has been widely applied to various fields such as motor speed regulation, inverters, power supplies, electronic switches, audio devices, automobile electric appliances, and the like.

The mainstream power semiconductor devices with trench type gates are designed by repeating and finally connecting a plurality of cells in parallel according to a certain step pitch. Driven by moore's law, the number of cells per unit area ultimately determines the performance of the device, and thus it is necessary to reduce the size of the trenches and contact holes as much as possible to reduce the size of the cells as much as the fabrication capability allows. The smaller step size places higher demands on the equipment, such as the use of a deep ultraviolet lithography tool with a 248nm or shorter wavelength light source to etch process-sized trenches and contact holes when etching trenches and contact holes. In addition, the step pitch is reduced, and the two-time photoetching patterns for preparing the grooves and the contact holes are required to have higher alignment precision, so that the problems of high process control difficulty, reduced yield, high manufacturing cost and the like are caused.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a semiconductor device with a groove type grid, which is used for solving the problems of high process control difficulty, yield reduction and high manufacturing cost of a power semiconductor device.

An embodiment of the present application provides a semiconductor device having a trench gate, including:

a semiconductor substrate;

the semiconductor substrate comprises a body region extending from the surface of the semiconductor substrate to the inside of the semiconductor substrate, wherein the body region comprises a first region and a second region, and a first insulating layer, a stop layer and an interlayer dielectric layer are sequentially arranged on the surface of the second region;

the first groove penetrates through the first region and extends into the semiconductor substrate, a second insulating layer is arranged on the inner wall of the first groove, the second insulating layer exceeds the surface of the first region, first polycrystalline silicon, a fourth insulating layer and a covering structure are sequentially arranged in the first groove from bottom to top, the surface of the fourth insulating layer is lower than the surface of the first region, a source region is arranged on the side face of a body region around the first groove, the doping type of the source region is opposite to that of the body region, a contact region is arranged on the surface of the body region around the first groove, and the doping type of the contact region is the same as that of the body region;

the second groove penetrates through the first insulating layer and the second region in sequence and extends into the semiconductor substrate, the width of the second groove is larger than that of the first groove, a third insulating layer is arranged on the inner wall of the second groove, the second groove is completely filled with second polycrystalline silicon, and a fifth insulating layer is arranged on the surface of the second polycrystalline silicon;

sequentially penetrates through the interlayer dielectric layer, the stop layer and the fifth insulating layer and extends to the contact hole in the second polysilicon.

Further, the surface of the first area is lower than the surface of the second area, and the surface of the cover structure and the surface of the second area are in the same plane.

Further, the ratio of the height of the covering structure beyond the surface of the first area to the width of the source region is 1: 1-10: 1.

further, the width of the contact hole is smaller than that of the second trench.

Further, the capping structure and the stop layer are both silicon nitride layers.

Furthermore, the first insulating layer, the second insulating layer and the third insulating layer are all silicon oxide layers, silicon nitride layers, silicon oxynitride layers or high-K gate dielectric material layers;

the fourth insulating layer and the fifth insulating layer are silicon oxide layers, silicon nitride layers, silicon oxynitride layers or high-K gate dielectric material layers.

Furthermore, the interlayer dielectric layer is a silicon dioxide layer.

Further, the semiconductor device having the trench gate described above further includes:

the first electrode structure at least covers the covering structure, the source region and the contact region, the first electrode structure comprises a first barrier metal layer and a first front metal layer, the first barrier metal layer is positioned on the surface of the covering structure, the surface of the source region and the surface of the contact region, and the first front metal layer is positioned on the surface of the first barrier metal layer;

and the second electrode structure at least fills the contact hole, and comprises a second barrier metal layer and a second front metal layer, wherein the second barrier metal layer is positioned on the inner wall of the contact hole, and the second front metal layer is positioned on the surface of the second barrier metal layer.

and a back metal layer on the back of the semiconductor substrate.

a PN junction located within the semiconductor substrate.

By adopting the semiconductor device with the trench type gate provided in the embodiment of the present application, the covering structure is arranged above the first polysilicon in the first trench in the main cell region, and the source region is arranged on the side surface of the body region around the first trench, so that the body region around the first trench can be connected with the front metal layer not through a plurality of small-sized contact holes, but through one conductive layer, the extraction of the electrode is realized. Because small-sized contact holes do not need to be manufactured independently, the harsh requirements of device preparation on high-end semiconductor equipment, particularly high-precision photoetching machines, are reduced, or the dependence on the high-precision photoetching machines is reduced. Moreover, the process requirement of the large-size contact hole on the metalized filling hole is reduced, and high-cost manufacturing processes such as metal plugs, CMP planarization and the like are not needed; the reliability of a single large-sized contact hole is much higher than that of a plurality of small-sized contact holes. Therefore, the semiconductor device with the trench type grid electrode provided by the embodiment of the application is low in process difficulty, high in yield and low in manufacturing cost.

On the basis, due to the existence of the covering structure, the distance between the first front metal layer and the first polycrystalline silicon is increased, so that the grid-source capacitance can be reduced, namely the input capacitance is reduced, and the switching speed of the power semiconductor device can be improved. In addition, when the contact region is formed by injection, the doping concentration on the surface of the polysilicon gate can be prevented from being reduced due to the influence of inversion injection doping by utilizing the isolation effect of the covering structure, and the abnormal rise of the resistance of the gate can be further prevented, so that the performance of a device can be improved, and the stability of parameters of the device can be guaranteed. In addition, because the covering structure is higher than the source region on the side face of the body region around the first groove, when the source region is formed by injection, the shadow effect of the covering structure is utilized, the phenomenon that the doping concentration of the source region is reduced by inversion injection doping can be avoided, the abnormal rise of the source resistance is avoided, the performance of the device can be further improved, and the stability of the parameters of the device is ensured.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

fig. 1 is a schematic structural diagram of a semiconductor device having a trench gate according to an embodiment of the present application;

fig. 2 to 14 are schematic device structures in steps of manufacturing a semiconductor device having a trench gate according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present application clearer, the following describes exemplary embodiments of the present application in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all the embodiments.

In a first aspect, embodiments of the present application provide a semiconductor device with a trench gate, which may be a semiconductor device with a trench gate, such as a MOSFET, an IGBT, or the like. Fig. 1 is a schematic structural diagram of a semiconductor device with a trench gate according to an embodiment of the present disclosure, where the semiconductor device with a trench gate includes a semiconductor substrate, a body region 13, a first trench, a second trench, and a contact hole 21, and a width of the second trench is greater than a width of the first trench.

Specifically, different types of semiconductor devices having trench-type gates correspond to different semiconductor substrates. If the semiconductor device with the trench-type gate provided by the embodiment of the application is a MOSFET, the semiconductor substrate can be an epitaxial wafer; if the semiconductor device with the trench gate provided in the embodiment of the present application is an IGBT, the semiconductor substrate may be an epitaxial wafer or a single wafer. Taking an epitaxial wafer as an example of a semiconductor substrate, the epitaxial wafer includes a substrate 11 and an epitaxial layer 12 on a surface of the substrate 11. The epitaxial wafer may be obtained commercially, or may be obtained by depositing the epitaxial layer 12 on the surface of the substrate 11 by a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process.

In the embodiments of the present application, the doping types of the substrate 11 and the epitaxial layer 12 are not particularly limited. In general, if the semiconductor device having the trench gate is a MOSFET, the doping types of the substrate 11 and the epitaxial layer 12 are the same, for example, the substrate 11 and the epitaxial layer 12 are both N-type doped or both P-type doped; if the semiconductor device having the trench gate is an IGBT, the doping types of the substrate 11 and the epitaxial layer 12 may be different, for example, the substrate 11 is doped P-type, and the epitaxial layer 12 is doped N-type. The embodiments of the present application are not limited thereto, and the doping types of the two can be controlled according to the actual device type and parameter requirements.

In a semiconductor device having a trench-type gate, the doping concentration of the substrate 11 is generally controlled to be greater than that of the epitaxial layer 12. However, the present invention is not limited thereto, and the doping concentration of the two can be controlled according to the actual device type and parameter requirement.

In addition, the larger the thickness of the epitaxial layer 12, the more favorable the breakdown voltage of the device, especially in an IGBT, but the less favorable the miniaturization of the device. The thickness of the substrate 11 and the epitaxial layer 12 can be determined by those skilled in the art according to actual requirements. In this embodiment, the thickness of the epitaxial layer 12 is greater than the depth of the trench; in other embodiments, the thickness of the epitaxial layer 12 may also be less than or equal to the trench depth.

The body region 13 extends from the surface of the semiconductor substrate into the semiconductor substrate. The doping type and doping concentration of the body region 13 can be set according to actual requirements. In the embodiment of the present application, the body region 13 is doped P-type. The junction depth of the body region 13 can be set according to actual requirements, as long as the junction depth of the body region 13 is ensured to be smaller than the thickness of the epitaxial layer 12.

The body region 13 includes a first region and a second region. The first region is a Main Cell (Main Cell) region, the second region is a Gate (Gate) region, and a first insulating layer 151, a stop layer 18, and an interlayer dielectric layer 19 are sequentially disposed on the surface of the second region from bottom to top. In an embodiment of the application, the surface of the first region is lower than the surface of the second region.

The first trench passes through the first region and extends into the semiconductor substrate. The inner wall of the first trench is provided with a second insulating layer 152, and the second insulating layer 152 exceeds the surface of the first region. The first polysilicon 161, the fourth insulating layer 154 and the cover structure 20 are sequentially disposed in the first trench from bottom to top, and the surface of the fourth insulating layer 154 is lower than the surface of the first region. The side of the body region 13 around the first trench is provided with a source region 17, and the doping type of the source region 17 is opposite to that of the body region 13. The surface of the body region 13 around the first trench is provided with a contact region 22, and the doping type of the contact region 22 is the same as the doping type of the body region 13.

The second trench sequentially passes through the first insulating layer 151 and the second region and extends into the semiconductor substrate. The inner wall of the second trench is provided with a third insulating layer 153, the second trench 153 is completely filled with second polysilicon 162, and the surface of the second polysilicon 162 is provided with a fifth insulating layer 155.

The first trench is a trench of the main cell region, and the second trench is a trench of the gate region. In the embodiment of the present application, the depth of the first trench is greater than the junction depth of the first region, and the depth of the second trench is greater than the junction depth of the second region, i.e., both the first trench and the second trench extend through the body region 13 into the epitaxial layer 12. Of course, the embodiments of the present application do not limit this, and those skilled in the art may make other settings on the depths of the first trench and the second trench according to actual needs, for example, the first trench and the second trench may extend to the surface of the substrate 11, and even extend into the substrate 11. Further, the bottoms of the first groove and the second groove are of smooth structures.

The contact hole 21 sequentially passes through the interlayer dielectric layer 19, the stop layer 18 and the fifth insulating layer 155 and extends into the second polysilicon 162. In the embodiment of the present application, the width of the contact hole 21 is smaller than the width of the second trench.

In the embodiment of the present application, the first insulating layer 151, the second insulating layer 152, the third insulating layer 153, the fourth insulating layer 154, and the fourth insulating layer 154 are all silicon oxide layers, all silicon nitride layers, all silicon oxynitride layers, or all high-K gate dielectric material layers.

In the present embodiment, the capping structure 20 and the stop layer 18 are both SiN layers. The height of the cover structure 20 can be set according to actual requirements, and in the embodiment of the present application, the surface of the cover structure 20 and the surface of the second area are in the same plane.

In the embodiment of the present application, the interlayer dielectric layer 19 may be SiO₂And (3) a layer.

Further, the semiconductor device with the trench gate provided by the embodiment of the present application further includes a first electrode structure and a second electrode structure, and the second electrode structure is not in contact with the first electrode structure.

The first electrode structure covers at least the cover structure 20, the source region 17 and the contact region 22. The first electrode structure includes a first barrier metal layer 231 and a first front metal layer 241, the first barrier metal layer 231 is located on the surface of the cover structure 20, the surface of the source region 17 and the surface of the contact region 22, and the first front metal layer 241 is located on the surface of the first barrier metal layer 231. In the embodiment of the present application, the first electrode structure may also cover a portion of the surface of the interlayer dielectric layer 19.

The second electrode structure fills at least the contact hole 21. The second electrode structure includes a second barrier metal layer 232 and a second front metal layer 242, the second barrier metal layer 232 is located on the inner wall of the contact hole 21, and the second front metal layer 242 is located on the surface of the second barrier metal layer 232. In the embodiment of the present application, the second electrode structure may also cover a portion of the surface of the interlayer dielectric layer 19.

In the embodiment of the present application, the material of the first barrier metal layer 231 and the material of the second barrier metal layer 232 may adopt a combination of Ti and TiN. Wherein, Ti can form metal silicide with Si to reduce contact resistance, and TiN can block sharp pricks caused by alloy process.

If the semiconductor device with the trench-type gate provided by the embodiment of the application is a MOSFET, the first electrode structure and the second electrode structure are a source electrode and a gate electrode respectively; if the semiconductor device with the trench gate provided in the embodiment of the present application is an IGBT, the first electrode structure and the second electrode structure are an emitter and a gate, respectively.

Further, the semiconductor device with the trench gate provided by the embodiment of the present application further includes: and a back metal layer 25 on the back surface of the semiconductor substrate. If the semiconductor device with the trench gate provided in the embodiment of the present application is a MOSFET, the back metal layer 25 serves as a drain; if the semiconductor device with the trench gate provided in the embodiment of the present application is an IGBT, the back metal layer 25 serves as a collector. In addition, for the IGBT, the device structure thereof further includes a PN junction located in the semiconductor substrate.

In the semiconductor device with the trench-type gate provided in the embodiment of the present application, the cover structure 20 is disposed in the first trench, and the source region 17 is formed on the side surface of the body region 13 around the first trench, so that the body region 13 around the first trench can be connected to the front metal layer without a plurality of small-sized contact holes, and the extraction of the electrode can be realized by uniformly manufacturing a conductive layer.

Because small-sized contact holes do not need to be manufactured independently, the harsh requirements of device preparation on high-end semiconductor equipment, particularly high-precision photoetching machines, are reduced, or the dependence on the high-precision photoetching machines is reduced. For example, a conventional semiconductor process is used to fabricate a power semiconductor device having a trench gate, and if the size of the contact hole is 350nm to 250nm, a DUV-KrF lithography machine is generally used, and the wavelength of the light source is 248 nm; if the size of the contact hole is 250nm to 180nm, a DUV-ArF lithography machine is generally used, and the wavelength of the light source is 193 nm. By adopting the preparation method of the power semiconductor device provided by the embodiment of the application, only an i-Line photoetching machine is needed, the wavelength of a light source is 365nm, and the size of a processing key feature is more than 0.4 mu m.

Moreover, the process requirement of the large-size contact hole on the metalized filling hole is reduced, and high-cost manufacturing processes such as metal plugs, CMP planarization and the like are not needed; furthermore, the reliability of a single large-sized contact hole is much higher than that of a plurality of small-sized contact holes. Therefore, the semiconductor device with the trench type gate provided by the embodiment of the application is low in process control difficulty, high in yield and low in manufacturing cost.

Further, the first front metal layer 251 and the first polysilicon 161 are equivalent to two plates of a capacitor, and when the connection mode of the source is changed, the distance between the source and the first polysilicon 161 is inevitably shortened, which may cause the increase of the gate-source parasitic capacitance. In the embodiment of the present application, the covering structure 20 is arranged to increase the distance between the two plates of the capacitor in a phase-change manner, thereby reducing the gate-source parasitic capacitance. The power semiconductor device is mostly applied as a switch, and for a switching element, the size of the capacitor directly affects the switching speed. Because the input capacitance of the device is the sum of the grid-source capacitance and the grid-drain capacitance, the grid-drain capacitance cannot be changed in the embodiment of the application, the input capacitance is reduced by reducing the grid-source capacitance, and the switching speed of the device is further improved.

In addition, in the process of manufacturing the semiconductor device with the trench gate provided in the embodiment of the present application, when the contact region 22 is formed by implantation, the isolation effect of the capping structure 20 can prevent the doping concentration on the surface of the first polysilicon 161 from being reduced due to the influence of the inversion implantation doping, so as to prevent the gate resistance from being abnormally increased, thereby improving the device performance and ensuring the stability of the device parameters.

Moreover, since the cover structure 20 is higher than the source region 17, when the contact region 22 is formed by injection, the shadow effect of the cover structure 20 can be used to prevent the doping concentration of the source region 17 from being reduced by the inversion injection doping, thereby preventing the source resistance from being abnormally increased, further improving the performance of the device, and ensuring the stability of the device parameters. Through further research and practice, the height a of the cover structure 20 above the surface of the source region 17 is preferably greater than or equal to the width b of the source region 17, but if the cover structure 20 is too high above the surface of the source region 17, the shadow effect is too significant, which results in discontinuity of the contact region 22, resulting in increased contact resistance and impaired device performance. Therefore, in the embodiment of the present application, the ratio of the height a of the cover structure 20 beyond the surface of the source region 17 to the width b of the source region 17 is generally controlled to be 1: 1-10: 1 to optimize device performance.

The embodiments of the present application provide a method for manufacturing the aforementioned semiconductor device with a trench gate, fig. 2 to 14 are schematic diagrams of device structures in steps of manufacturing the aforementioned semiconductor device with a trench gate, and how to manufacture the aforementioned semiconductor device with a trench gate is described in detail below with reference to fig. 2 to 14.

Referring to fig. 2, a semiconductor substrate is provided and a body region 13 is formed extending from a surface of the semiconductor substrate into the semiconductor substrate.

The choice of semiconductor substrate is also different for different types of semiconductor devices having trench-type gates. If the MOSFET is prepared, an epitaxial wafer can be used as a semiconductor substrate; for the preparation of an IGBT, an epitaxial wafer or a single wafer can be used as a semiconductor substrate. Taking an epitaxial wafer as an example of a semiconductor substrate, the epitaxial wafer includes a substrate 11 and an epitaxial layer 12 on a surface of the substrate 11. The epitaxial wafer may be obtained commercially, or may be obtained by depositing the epitaxial layer 12 on the surface of the substrate 11 by a process such as chemical vapor deposition or physical vapor deposition.

In addition, the larger the thickness of the epitaxial layer 12, the more favorable the breakdown voltage of the device, especially in an IGBT, but the less favorable the miniaturization of the device. The thickness of the substrate 11 and the epitaxial layer 12 can be determined by those skilled in the art according to actual requirements. In this embodiment, the thickness of the epitaxial layer 12 is greater than the depth of the subsequently fabricated trench; in other embodiments, the thickness of the epitaxial layer 12 may be less than or equal to the depth of the subsequently formed trench.

The body region 13 is formed by implanting impurities into the epitaxial layer 12 and then annealing. In particular practice, the junction depth of the body region 13 is also increased by the subsequent thermal processing, so that the annealing after the ion implantation is not an essential step, and whether to perform the annealing or not and the annealing process can be adjusted according to actual process conditions. Of course, the junction depth of body region 13 should be less than the thickness of epitaxial layer 12. The doping impurities and the doping concentration used for doping the epitaxial layer 12 can be set according to actual requirements. In the embodiment of the present invention, P-type impurities such as boron having an order of magnitude of E12 or more are implanted into the epitaxial layer 12 to form a P-type doped region as the body region 13.

Referring to fig. 3, the body region 13 is etched to form a first trench 141 and a second trench 142.

Specifically, the body region 13 includes a Main Cell (Main Cell) region and a Gate (Gate) region. A mask (not shown) is disposed on the surface of the body region 13 to define a trench formation region, and the body region 13 is anisotropically etched through a window in the mask to form a plurality of first trenches 141 in the main cell region and a plurality of second trenches 142 in the gate region. Wherein, the width of the first trench 141 is smaller than the width of the second trench 142.

In the implementation of the present application, the first trench 141 and the second trench 142 are both U-shaped trenches. The etching solution can be obtained by anisotropic etching means such as ion milling etching, plasma etching, reactive ion etching, laser ablation and the like, and is not particularly limited. The depth of the trench can be specifically adjusted by controlling the etching time and the etching rate.

Further, in order to avoid a tip problem of a subsequently formed trench gate structure, Rounding etching (Rounding Etch) may be performed on the first trench 141 and the second trench 142, so that inner walls of the first trench 141 and the second trench 142 are rounded.

The depth of the first trench 141 and the depth of the second trench 142 are equal. In the embodiment of the present application, the depth of the first trench 141 and the depth of the second trench 142 are greater than the junction depth of the body region 13. The depths of the first trench 141 and the second trench 142 are sufficiently increased to allow for the junction depth of the P-type doped region to be increased in a subsequent thermal process. In the present embodiment, the first trenches 141 and the second trenches 142 extend into the epitaxial layer 12 through the body region 13. In other embodiments, the depth of the first trench 141 and the depth of the second trench 142 may be set by those skilled in the art according to actual needs, for example, the bottoms of the first trench 141 and the second trench 142 may reach the surface of the substrate 11 through the epitaxial layer 12 and even extend into the substrate 11.

Referring to fig. 4, an insulating layer is grown over the entire device surface and polysilicon filling is performed.

Specifically, a thermal oxidation process, a chemical vapor deposition process, or the like may be employed to form the first insulating layer 151 on the surface of the body region 13, the second insulating layer 152 on the inner wall of the first trench 141, and the third insulating layer 153 on the inner wall of the second trench 142.

In the embodiment, the material of the first insulating layer 151, the material of the second insulating layer 152, and the material of the third insulating layer 153 may include one of silicon oxide, silicon nitride, silicon oxynitride, and a high-K gate dielectric material. The thicknesses of the first insulating layer 151, the second insulating layer 152, and the third insulating layer 153 may be set according to the requirement of the threshold voltage.

After the insulating layer is grown, a CVD process may be used to form polysilicon, and thermal diffusion, post-ion implantation annealing, and the like may be used to dope the polysilicon. The doping to the polysilicon can adopt an in-situ doping process, namely the doping is completed simultaneously in the growth process of the polysilicon. The thickness of the polysilicon may be set according to actual requirements, as long as it is ensured that the first trench 141 and the second trench 142 are completely filled. Generally, the thickness of the polysilicon needs to be no less than half the width of the widest part of the trench. In addition, Chemical Mechanical Polishing (CMP) of the polysilicon may also be performed.

Referring to fig. 5, the polysilicon is etched back, and the polysilicon on the surface of the first insulating layer 151 is removed to form first polysilicon 161 completely filling the first trench 141 and second polysilicon 162 completely filling the second trench 142.

Specifically, the polysilicon etching may be performed using a dry etching process, a wet etching process, or a dry-wet combined etching process to expose the first insulating layer 151.

Referring to fig. 6, the first polysilicon 161 is etched such that the first trenches 141 are partially filled with the first polysilicon 161.

Specifically, a photoresist layer is formed on the surface of the gate region as a mask, and the first polysilicon 161 is etched. In the embodiment of the present application, the distance between the surface of the etched first polysilicon 161 and the surface of the body region 13 is greater than 1000 angstroms, and may be controlled to be about 4500 angstroms, for example.

Referring to fig. 7, the surface of body region 13 around first trench 141 and the side of body region 13 are doped to form source region 17.

Specifically, ion implantation is performed on the main cell region, still using the photoresist layer on the surface of the gate region as a mask, to form the source region 17. In the embodiment of the present application, N-type impurities such as arsenic with an order of magnitude of E15 or more are implanted into the body region 13 by a large angle implantation, and an angle between an ion incident direction and a normal line of the body region 13 is 30 to 45 degrees. After the ion implantation is completed, the photoresist is removed, thereby forming source regions 17 at the surface of body region 13 around first trenches 141 and at the sides of body region 13. Note that, when the power semiconductor device to be formed is an IGBT, the source region 17 functions as an emitter region of the IGBT.

Referring to fig. 8, a fourth insulating layer 154 is grown on the surface of the first polysilicon 161, and a fifth insulating layer 155 is grown on the surface of the second polysilicon 162.

Specifically, after the ion implantation is completed, annealing or silicon oxide deposition is performed to form the fourth insulating layer 154 on the surface of the first polysilicon 161 and the fifth insulating layer 155 on the surface of the second polysilicon 162. The material of the fourth insulating layer 154 and the material of the fifth insulating layer 155 may include one of silicon oxide, silicon nitride, silicon oxynitride, and a high-K gate dielectric material.

Referring to fig. 9, a stop layer 18 and an interlevel dielectric layer 19 are sequentially deposited over the entire device surface.

Specifically, the stop layer 18 may be deposited using an LPCVD process, which is characterized by the simultaneous growth of thin films on the sidewalls and bottom surface. The thickness of the stop layer 18 may be set according to actual requirements, as long as it is ensured that the first trench 141 is completely filled. Generally, the thickness of the stop layer 18 is larger than half of the maximum width of the first trench 141.

In the embodiment of the present application, the material of the stop layer 18 is SiN. SiN is used as an etch stop layer to improve the tolerance of the subsequent hole etch process.

After the stop layer 18 is formed, a dielectric material that is flowable at a predetermined temperature (e.g., 800 ℃ to 1200 ℃) may be coated on the surface of the stop layer 18 by a sputtering deposition process, a chemical vapor deposition process, or a spin-on deposition process. The dielectric material may be any material capable of flowing at a certain temperature and serving as an insulating medium in the art, such as at least one of silicate glass, tetraethoxysilane, spin-on glass (SOG), and polymer material, wherein the silicate glass may include at least one of phosphosilicate glass (PSG), borosilicate glass (BSG), and borophosphosilicate glass (BPSG). By using the above dielectric material as a raw material for deposition, SiO can be formed₂The layer serves as an interlevel dielectric layer 19.

Referring to fig. 10, the interlayer dielectric layer 19 is etched to expose the stop layer 18 directly over the main cell region and a portion of the stop layer 18 directly over the second trench 142.

Specifically, the photoresist is used as a mask, the stop layer 18 is used as a stop layer for etching, the interlayer dielectric layer 19 directly above the main cell region and a part of the stop layer 18 directly above the second trench 142 are fully etched, and an opening with a larger area is formed in the main cell region, wherein the opening of the main cell region exposes the stop layer 18 directly above the first trench 141 and on the surface of the surrounding body region 13.

Compared with the traditional process, the etching process does not need to use a DUV mask to manufacture hundreds of thousands or even millions of independent small holes in the main unit area to manufacture the metal plug, but uses a common photoetching machine to manufacture a large-area opening in the main unit area, and does not need to consider the alignment precision too much, so that the process difficulty of the device is reduced.

Referring to fig. 11, the stop layer 18, the first insulating layer 151 and the fifth insulating layer 155 are etched to expose the surface of the body region 13 around the first trench 141, so as to leave the stop layer 18 in the first trench 141 as the capping structure 20 and expose a portion of the surface of the second polysilicon 162.

Specifically, the etching is continued to be performed on the stop layer 18, the first insulating layer 151 and the fifth insulating layer 155, so as to remove the stop layer 18 and the first insulating layer 151 on the surface of the main cell region, and expose the surface of the body region 13 around the first trench 141, and the stop layer 18 in the first trench 141 serves as the cover structure 20 to protect the first polysilicon 161 thereunder. The fifth insulating layer 155 is etched to expose a portion of the second polysilicon 162. And after the etching is finished, removing the photoresist.

Referring to fig. 12, the body region 13 around the first trench 141 and the second polysilicon 162 are etched to remove the source region 17 on the surface of the body region 13 around the first trench 141 and form a groove structure on the second polysilicon 162.

Specifically, the interlayer dielectric layer 19 is used as a hard mask, the body region 13 located in the main cell region and the second polysilicon 162 located in the gate region are etched, the etching depth is not less than the junction depth of the annealed source region 17, only the source region 17 on the side of the body region 13 around the first trench 141 is reserved, and a groove structure is formed in the second polysilicon 162. After the etching, the surface of the first trench 141 is higher than the surface of the body region 13 around the first trench, i.e. the cover structure 20 is higher than the source region 17 on the side of the body region 13, and a contact hole 21 is formed in the gate region.

Referring to fig. 13, the surface of the body region 13 around the first trench 141 is doped to form a contact region 22 of the first doping type.

Specifically, the contact region 22 is located on a P-type doped region with a relatively low doping concentration, and therefore, in order to ensure ohmic contact and reduce contact resistance, boron implantation is generally performed at a dose of the order of E14. In the embodiment of the present application, the angle between the ion incident direction and the normal of the body region 13 is not less than 7 degrees, for example, a large angle ion implantation is adopted, so that the concentration of the P-type lightly doped region on the exposed sidewall of the body region 13 is supplemented.

In order to form the complete device structure, it is also necessary to fabricate an electrode structure after forming the contact region 22.

Referring to fig. 14, a barrier metal layer and a front metal layer are sequentially deposited on the entire device surface, and the barrier metal layer and the front metal layer are etched to form a first electrode structure and a second electrode structure, where the second electrode structure is not in contact with the first electrode structure.

The second electrode structure fills at least the contact hole 21. The second electrode structure includes a second barrier metal layer 232 and a second front metal layer 242, the second barrier metal layer 232 is located on the inner wall of the contact hole 21, and the second front metal layer 242 is located on the surface of the second barrier metal layer 242. In the embodiment of the present application, the second electrode structure may also cover a portion of the surface of the interlayer dielectric layer 19.

And after the patterning of the front metallization is finished, alloy treatment is carried out, a passivation layer covering the surface of the device can be manufactured according to the requirement, and the process for manufacturing the passivation layer is a conventional process and is not repeated.

Referring to fig. 1, when the semiconductor device with the trench gate is formed as a MOSFET, after the electrode structure is formed on the front surface, the substrate 11 may be thinned, and a back metal layer 25 may be deposited on the back surface of the substrate 11, where the back metal layer 25 serves as a drain.

When the semiconductor device with the trench gate is formed as an IGBT, after an electrode structure is formed on the front surface, the substrate 11 is thinned, a PN junction is formed in the substrate 11, and finally, a back metal layer 25 is deposited on the back surface of the substrate 11, the back metal layer 25 serving as a collector.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A semiconductor device having a trench gate, comprising:

a semiconductor substrate;

a first trench penetrating through the first region and extending into the semiconductor substrate, wherein a second insulating layer is arranged on the inner wall of the first trench, the second insulating layer exceeds the surface of the first region, first polycrystalline silicon, a fourth insulating layer and a covering structure are sequentially arranged in the first trench from bottom to top, the surface of the fourth insulating layer is lower than the surface of the first region, a source region is arranged on the side surface of a body region around the first trench, the doping type of the source region is opposite to that of the body region, a contact region is arranged on the surface of the body region around the first trench, and the doping type of the contact region is the same as that of the body region;

the second groove penetrates through the first insulating layer and the second area in sequence and extends into the semiconductor substrate, the width of the second groove is larger than that of the first groove, a third insulating layer is arranged on the inner wall of the second groove, the second groove is completely filled with second polycrystalline silicon, and a fifth insulating layer is arranged on the surface of the second polycrystalline silicon;

and the contact hole penetrates through the interlayer dielectric layer, the stop layer and the fifth insulating layer in sequence and extends to the second polycrystalline silicon.

2. The semiconductor device according to claim 1, wherein a surface of the first region is lower than a surface of the second region, and a surface of the capping structure and a surface of the second region are in the same plane.

3. The semiconductor device with the trench gate of claim 1, wherein a ratio of a height of the cover structure beyond the surface of the first region to a width of the source region is 1: 1-10: 1.

4. the semiconductor device having a trench gate of claim 1, wherein a width of the contact hole is smaller than a width of the second trench.

5. The semiconductor device with a trench-type gate of claim 1, wherein the capping structure and the stop layer are both silicon nitride layers.

6. The semiconductor device with the trench gate of claim 1, wherein the first insulating layer, the second insulating layer and the third insulating layer are all silicon oxide layers, silicon nitride layers, silicon oxynitride layers or high-K gate dielectric material layers;

the fourth insulating layer and the fifth insulating layer are both silicon oxide layers, silicon nitride layers, silicon oxynitride layers or high-K gate dielectric material layers.

7. The semiconductor device with the trench gate of claim 1, wherein the interlayer dielectric layer is a silicon dioxide layer.

8. The semiconductor device having a trench gate according to any one of claims 1 to 7, further comprising:

a first electrode structure at least covering the cover structure, the source region and the contact region, the first electrode structure including a first barrier metal layer and a first front metal layer, the first barrier metal layer being located on a surface of the cover structure, a surface of the source region and a surface of the contact region, the first front metal layer being located on a surface of the first barrier metal layer;

9. The semiconductor device having a trench gate of claim 8, further comprising:

and the back metal layer is positioned on the back of the semiconductor substrate.

10. The semiconductor device having a trench gate of claim 9, further comprising:

a PN junction located within the semiconductor substrate.