CN111986997A - Method for manufacturing super junction device - Google Patents
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- CN111986997A CN111986997A CN202010867039.9A CN202010867039A CN111986997A CN 111986997 A CN111986997 A CN 111986997A CN 202010867039 A CN202010867039 A CN 202010867039A CN 111986997 A CN111986997 A CN 111986997A
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention discloses a manufacturing method of a super junction device, which comprises the following steps: filling a grid groove with a polysilicon grid and carrying out first planarization to form a grid structure; and step two, carrying out back etching on the polysilicon gate, forming a sealing layer in a top depression formed by the back etching, and step three, filling the super junction groove with a second epitaxial layer and carrying out secondary planarization to form a super junction. The invention can realize the full flat process, conveniently arrange the trench gate process before the super junction forming process, and reduce the thermal process after the super junction forming, thereby reducing the impurity interdiffusion of the super junction and improving the device performance, saving the photomask and reducing the process cost; and the polysilicon gate can be prevented from doping and expanding outwards, and the gate oxide layer can be protected, so that the product quality and reliability are improved.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a super junction device.
Background
The super junction is composed of alternately arranged P-type thin layers, also called P-type pillars (pilar), and N-type thin layers, also called N-type pillars, formed in a semiconductor substrate, and the device employing the super junction is a super junction device such as a super junction MOSFET. The technology of reducing the surface electric field (Resurf) in a body by utilizing the charge balance of the P-type thin layer and the N-type thin layer can improve the reverse breakdown voltage of the device and simultaneously keep smaller on-resistance.
The PN-spaced Pillar structure of the super junction is the biggest characteristic of the super junction. The conventional method for manufacturing the p-n spaced pilar structure mainly comprises two methods, one is obtained by multiple times of epitaxy and ion implantation, and the other is manufactured by deep trench etching and Epitaxy (EPI) filling. The latter method is to fabricate the super junction device by a trench process, in which a trench with a certain depth and width is first etched on an N-type doped epitaxial layer on the surface of a semiconductor substrate, such as a silicon substrate, and then a P-type doped silicon epitaxy is filled on the etched trench by an epitaxial Filling (EPI Filling) method.
With the continuous reduction of the step (Pitch) of the super junction, the problem caused by the counter doping (counter dope) formed by the mutual diffusion of the P-type doping and the N-type doping of the P-type column and the N-type column in the thermal process is more and more serious, and the device performance is seriously affected.
FIG. 1 is a schematic diagram of the interdiffusion structure of a conventional super junction; the super junction mainly comprises:
an N-type epitaxial layer 102 formed on a surface of an N-type semiconductor substrate, such as a silicon substrate 101, by which the semiconductor substrate is referred to as a wafer (wafer) in the field of integrated circuit fabrication by having a wafer structure; a super junction trench 103 is formed in the N-type epitaxial layer 102, a trench corresponding to a super junction is referred to as a super junction trench in the present application, a P-type epitaxial layer is filled in the super junction trench 103, P-type columns 104 are formed by the P-type epitaxial layer filled in the super junction trench 103, N-type columns are formed by the N-type epitaxial layer 102 between the P-type columns 104, and the P-type columns 104 and the N-type columns are alternately arranged to form the super junction. In general, the impurities of the P-type column 104 and the N-type column of the super junction may diffuse into each other in a thermal process, for example, the P-type impurity in the P-type column 104 may diffuse into the N-type column, and a region 105 in fig. 1 corresponds to a region where the P-type impurity in the P-type column 104 diffuses into the N-type column. In an N-type super junction device, an N-type column is usually used as a component of a drift region during conduction, and after the doping concentration of the N-type column is reduced and the width of the N-type column is narrowed, the on-resistance of the device is reduced.
As the step size of the super junction decreases, the ratio of the width range of the super junction affected by the interdiffusion of P-type and N-type impurities generated by the thermal process, such as the width of the region 105 in fig. 1, to the total width of the step, which is the sum of the width and the pitch of the super junction trenches 103, increases, thus seriously affecting the performance of the device.
FIG. 2 is a flow chart of a method for fabricating a conventional super junction device; fig. 2 illustrates a flow of a method for manufacturing a super junction device by using photolithography steps, wherein a Mask (Mask) is used for each photolithography step. The manufacturing method of the prior super junction device comprises the following steps:
and forming a zero layer alignment mark by a first layer of photoetching process. And on the scribing way formed by the alignment mark of the zeroth layer, the alignment mark of the zeroth layer is required to be adopted for alignment in the subsequent second-layer photoetching process corresponding to the formed body region. The zeroth layer alignment mark is defined by a zeroth layer Mask (ZM), and the Mask1 is also used to indicate the zeroth layer Mask.
Second layer photolithography process, body implantation and drive-in. The sampling of the body implant needs to be defined with Mask 2.
And a third layer of photoetching process, and etching and filling the super junction groove. The forming area of the super structure groove needs to be defined by Mask 3.
And a fourth layer photoetching process, and depositing and etching field oxygen. The etched area of the field oxide needs to be defined by Mask 4. The field oxygen is generally formed on the surface of the termination region, which surrounds the periphery of the device cell region, i.e., the current flow region, i.e., the active region. The field oxide of the device cell region needs to be removed before the structure of the device cell region is formed.
And a fifth layer of photoetching process, etching the grid groove and forming a grid oxide layer and a polysilicon grid. In the invention, the trench corresponding to the trench gate is called a gate trench, and the gate trench needs to be defined by Mask 5.
And a sixth layer of photoetching process, polysilicon photoetching and etching, and body region injection and propulsion. The Mask6 is adopted to define the etching area of the polysilicon, and after the polysilicon is photoetched and etched, the extraction structure of the polysilicon gate of the trench gate can be formed. The extraction structure of the polysilicon gate is usually located in the termination region, so the polysilicon of the extraction structure needs to climb over the slope between the field oxide and the active region.
The body implant here does not require lithographic definition.
And a seventh layer of photoetching process, and injecting and advancing a source region. The implantation area of the source region is defined by Mask 7.
And an eighth layer of photoetching process, interlayer film deposition and contact hole (CT) etching, and injection and propulsion of a body region lead-out region. The etching area of the contact hole is defined by Mask 8.
And a ninth layer of photoetching process, and depositing and etching the front metal layer. The etched area of the front metal layer is defined by Mask 9.
A tenth layer of photoetching process, deposition and etching of a Contact PAD (CP); the etched area of the contact pad is defined using Mask 10.
As can be seen from the above, in the conventional method, 10 photolithography processes are required, and many thermal processes are further included after the super junction is formed, so that the super junction formed by the conventional method is easily affected by the thermal processes and generates large interdiffusion, thereby reducing the performance of the device.
Disclosure of Invention
The invention aims to provide a manufacturing method of a super junction device, which can reduce the thermal process after the super junction is formed, thereby reducing the mutual diffusion of impurities of the super junction and improving the performance of the device.
In order to solve the above technical problem, the method for manufacturing a super junction device provided by the present invention is implemented by using an All flat (al flat) process, so that the process for forming the gate structure is located before the process for forming the super junction, and comprises the following steps:
step one, forming the grid structure, wherein the grid structure is a groove grid, and the forming process of the groove grid comprises the following steps:
providing a first epitaxial layer with a first conductivity type, and performing a photolithography process to define a formation region of a gate trench.
And etching the first epitaxial layer to form the gate trench, wherein the width of the gate trench at the leading-out position of the gate structure meets the requirement of forming a contact hole.
And forming a gate oxide layer on the side surface of the gate trench, and forming a bottom oxide layer on the bottom surface of the gate trench.
And filling a polysilicon gate with second conductive type heavy doping in the gate trench, wherein the gate oxide layer, the bottom oxide layer and the polysilicon gate formed in the gate trench form the trench gate.
And carrying out first planarization to enable the surface of the first epitaxial layer on which the trench gate is formed to be a flat surface.
Step two, carrying out a sealing treatment process of the polysilicon gate, comprising the following steps of:
and carrying out back etching on the polysilicon gate to enable the top surface of the polysilicon gate to be lower than the surface of the first epitaxial layer and form a top recess, wherein the depth of the top recess is smaller than that of the source region.
And filling a sealing layer consisting of a dielectric layer in the top recess, wherein the surface of the sealing layer is level to that of the first epitaxial layer, and the sealing layer prevents the doping of the polysilicon gate from expanding outwards and protects the gate oxide layer.
Step three, performing a super junction forming process, comprising:
and carrying out a photoetching process on the flat surface of the first epitaxial layer on which the trench gate is formed to define a formation region of the super junction trench.
And etching the first epitaxial layer to form a super junction groove.
And filling a second epitaxial layer of a second conductivity type in the super junction trench, forming second conductivity type columns by the second epitaxial layer filled in the super junction trench, forming first conductivity type columns by the first epitaxial layer between the second conductivity type columns, and alternately arranging the first conductivity type columns and the second conductivity type columns to form the super junction.
And carrying out second planarization to enable the surface of the first epitaxial layer formed with the super junction to be a flat surface.
The further improvement is that, in the first step, before the photolithography process for defining the gate trench, a step of forming a first hard mask layer on the surface of the first epitaxial layer is further included, and then, the first hard mask layer is etched first and then the first epitaxial layer is etched to form the gate trench;
removing the first hard mask layer after the first planarization is stopped on the first hard mask layer.
In a further improvement, in the step one, after the gate trench is etched and before the gate oxide layer is formed, a step of rounding the gate trench is further included, and the rounding includes:
a first sacrificial oxide layer is formed by a thermal oxidation process.
And removing the first sacrificial oxide layer.
In a further improvement, the gate oxide layer is formed on the side surface of the gate trench by a thermal oxidation process.
In a further improvement, the bottom oxide layer and the gate oxide layer are formed simultaneously by the same process.
Or the thickness of the bottom oxide layer is larger than that of the gate oxide layer, and the bottom oxide layer and the gate oxide layer are formed separately.
The further improvement is that the method also comprises the following steps:
and forming a body region by adopting an ion implantation and annealing advancing process, wherein the forming region of the body region is defined by photoetching.
And forming a source region by adopting an ion implantation and annealing advancing process, wherein the forming region of the source region is defined by photoetching, and the source region is self-aligned with the side surface of the corresponding grid structure in the device unit region.
And forming field oxygen, wherein the field oxygen covers the first epitaxial layer which is formed with the super junction and the trench gate and has a flat surface, and the field oxygen has a flat structure without climbing.
The formation process of the body region and the formation process of the source region are disposed before the formation process of the field oxide.
The further improvement is that the forming process of the field oxygen is arranged before the third step;
the field oxide is composed of a thermal oxide layer or an oxide layer formed by superposing the thermal oxide layer with a TEOS (tetraethyl orthosilicate) oxidation process, the thermal oxide layer of the field oxide is formed by a thermal oxidation process, the sealing layer is directly composed of the thermal oxide layer of the field oxide positioned in the top recess, and the top surface of the thermal oxide layer of the field oxide is of a flat structure by utilizing the characteristic that the thermal oxidation rate of the polysilicon gate is greater than that of the first epitaxial layer.
In a further improvement, the field oxygen forming process is arranged after the third step;
the forming process of the body region is arranged before the first step, and the forming process further comprises the steps of carrying out photoetching by adopting a zero-layer photomask and forming a zero-layer alignment mark before the body region is formed; or, the forming process of the body region is arranged after the first step and before the third step;
the forming process of the source region is arranged after the first step and before the third step; or, the forming process of the source region is arranged after the third step.
In a further improvement, after the field oxygen is formed, the method further comprises the following steps:
forming an interlayer film and a contact hole, wherein the forming area of the contact hole is defined by photoetching, and the corresponding contact hole is formed at the leading-out position of the grid structure;
forming a front metal layer, and patterning the front metal layer by adopting a photoetching definition and etching process, wherein an electrode formed by the patterned front metal layer comprises a gate electrode structure, and the gate electrode structure is contacted with the polysilicon gate through the contact hole at the leading-out position of the gate electrode structure;
forming a contact pad, wherein a forming area of the contact pad is defined by photoetching;
and finishing the back process of the super junction device.
In a further refinement, the interlayer film covers the flat field oxide surface;
the interlayer film is formed by a USG oxidation process or a TEOS oxidation process.
The further improvement is that in the third step, a second hard mask layer is adopted in the super junction forming process, the second hard mask layer is formed by overlapping a second bottom oxide layer, a middle nitride layer and a top oxide layer, and the super junction forming process comprises the following steps when the second hard mask layer is adopted:
forming the second hard mask layer;
defining a forming area of the super junction groove by adopting a photoetching process;
sequentially etching the second hard mask layer and the first epitaxial layer to form the super junction groove;
removing the top oxide layer of the second hard mask layer, forming a second sacrificial oxide layer by adopting a thermal oxidation process, and then removing the second sacrificial oxide layer;
removing the middle nitriding layer of the second hard mask layer;
carrying out epitaxial filling in the super junction groove to form the second epitaxial layer;
performing a chemical mechanical polishing process on the second epitaxial layer to achieve the second planarization, so that the second epitaxial layer is only filled in the super junction trench;
and completely removing or only partially removing the second bottom oxide layer of the second hard mask layer.
The second bottom oxide layer is formed by adopting a thermal oxidation process, the closed layer is directly formed by the second bottom oxide layer positioned in the top recess, and the top surface of the second bottom oxide layer is of a flat structure by utilizing the characteristic that the thermal oxidation rate of the polysilicon gate is greater than that of the first epitaxial layer.
In a further improvement, the top recess has a depth of
In a further improvement, the first epitaxial layer is formed on a semiconductor substrate, and the back process of the super junction device comprises:
thinning the back of the semiconductor substrate;
directly taking the thinned semiconductor substrate as the drain region, or performing back injection of first conductivity type heavy doping on the thinned semiconductor substrate to form the drain region;
and forming a back metal layer on the back of the drain region.
In a further improvement, the first planarization is realized by a back etching process or a chemical mechanical polishing process.
The key point of the invention is to adopt the full flat technology to realize, make the forming process of the grid structure before the forming process of the super junction, and realize the key point of the full flat technology is that the invention has made the special arrangement to the leading-out of the grid structure, has cancelled the climbing structure used in the leading-out of the grid, but connect to the gate electrode structure composed of metal layer of front through forming the contact hole in the leading-out position of the grid structure directly; because of no climbing structure, the grid structure of the invention can form a flattened surface, the flattened surface after the grid structure is formed is the key for forming the super junction after the grid structure is formed, and the super junction is formed after the grid structure is formed, thus the technical problem of reducing the mutual diffusion of impurities of the super junction can be well solved; the leading-out of the grid structure of the super junction device is set to be led out through the contact hole at the top of the trench grid, so that the super junction device can be well flattened; the characteristic of realizing flatness after the grid structure is formed enables the groove grid process of the invention to be conveniently arranged before the super junction forming process, and to be conveniently flattened after the super junction is formed, finally, the full flat process can be realized, and the process difficulty of the device can be greatly reduced; the trench gate process is arranged before the super junction forming process, so that a plurality of unexpected technical effects can be brought, and the technical effects comprise:
the method can eliminate the influence of the thermal process of the forming process of the grid structure on the super junction, the thermal process of the forming process of the grid structure mainly comprises the forming process of a sacrificial oxide layer and the forming process of a grid oxide layer, the thermal process of the grid structure is large, and the influence on mutual diffusion of PN impurities of the super junction can be greatly reduced, so that the technical problem of the invention can be well solved, and finally the performance of a device is improved.
Secondly, because the forming process of the grid structure is positioned before the forming process of the super junction, the adverse effect of the thermal process on the super junction is not required to be considered in the forming process of the grid structure, so that the use of the thermal process of the forming process of the grid structure is not limited, and the grid structure with better quality can be obtained.
And thirdly, in the prior art, two times of body region injection and propulsion are adopted, wherein one time of body region injection and propulsion is arranged after the gate structure is formed, so that the thermal process of the next time of body region propulsion still can generate adverse effects on the super junction.
And thirdly, because the forming process of the grid structure is placed before the forming process of the super junction, the surface of the device unit area is originally exposed when the grid structure is formed, and the forming and etching processes of field oxygen are not needed to expose the device unit area, so that the photoetching defining process of field oxygen can be saved once, and a layer of photomask related to field oxygen etching can be saved.
Because the field oxygen at the top of the device unit region is not required to be removed, the edge of the device unit region and the terminal region is not provided with a climbing structure of the field oxygen, the surface of the whole field oxygen is in a flat structure, and thus the interlayer film is also in a flat structure after being formed on the field oxygen, and the interlayer film is not required to be flattened by adopting a BPSG (band-gap glass) reflow process, so that the adverse effect of the thermal process of the BPSG reflow process on the super junction can be further reduced, and the performance of the device can be further improved.
In addition, in the invention, because the grid structure is formed before the forming process of the super junction, the forming process of the source region including the injection and the annealing propulsion process can also be arranged before the forming process of the super junction, so the invention can further reduce the adverse effect of the thermal process of the propulsion process of the source region on the super junction, thereby further improving the performance of the device.
In addition to the beneficial effects associated with reducing the thermal process of the super junction, the present invention can also save the photomask by setting the process sequence of the gate structure, which is specifically described as follows:
first, the reticle of the above-described field oxygen lithographic definition process can be saved.
Secondly, when a grid structure is formed on the wafer firstly and then a body region is formed, the photoetching of the body region can be directly aligned by adopting the grid structure without adopting a zeroth layer alignment mark, so that the invention can save a zeroth layer photomask.
And then, in the invention, a contact hole can be directly formed at the top of the leading-out position of the grid structure to lead out the grid structure, the polysilicon gate of the grid structure does not need to extend to the top of the field oxide through climbing, and then the contact hole is formed on the polysilicon at the top of the field oxide to lead out the grid structure, so that the photoetching process is not needed to carry out photoetching definition on the polysilicon climbing to the top of the field oxide, and the invention can also save a photomask for photoetching definition of the polysilicon.
Therefore, the invention can save multi-layer light shield, such as 3 layers of light shield at most, and can greatly reduce the process cost.
In addition, after the grid structure is formed, the step of forming the sealing layer on the top of the polysilicon gate is added, the sealing layer can prevent impurities of the polysilicon gate from expanding outwards (out bulging) in the thermal process of a subsequent process such as a furnace tube, the impurities of the polysilicon gate can influence process equipment so as to influence the film forming quality of the same batch (lot) or other batches of wafer products produced in the same process equipment and influence the self film forming quality of the same wafer, and therefore after the sealing layer is added on the top of the polysilicon gate, the impurities of the polysilicon gate can be prevented from expanding outwards under the condition of not influencing the surface flatness of the first epitaxial layer so as to improve the film forming quality of the product.
The sealing layer at the top of the polysilicon gate can protect the gate oxide layer, and can prevent the gate oxide layer from being damaged by subsequent etching processes such as wet etching, thereby improving the reliability of the gate structure.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of the structure of the interdiffusion of a conventional superjunction;
FIG. 2 is a flow chart of a method of fabricating a prior art super junction device;
FIG. 3 is a flow chart of a method of fabricating a super junction device according to an embodiment of the present invention;
fig. 4A to 4N are schematic views of device structures in steps of a method for manufacturing a super junction device according to an embodiment of the present invention.
Detailed Description
FIG. 3 is a flow chart of a method of fabricating a super junction device according to an embodiment of the present invention; fig. 3 is a diagram illustrating a photolithography process level, where a photolithography process level includes a plurality of specific process steps and a photolithography process level performs only a photolithography process corresponding to a reticle. Fig. 4A to 4N are schematic diagrams of device structures in steps of a method for manufacturing a super junction device according to an embodiment of the present invention; the manufacturing method of the super junction device comprises the following steps:
step one, forming the grid structure, wherein the grid structure is a groove grid, and the forming process of the groove grid comprises the following steps:
a first epitaxial layer 2 having a first conductivity type is provided, and a photolithography process is performed to define a formation region of the gate trench 201.
As shown in fig. 4A, a first epitaxial layer 2 of a first conductivity type is provided, said first epitaxial layer 2 being formed on a surface of a semiconductor substrate 1, such as a silicon substrate(ii) a A photolithography process is performed to define a formation region of the gate trench 201. The doping concentration of the first epitaxial layer 2 is 1e14cm-3～1e17cm-3. The thickness of the first epitaxial layer 2 is 5-100 microns.
As shown in fig. 4B, the first epitaxial layer 2 is etched to form the gate trench 201, and the width of the gate trench 201 at the position where the gate structure is led out meets the requirement of forming the contact hole 10.
As shown in fig. 4B, a gate oxide layer 3 is formed on the side surface of the gate trench 201, and a bottom oxide layer is formed on the bottom surface of the gate trench 201.
As shown in fig. 4C, a polysilicon gate 4 with a heavy doping of a second conductivity type is filled in the gate trench 201, and the gate oxide layer 3, the bottom oxide layer and the polysilicon gate 4 formed in the gate trench 201 constitute the trench gate.
And carrying out first planarization to enable the surface of the first epitaxial layer 2 with the trench gate to be a flat surface.
Preferably, the method further includes a step of forming a first hard mask layer on the surface of the first epitaxial layer 2 before performing the photolithography process for defining the gate trench 201, and then etching the first hard mask layer and then etching the first epitaxial layer 2 to form the gate trench 201.
Removing the first hard mask layer after the first planarization is stopped on the first hard mask layer.
The first planarization is realized by a back etching process or a chemical mechanical polishing process.
In the first step, the method further includes a step of rounding the gate trench 201 after the gate trench 201 is etched and before the gate oxide layer 3 is formed, where the rounding includes:
a first sacrificial oxide layer is formed by a thermal oxidation process.
And removing the first sacrificial oxide layer.
The gate oxide layer 3 is formed on the side surface of the gate trench 201 by adopting a thermal oxidation process.
In the embodiment of the invention, the bottom oxide layer and the gate oxide layer 3 are formed simultaneously by the same thermal oxidation process, so that the bottom oxide layer and the gate oxide layer 3 are the same oxide layer with the same thickness and are marked by a mark 3. In other embodiments can also be: the thickness of the bottom oxide layer is larger than that of the gate oxide layer 3, and the bottom oxide layer and the gate oxide layer 3 are formed separately; usually, the bottom oxide layer with a larger thickness is formed first, and the gate oxide layer 3 is formed by adopting a thermal oxidation process; the bottom of the gate trench 201 may also be subjected to amorphization ion implantation, and then subjected to thermal oxidation to simultaneously form the bottom oxide layer and the gate oxide layer 3, because the bottom of the gate trench 201 is subjected to amorphization ion implantation, the thermal oxidation rate of the bottom of the gate trench 201 is accelerated, and the thickness of the bottom oxide layer is greater than that of the gate oxide layer 3. The thickening of the thickness of the bottom oxide layer is beneficial to improving the pressure resistance of the bottom of the gate trench 201.
The process of forming the trench gate corresponds to the first layer of photolithography process in fig. 3.
Step two, performing a sealing treatment process of the polysilicon gate 4, including:
fig. 4C1 is an enlarged view of the formation region of the gate structure shown in fig. 4C, and as shown in fig. 4C1, the polysilicon gate 4 is etched back such that the top surface of the polysilicon gate 4 is lower than the surface of the first epitaxial layer 2 and a top recess 301 is formed, wherein the depth of the top recess 301 is smaller than that of the source region 6. The depth of the top recess 301 is
Is typically given a value of
The top recess 301 is filled with a closed layer 302 composed of a dielectric layer, the closed layer 302 is flush with the surface of the first epitaxial layer 2, and the closed layer 302 prevents the polysilicon gate 4 from being doped to expand outwards and protects the gate oxide layer 3. Fig. 4G1 is an enlarged view of a region where the gate structure of fig. 4G is formed, and the capping layer 302 is shown in fig. 4G 1.
Further comprising the steps of: as shown in fig. 4D, the body region 5 is formed by ion implantation and an annealing advancement process, and a formation region of the body region 5 is defined by photolithography. The formation step of the body region 5 corresponds to the second level lithography process in fig. 3. Compared with the prior art shown in fig. 2, in the embodiment of the present invention, since the gate structure forming process is performed before the body region 5 forming process, the zero-th layer alignment mark forming process shown in fig. 2 is not required, which can save a layer of photomask and corresponding photolithography process.
Further comprising the steps of: as shown in fig. 4E, an ion implantation and an annealing advancement process are used to form the source region 6, a formation region of the source region 6 is defined by photolithography, and the source region 6 and the corresponding side surface of the gate structure in the device cell region are self-aligned. The source region 6 is not formed in the termination region, so the source region 6 needs to be defined by a layer of photomask, and the forming process of the source region 6 corresponds to the third layer of photolithography process in fig. 3.
Step three, performing a super junction forming process, comprising:
as shown in fig. 4F, a photolithography process is performed on the planar surface of the first epitaxial layer 2 on which the trench gate is formed to define a formation region of the super junction trench 205.
As shown in fig. 4F, the first epitaxial layer 2 is etched to form a super junction trench 205.
As shown in fig. 4G, the super junction trench 205 is filled with a second epitaxial layer 7 of the second conductivity type; second conductive type columns are formed by the second epitaxial layer 7 filled in the super junction grooves 205, first conductive type columns are formed by the first epitaxial layer 2 between the second conductive type columns, and the first conductive type columns and the second conductive type columns are alternately arranged to form the super junctions.
As shown in fig. 4H, the second planarization is performed to make the surface of the first epitaxial layer 2 on which the super junction is formed a flat surface.
Preferably, a second hard mask layer is adopted in the super junction forming process, and the super junction forming process includes the following steps when the second hard mask layer is adopted:
as shown in fig. 4F, the second hard mask layer is formed, and the second hard mask layer is formed by stacking a second bottom oxide layer 202, a middle nitride layer 203, and a top oxide layer 204.
The second bottom oxide layer is formed by a thermal oxidation process, the sealing layer 302 is directly formed by the second bottom oxide layer in the top recess 301, and the top surface of the second bottom oxide layer is a flat structure by utilizing the characteristic that the thermal oxidation rate of the polysilicon gate 4 is greater than the thermal oxidation rate of the first epitaxial layer 2. For example, the second bottom oxide layer has a thickness of
In the above-mentioned manner,
the deeply acting top recess 301 may be fully leveled by the second bottom oxide layer.
The formation region of the super junction trench 205 is defined by a photolithography process.
And etching the second hard mask layer and the first epitaxial layer 2 in sequence to form the super junction trench 205.
As shown in fig. 4G, the top oxide layer 204 of the second hard mask layer is removed, a second sacrificial oxide layer is formed by a thermal oxidation process, and then the second sacrificial oxide layer is removed.
The intermediate nitride layer 203 of the second hard mask layer is removed as shown in fig. 4G.
As shown in fig. 4G, the second epitaxial layer 7 is formed by epitaxial filling in the super junction trench 205.
As shown in fig. 4H, the second planarization is performed by performing a chemical mechanical polishing process on the second epitaxial layer 7, so that the second epitaxial layer 7 is only filled in the super junction trench 205.
The second bottom oxide layer 202 of the second hard mask layer is removed entirely or only partially.
Step three corresponds to the fourth layer photolithography process in fig. 3.
After the third step is completed, the method further comprises the following steps:
as shown in fig. 4I, field oxide 8 is formed. In the embodiment of the present invention, after the field oxide 8 is formed, the field oxide 8 does not need to be etched to open the device unit region, so a mask can be saved in the process for forming the field oxide 8, and in fig. 3, the process for forming the field oxide 8 is still classified into the fourth layer photolithography process in fig. 3. In addition, the field oxide 8 is not patterned by the photolithography process and the etching process, so that the field oxide 8 has a flat structure without climbing. The field oxide 8 is composed of an oxide layer formed by superposing a thermal oxide layer on a TEOS (tetraethyl orthosilicate) oxidation process, for example, the thermal oxide layer of the field oxide 8 has a thickness of
The thickness of the oxide layer formed by the TEOS oxidation process of the field oxide 8 is
Is typically given a value of
In other embodiments can also be: the field oxide 8 is composed of a thermal oxide layer.
As shown in fig. 4J, an interlayer film 9 is formed. The interlayer film 9 covers the flat surface of the field oxide 8, and the field oxide 8 has a flat structure without climbing, so that a BPSG (binary pattern generator) reflow process required by the planarization of the interlayer film 9 is eliminated in the interlayer film 9 forming process, and the heat process can be saved by eliminating the BPSG reflow process. Since the BPSG reflow process is not required, the interlayer film 9 does not need to be formed by the BPSG oxidation process, and in the embodiment of the present invention, the interlayer film 9 is formed by the USG oxidation process or the TEOS oxidation process. In fig. 3, the process of forming the interlayer film 9 is still classified into the fourth photolithography process in fig. 3.
A contact hole 10, a forming region of the contact hole 10 being defined by photolithography. The forming process of the contact hole 10 comprises the following sub-steps:
as shown in fig. 4J, a photolithography process is used to define a formation region of the contact hole 10, and then the interlayer film 9 and the field oxide 8 are sequentially etched to form an opening 206 of the contact hole 10.
In fig. 4J, the opening 206 is only located on the top of the corresponding source region 6 and body region 5 in the device cell region. An opening 206a having a width larger than that of the opening 206 is further formed at the periphery of the device cell region, and the bottom of the opening 206a opens the corresponding second conductive type pillar and the body region 5.
In fig. 4J, the opening 206 of the contact hole 10 is not formed at the top of the polysilicon gate 4 of the gate structure of the device cell region. As shown in fig. 4K, fig. 4K shows the lead-out position region of the gate structure, and it can be seen that the width of the gate trench 201 at the lead-out position of the gate structure meets the requirement of forming the contact hole 10, so in fig. 4K, an opening 206 of the contact hole 10 is formed at the top of the polysilicon gate 4 at the lead-out position of the gate structure.
Generally, after the openings 206 and 206a are formed, a step of performing a body region extraction region implantation of heavily doped ions of the second conductivity type is further included, and the body region extraction region implantation forms a body region extraction region at the bottom of the openings 206 and 206a corresponding to the source regions 6 so as to realize the subsequent ohmic contact between the contact holes 10 and the body regions 5.
Then, the opening 206 and the opening 206a are filled with a metal such as tungsten to form the contact hole 10.
The above-described process of forming the contact hole 10 corresponds to the fifth layer photolithography process in fig. 3.
As shown in fig. 4L, a front metal layer 11 is formed, and the front metal layer 11 is patterned by using a lithography definition and etching process. The patterned front-side metal layer 11 typically forms a source electrode structure connected to the source regions 6 and the body regions 5 and a gate electrode structure connected to the polysilicon gate 4. The gate electrode structure is in contact with the polysilicon gate 4 through the contact hole 10 at the lead-out position of the gate electrode structure.
The formation process of the front metal layer 11 corresponds to the sixth photolithography process in fig. 3.
As shown in fig. 4M, a contact pad is formed, and a formation region of the contact pad is defined by photolithography. The contact pad is typically composed of the topmost front side metal layer 11. The contact pad includes a source electrode pad leading out the source electrode structure and a gate electrode pad leading out the gate electrode structure. The formation process of the contact pad corresponds to the seventh photolithography process in fig. 3.
And 7, finishing the back process of the super junction device. The back process of the super junction device comprises the following steps:
and thinning the back of the semiconductor substrate 1.
Directly using the thinned semiconductor substrate 1 as the drain region, and then requiring the semiconductor substrate 1 to have the first conductivity type heavy doping. Can also be: and performing back injection of the first conductive type heavy doping on the thinned semiconductor substrate to form a drain region.
And forming a back metal layer 12 on the back of the drain region. In the embodiment of the present invention, the back process of the super junction device does not need to adopt the photolithography definition, so the back process of the super junction device is included in the seventh photolithography process in fig. 3.
In the embodiment of the invention, the super junction device is an N-type device, the first conduction type is an N-type device, and the second conduction type is a P-type device; in other embodiments can also be: the super junction device is a P-type device, the first conduction type is a P-type device, and the second conduction type is an N-type device.
In the embodiment of the invention, the leading-out of the grid structure of the super junction device is also set to be led out through the contact hole at the top of the trench grid structure, so that the grid structure can be formed by adopting a trench grid process and can be well flattened; the characteristic of realizing flatness after the grid structure is formed enables the groove grid process of the invention to be conveniently arranged before the super junction forming process, and to be conveniently flattened after the super junction is formed, finally, the full flat process can be realized, and the process difficulty of the device can be greatly reduced; the trench gate process is arranged before the super junction forming process, so that a plurality of unexpected technical effects can be brought, and the technical effects comprise:
the method can eliminate the influence of the thermal process of the forming process of the grid structure on the super junction, the thermal process of the forming process of the grid structure mainly comprises the forming process of the sacrificial oxide layer and the forming process of the grid oxide layer 3, the thermal process of the grid structure is large, and the influence on the mutual diffusion of PN impurities of the super junction can be greatly reduced, so that the technical problem of the invention can be well solved, and finally the performance of the device is improved.
Secondly, because the forming process of the gate structure is positioned before the forming process of the super junction, the adverse effect of the thermal process on the super junction is not required to be considered in the forming process of the gate structure, so that the use of the thermal process of the forming process of the gate structure is not limited, and the gate structure with better quality can be obtained.
Thirdly, in the prior art, two times of body region 5 injection and propulsion are adopted, and one time of body region 5 injection and propulsion is arranged after the gate structure is formed, so that the thermal process of the next time of body region 5 propulsion still has adverse effect on the super junction, however, in the embodiment of the invention, the forming process of the gate structure is arranged before the forming process of the super junction, and the injection and propulsion processes of the body region 5 can be arranged before the forming process of the super junction, so that the embodiment of the invention can also prevent the adverse effect of the thermal process of the body region 5 propulsion on the super junction, and further improve the performance of the device.
Thirdly, because the forming process of the grid structure is placed before the forming process of the super junction, the surface of the device unit area is originally exposed when the grid structure is formed, and the forming and etching processes of the field oxide 8 are not needed to expose the device unit area, so that the photoetching defining process of the field oxide 8 can be saved, and a layer of photomask related to the etching of the field oxide 8 can be saved.
Since the field oxide 8 on the top of the device unit region is not required to be removed, the edge of the device unit region and the terminal region is not provided with a climbing structure of the field oxide 8, the surface of the whole field oxide 8 is in a flat structure, and the interlayer film 9 is also in a flat structure after being formed on the field oxide 8, so that the interlayer film 9 is not required to be planarized by adopting a BPSG (band gap glass) reflow process, the adverse effect of the thermal process of the BPSG reflow process on the super junction can be further reduced, and the performance of the device can be further improved.
In addition, in the embodiment of the invention, because the gate structure is formed before the formation process of the super junction, the formation process of the source region 6 including the implantation and the annealing propulsion process can also be arranged before the formation process of the super junction, so that the adverse effect of the thermal process of the propulsion process of the source region 6 on the super junction can be further reduced, and the performance of the device can be further improved.
In the embodiment of the present invention, by setting the process sequence of the gate structure, in addition to obtaining the beneficial effects related to the reduction of the thermal process of the super junction, the embodiment of the present invention can also save the photomask, and the following specific descriptions are provided:
first, the above-described photolithographic definition process of the field oxide 8 can be saved.
Secondly, when a grid structure is formed on the wafer firstly and then the body region 5 is formed, the photoetching of the body region 5 can be directly aligned by adopting the grid structure without adopting a zero-level alignment mark, so that the zero-level photomask can be saved.
In the embodiment of the invention, the contact hole 10 can be directly formed at the top of the leading-out position of the gate structure to lead out the gate structure, the polysilicon gate 4 of the gate structure does not need to extend to the top of the field oxide 8 through climbing, and then the contact hole 10 is formed on the polysilicon at the top of the field oxide 8 to lead out the gate structure, so that the polysilicon climbing to the top of the field oxide 8 does not need to be defined by photoetching by adopting a photoetching process, and a photomask defined by photoetching of the polysilicon can be saved.
Therefore, the embodiment of the invention can save a plurality of layers of photomasks and can greatly reduce the process cost.
In addition, in the embodiment of the invention, after the gate structure is formed, the step of forming the sealing layer 302 on the top of the polysilicon gate 4 is added, the sealing layer 302 can prevent the impurities of the polysilicon gate 4 from expanding outwards in the thermal process of a subsequent process such as a furnace tube, the impurities expanding outwards of the polysilicon gate 4 can affect process equipment, thereby affecting the film forming quality of wafer products in the same batch or other batches produced in the same process equipment, and also affecting the film forming quality of the wafer per se, so that after the sealing layer 302 is added on the top of the polysilicon gate 4, the impurities of the polysilicon gate 4 can be prevented from expanding outwards without affecting the surface flatness of the first epitaxial layer, thereby improving the film forming quality of the product. As shown in fig. 4G1, after the super junction formation process is completed; if the sealing layer 302 is not formed before the furnace process is performed, the doping impurities of the polysilicon gate 4, such as phosphorus (P), may generate an outward expansion, which may not only affect the film forming quality of the same wafer, but also pollute the furnace equipment, thereby affecting the film forming quality of the wafer products of the same batch or other subsequent batches generated in the furnace.
The sealing layer 302 on the top of the polysilicon gate 4 in the embodiment of the invention can also protect the gate oxide layer 3, and can prevent the subsequent etching process such as wet etching from damaging the gate oxide layer 3, thereby improving the reliability of the gate structure. As shown in fig. 4F-4G1, in the super junction forming process, an etching process of the second bottom oxide layer 202, the middle nitride layer 203 and the top oxide layer 204 of the second hard mask layer is performed, and if the seal layer 302 is not formed, the etching process for removing the second bottom oxide layer 202, the middle nitride layer 203 and the top oxide layer 204 will have an etching effect on the gate oxide layer 3 on the top of the gate trench 201, thereby affecting the reliability of the gate oxide layer 3 and the reliability of the gate structure.
The method of the embodiment of the invention can also be used for carrying out various changes to form various other embodiments, such as:
in the first modified embodiment method, the process for forming the body region 5 is provided before the first step, and before forming the body region 5, the method further includes a step of performing photolithography using a zeroth-layer photomask and forming a zeroth-layer alignment mark.
In a second alternative embodiment, the formation process of the source region 6 is arranged after step three.
In a third alternative embodiment method, the process for forming the field oxide 8 is performed before the third step; at this time, the sealing layer 302 is directly formed by the thermal oxide layer of the field oxide 8 in the top recess 301, and the top surface of the thermal oxide layer of the field oxide 8 is a flat structure by utilizing the characteristic that the thermal oxidation rate of the polysilicon layer is greater than the thermal oxidation rate of the first epitaxial layer 2.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A manufacturing method of a super junction device is characterized in that the manufacturing method is realized by adopting a full flat process, and a forming process of a grid structure is positioned before the forming process of a super junction, and the manufacturing method comprises the following steps:
step one, forming the grid structure, wherein the grid structure is a groove grid, and the forming process of the groove grid comprises the following steps:
providing a first epitaxial layer with a first conductivity type, and defining a forming region of a grid groove by a photoetching process;
etching the first epitaxial layer to form the gate trench, wherein the width of the gate trench at the leading-out position of the gate structure meets the requirement of forming a contact hole;
forming a gate oxide layer on the side surface of the gate trench, and forming a bottom oxide layer on the bottom surface of the gate trench;
filling a polysilicon gate with second conductivity type heavy doping in the gate trench, wherein the gate oxide layer, the bottom oxide layer and the polysilicon gate formed in the gate trench form the trench gate;
carrying out first planarization to enable the surface of the first epitaxial layer with the trench gate to be a flat surface;
step two, carrying out a sealing treatment process of the polysilicon gate, comprising the following steps of:
back-etching the polysilicon gate to enable the top surface of the polysilicon gate to be lower than the surface of the first epitaxial layer and form a top recess, wherein the depth of the top recess is smaller than that of the source region;
a sealing layer consisting of a dielectric layer is filled in the top recess, the surface of the sealing layer is level to that of the first epitaxial layer, and the sealing layer prevents the doping of the polysilicon gate from expanding outwards and protects the gate oxide layer;
step three, performing a super junction forming process, comprising:
performing a photoetching process on the flat surface of the first epitaxial layer on which the trench gate is formed to define a formation region of a super junction trench;
etching the first epitaxial layer to form a super junction groove;
filling a second epitaxial layer of a second conductivity type in the super junction trench, forming a second conductivity type column by the second epitaxial layer filled in the super junction trench, forming a first conductivity type column by the first epitaxial layer between the second conductivity type columns, and alternately arranging the first conductivity type column and the second conductivity type column to form the super junction;
and carrying out second planarization to enable the surface of the first epitaxial layer formed with the super junction to be a flat surface.
2. The method of manufacturing a super junction device of claim 1, wherein: in the first step, before the photoetching process for defining the grid groove, a step of forming a first hard mask layer on the surface of the first epitaxial layer is also included, and then the first hard mask layer is etched firstly and then the first epitaxial layer is etched to form the grid groove;
removing the first hard mask layer after the first planarization is stopped on the first hard mask layer.
3. The method of manufacturing a super junction device of claim 1, wherein: in the first step, the method further comprises a step of rounding the gate trench after the gate trench is etched and before the gate oxide layer is formed, wherein the rounding comprises the following steps:
forming a first sacrificial oxide layer by adopting a thermal oxidation process;
and removing the first sacrificial oxide layer.
4. The method of manufacturing a super junction device of claim 3, wherein: the gate oxide layer is formed on the side face of the grid groove by adopting a thermal oxidation process.
5. The method of manufacturing a super junction device of claim 4, wherein: the bottom oxide layer and the gate oxide layer are formed simultaneously by adopting the same process;
or the thickness of the bottom oxide layer is larger than that of the gate oxide layer, and the bottom oxide layer and the gate oxide layer are formed separately.
6. The method of manufacturing a super junction device of claim 1, further comprising the steps of:
forming a body region by adopting an ion implantation and annealing propulsion process, wherein the forming region of the body region is defined by photoetching;
forming a source region by adopting an ion implantation and annealing propulsion process, wherein the forming region of the source region is defined by photoetching, and the source region is self-aligned with the side surface of the corresponding grid structure in the device unit region;
forming field oxygen, wherein the field oxygen covers the first epitaxial layer which is formed with the super junction and the trench gate and has a flat surface, and the field oxygen has a flat structure without climbing;
the formation process of the body region and the formation process of the source region are disposed before the formation process of the field oxide.
7. The method of manufacturing a super junction device of claim 6, wherein: before the third step of the formation process of the field oxygen is arranged;
the field oxide is composed of a thermal oxide layer or an oxide layer formed by superposing the thermal oxide layer with a TEOS (tetraethyl orthosilicate) oxidation process, the thermal oxide layer of the field oxide is formed by a thermal oxidation process, the sealing layer is directly composed of the thermal oxide layer of the field oxide positioned in the top recess, and the top surface of the thermal oxide layer of the field oxide is of a flat structure by utilizing the characteristic that the thermal oxidation rate of the polysilicon gate is greater than that of the first epitaxial layer.
8. The method of manufacturing a super junction device of claim 6, wherein: after the step III, the field oxygen forming process is arranged;
the forming process of the body region is arranged before the first step, and the forming process further comprises the steps of carrying out photoetching by adopting a zero-layer photomask and forming a zero-layer alignment mark before the body region is formed; or, the forming process of the body region is arranged after the first step and before the third step;
the forming process of the source region is arranged after the first step and before the third step; or, the forming process of the source region is arranged after the third step.
9. The method of manufacturing a super junction device of claim 6, wherein: after the field oxygen is formed, the method further comprises the following steps:
forming an interlayer film and a contact hole, wherein the forming area of the contact hole is defined by photoetching, and the corresponding contact hole is formed at the leading-out position of the grid structure;
forming a front metal layer, and patterning the front metal layer by adopting a photoetching definition and etching process, wherein an electrode formed by the patterned front metal layer comprises a gate electrode structure, and the gate electrode structure is contacted with the polysilicon gate through the contact hole at the leading-out position of the gate electrode structure;
forming a contact pad, wherein a forming area of the contact pad is defined by photoetching;
and finishing the back process of the super junction device.
10. The method of manufacturing a super junction device of claim 9, wherein: the interlayer film covers the flat field oxide surface;
the interlayer film is formed by a USG oxidation process or a TEOS oxidation process.
11. The method of manufacturing a super junction device of claim 8, wherein: in the third step, a second hard mask layer is adopted in the super junction forming process, the second hard mask layer is formed by overlapping a second bottom oxide layer, a middle nitride layer and a top oxide layer, and the super junction forming process comprises the following steps when the second hard mask layer is adopted:
forming the second hard mask layer;
defining a forming area of the super junction groove by adopting a photoetching process;
sequentially etching the second hard mask layer and the first epitaxial layer to form the super junction groove;
removing the top oxide layer of the second hard mask layer, forming a second sacrificial oxide layer by adopting a thermal oxidation process, and then removing the second sacrificial oxide layer;
removing the middle nitriding layer of the second hard mask layer;
carrying out epitaxial filling in the super junction groove to form the second epitaxial layer;
performing a chemical mechanical polishing process on the second epitaxial layer to achieve the second planarization, so that the second epitaxial layer is only filled in the super junction trench;
and completely removing or only partially removing the second bottom oxide layer of the second hard mask layer.
12. The method of manufacturing a super junction device of claim 11, wherein: the second bottom oxide layer is formed by adopting a thermal oxidation process, the closed layer is directly formed by the second bottom oxide layer positioned in the top recess, and the top surface of the second bottom oxide layer is of a flat structure by utilizing the characteristic that the thermal oxidation rate of the polysilicon gate is greater than that of the first epitaxial layer.
13. The method of manufacturing a super junction device of claim 1, 7 or 12, wherein: the depth of the top recess is
14. The method of manufacturing a super junction device of claim 9, wherein: the first epitaxial layer is formed on the semiconductor substrate, and the back process of the super junction device comprises the following steps:
thinning the back of the semiconductor substrate;
directly taking the thinned semiconductor substrate as the drain region, or performing back injection of first conductivity type heavy doping on the thinned semiconductor substrate to form the drain region;
and forming a back metal layer on the back of the drain region.
15. The method of manufacturing a super junction device of claim 1, wherein: the first planarization is realized by a back etching process or a chemical mechanical polishing process.
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| CN202010867039.9A CN111986997A (en) | 2020-08-26 | 2020-08-26 | Method for manufacturing super junction device |
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| CN114023650A (en) * | 2021-10-18 | 2022-02-08 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction device |
| CN114023649A (en) * | 2021-10-18 | 2022-02-08 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction device |
| WO2023066096A1 (en) * | 2021-10-20 | 2023-04-27 | 上海华虹宏力半导体制造有限公司 | Super junction device and manufacturing method therefor |
| CN116646251A (en) * | 2023-07-27 | 2023-08-25 | 北京智芯微电子科技有限公司 | Super junction device manufacturing method, super junction device, chip and circuit |
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