CN107799601B - Shielded gate trench power MOSTET device and method of making same - Google Patents

Shielded gate trench power MOSTET device and method of making same Download PDF

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CN107799601B
CN107799601B CN201710903865.2A CN201710903865A CN107799601B CN 107799601 B CN107799601 B CN 107799601B CN 201710903865 A CN201710903865 A CN 201710903865A CN 107799601 B CN107799601 B CN 107799601B
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deep
source
polysilicon
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dielectric layer
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CN107799601A (en
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颜树范
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

The invention discloses a power MOSTET device of a shielded gate groove, wherein a grid structure of a unit area comprises: the first deep grooves are internally provided with a bottom dielectric layer, a source electrode polysilicon gate, a gate dielectric layer, a polysilicon gate and an inter-polysilicon dielectric layer; and the second deep grooves are communicated with all the first deep grooves, the process conditions of the two deep grooves are the same, a bottom dielectric layer and source polysilicon are formed in the second deep grooves, two sides of the source polysilicon in the second deep grooves are protected by the bottom dielectric layer, first contact holes are formed at the tops of the second deep grooves, the width of each first contact hole is larger than or equal to that of the second deep groove, and the bottoms of the first contact holes are in contact with the source polysilicon of the second deep grooves to realize the leading-out of the source polysilicon of each first deep groove. The invention also discloses a manufacturing method of the shielding grid groove power MOSTET device. The invention can lead out thinner source electrode polycrystalline silicon without adding extra photoetching technology.

Description

Shielded gate trench power MOSTET device and method of making same
Technical Field
The invention relates to a semiconductor integrated circuit manufacturing method, in particular to a Shielded Gate (SGT) groove power MOSTET device; the invention also relates to a manufacturing method of the shielded gate trench power MOSTET device.
Background
Fig. 1 is a schematic diagram of a device structure of a first conventional shielded gate trench power mosfet device; the shielded gate trench power MOSTET device comprises an active region, a gate bus and a terminal region, wherein the active region is used for forming a unit structure of the device, and the terminal region is arranged on the periphery side of the active region. Taking an N-type device as an example, the device structure comprises:
a drift region 101 composed of an N-type doped semiconductor substrate such as a silicon substrate 101, a body region 105 composed of a P-well formed in a selected region of the surface of the drift region 101, and a source region 106 composed of an N + region formed on the surface of the body region 105.
The gate structure includes a bottom dielectric layer, such as an oxide layer 102, formed on the bottom surface and the side surface of the trench, and a gap formed by the bottom dielectric layer 102 is filled with source polysilicon 103. Removing the bottom dielectric layers 102 on two sides of the top of the source polysilicon 103 to form a top groove, forming a gate dielectric layer such as a gate oxide layer on the side surface of the semiconductor substrate of the top groove and forming a polysilicon dielectric layer on the side surface of the source polysilicon 103; a polysilicon gate 104 fills the top trench.
Contact holes 107a are formed through the interlayer film 108 at the top of the polysilicon gates 104 in the gate bus region, the top of the contact holes 107a are connected to the gate bus composed of the front metal layer, and each polysilicon gate 104 in the active region is connected to the polysilicon gate 104 in the gate bus region and to the gate bus through the contact holes 107 a.
Contact holes 107b are formed at the top of the source regions 106, and the tops of the contact holes 107b contact through the source regions 106 and the body regions 105 at the bottoms; preferably, a well contact region composed of a P + region is formed at the bottom of the contact hole 107 b.
Contact holes 107c are formed on top of the source polysilicon 103 at the outermost sides of the active region, and the contact holes 107b and 107c are connected to the source composed of the front metal layer 109.
A drain region composed of an N + region is formed on the back surface of the drift region 101 and a drain composed of a back metal layer 110 is formed on the back surface of the drain region.
The advantage of the structure shown in fig. 1 is that the contact holes 107a and 107c are directly punched on top of the polysilicon, and no additional lithography is required to define the extraction polysilicon. Namely, the shielded gate trench power mosfet device shown in fig. 1 is structured as a Mask-minimum (Mask). Considering the minimum lithographic line width and the one-sided registration deviation (OVL), each polysilicon line width needs to be larger than the sum of the contact hole line width and 2 times of the one-sided registration deviation, such as: the minimum photoetching line width is 0.3 mu m and the unilateral OVL is 0.1 mu m, and the final strip width of the polycrystalline silicon is more than 0.5 mu m. When the length of the polysilicon does not satisfy the above design rule, the source/gate short circuit or the drain point is larger, as shown by the dotted circle 201 in fig. 1, the width requirement of the source polysilicon 103 is usually smaller, and at this time, the contact hole 107c may be short-circuited with the polysilicon gate 104 due to the registration deviation of the photolithography. An enlarged view of the dashed circle 201 is shown in fig. 2, and the area indicated by reference numeral 202 in fig. 2 represents an area where the source/gate short or drain is large.
When the width or length of the polysilicon does not satisfy the above design requirements, the situation shown in fig. 2 may occur, so that the lead-out structure of the contact hole needs to be specially designed, as shown in fig. 3, which is a schematic view of a device structure of a second conventional shielded gate trench power mosfet device; in fig. 3, the top of the source polysilicon 103 at the outermost side of the active region is not directly connected to the contact hole 107c, but the source polysilicon 103 is led out to the terminal region through the polysilicon line 103a, so that the size of the polysilicon line 103a can be increased, and the line width and the registration accuracy of the contact hole 107c do not affect the structure in the trench, thereby eliminating the disadvantages of the structure shown in fig. 1. However, as shown in fig. 3, an additional photolithography plate is required to define the polysilicon line 103a, which increases the cost.
Disclosure of Invention
The invention aims to solve the technical problem of providing a power MOSTET device for a shielded gate groove, which can lead out thinner source electrode polycrystalline silicon without adding extra photoetching technology. Therefore, the invention also provides a manufacturing method of the shielded gate trench power MOSTET device.
In order to solve the above technical problem, the gate structure of the device unit region of the shielded gate trench power mosfet device provided by the present invention comprises:
the semiconductor device comprises a plurality of first deep trenches formed in a semiconductor substrate, wherein bottom dielectric layers are formed on the bottom surfaces and the side faces of the first deep trenches.
The bottom dielectric layer does not completely fill the first deep trench and a gap region is formed in the central region of the first deep trench; and filling the gap region with source polysilicon.
And removing the bottom dielectric layer on the side surface of the top area of the first deep groove and forming top grooves on two sides of the source polycrystalline silicon in the top area of the first deep groove.
And the gate dielectric layer is formed on the side surface of the top groove positioned on one side of the semiconductor substrate, and the inter-polycrystalline silicon dielectric layer is formed on the side surface of the top groove positioned on one side of the source polycrystalline silicon.
And filling a polysilicon gate in the top groove with the side surfaces formed with the gate dielectric layer and the inter-polysilicon dielectric layer.
At least one second deep groove communicated with all the first deep grooves, wherein the process conditions of the second deep groove and the first deep grooves are the same, the bottom dielectric layer and the source polysilicon which are the same as those in the first deep grooves are formed in the second deep groove, the source polysilicon in the second deep groove is connected with the source polysilicon in the first deep groove, two sides of the source polysilicon in the second deep groove are protected by the bottom dielectric layer, a first contact hole is formed at the top of the second deep groove, the width of the first contact hole is larger than or equal to that of the second deep groove, and the bottom of the first contact hole is contacted with the source polysilicon in the second deep groove to realize the leading-out of the source polysilicon in each first deep groove.
The semiconductor substrate is doped with a first conductive type, a well region of a second conductive type is formed on the surface of the semiconductor substrate, the polysilicon gate penetrates through the well region, and the surface of the well region covered by the side face of the polysilicon gate is used for forming a channel.
And a source region heavily doped with the first conduction type is formed on the surface of the well region.
An interlayer film, the first contact hole, the second contact hole, the third contact hole and a front metal layer are further formed on the front surface of the semiconductor substrate, a source electrode and a grid electrode are formed by photoetching and etching the front metal layer, the source electrode is in contact with the source region through the second contact hole, and the grid electrode is in contact with the polysilicon gate through the third contact hole.
The drain region is composed of a first conductive type heavily doped region formed on the back of the thinned semiconductor substrate, and a back metal layer is formed on the back of the drain region to serve as a drain electrode.
In a further improvement, the second contact hole contacts the well region through the source region.
In a further improvement, a well region contact region heavily doped with the second conductive type is formed at the bottom of the second contact hole.
The further improvement is that the bottom dielectric layer is an oxide layer, and the gate dielectric layer is an oxide layer.
The further improvement is that the shielded gate trench power MOSTET device is an N-type device, the first conductivity type is an N-type, the second conductivity type is a P-type, and the semiconductor substrate is doped with an N-type; or, the shielding grid groove power MOSTET device is a P-type device, the first conduction type is a P type, the second conduction type is an N type, and the semiconductor substrate is doped in a P type.
In a further improvement, the semiconductor substrate is a silicon substrate.
In order to solve the technical problem, the gate structure of the device unit area in the manufacturing method of the shielded gate trench power MOSTET device provided by the invention is formed by adopting the following steps:
providing a semiconductor substrate, and forming a plurality of first deep grooves and at least one second deep groove in the semiconductor substrate by adopting a photoetching process.
Secondly, forming a bottom dielectric layer on the bottom surface and the side surface of the first deep groove; the bottom dielectric layer does not completely fill the first deep trench and a gap region is formed in the central region of the first deep trench; and simultaneously forming the bottom dielectric layer in the second deep trench and simultaneously forming the gap region in the second deep trench.
Step three, depositing polycrystalline silicon, forming source polycrystalline silicon in the first deep groove and the second deep groove at the same time, and completely filling the corresponding gap regions; the source polysilicon in the second deep trench is connected to the source polysilicon in the first deep trench.
Etching the bottom dielectric layer in the top area of the first deep groove to form top grooves on two sides of the source electrode polycrystalline silicon in the top area of the first deep groove; the bottom dielectric layer of the second deep trench is protected from etching.
And fifthly, forming a gate dielectric layer on the side surface of the top groove in the first deep groove, which is positioned on one side of the semiconductor substrate, and forming an inter-polysilicon dielectric layer on the side surface of the top groove, which is positioned on one side of the source electrode polysilicon.
And sixthly, depositing polycrystalline silicon, filling the polycrystalline silicon in the top groove and forming a polycrystalline silicon gate.
Seventhly, forming an interlayer film, and performing photoetching to form first contact holes penetrating through the interlayer film at the tops of the second deep trenches, wherein the width of each first contact hole is larger than or equal to that of the second deep trench, the bottoms of the first contact holes are contacted with the source polycrystalline silicon of the second deep trenches, and the source polycrystalline silicon of each first deep trench is led out.
In a further improvement, the semiconductor substrate is doped with the first conductivity type, and after the gate structure is formed, the method further includes the following steps:
step eight, performing ion implantation to form a well region of a second conductivity type in the semiconductor substrate; performing source injection of first conductive type heavy doping to form a source region on the surface of the well region; carrying out thermal annealing propulsion process on the well region and the source region; the surface of the well region which is covered by the side face of the polysilicon gate is used for forming a channel.
And step nine, forming an interlayer film, the first contact hole, the second contact hole, the third contact hole and a front metal layer on the front surface of the semiconductor substrate, carrying out photoetching on the front metal layer to form a source electrode and a grid electrode, wherein the source electrode is contacted with the source region through the second contact hole, and the grid electrode is contacted with the polysilicon gate through the third contact hole.
And step ten, thinning the back surface of the semiconductor substrate, forming a drain region with the first conduction type heavily doped, and forming a back metal layer on the back surface of the drain region to serve as a drain electrode.
In a further improvement, the second contact hole contacts the well region through the source region.
In a further improvement, after the opening of the second contact hole is formed and before the metal is filled in the ninth step, a step of performing second conductive type heavy doping injection on the bottom of the second contact hole to form a well region contact region is further included.
The further improvement is that the bottom dielectric layer is an oxide layer, and the gate dielectric layer is an oxide layer.
The further improvement is that the shielded gate trench power MOSTET device is an N-type device, the first conductivity type is an N-type, the second conductivity type is a P-type, and the semiconductor substrate is doped with an N-type; or, the shielding grid groove power MOSTET device is a P-type device, the first conduction type is a P type, the second conduction type is an N type, and the semiconductor substrate is doped in a P type.
In a further improvement, a first conductive type epitaxial layer is formed on the surface of the semiconductor substrate, and the first deep trench and the second deep trench are both formed in the first conductive type epitaxial layer.
In a further improvement, the semiconductor substrate is a silicon substrate.
The invention adds a second deep groove communicated with all the first deep grooves in an active area, namely a device unit area, the second deep groove and the first deep groove are formed by adopting the same process, meanwhile, the second deep groove is filled with a bottom dielectric layer and source polysilicon which are the same as those in the first deep groove, polysilicon gates are not formed on two sides of the top of the source polysilicon of the second deep groove, but the bottom dielectric layer is reserved, so that a contact hole, namely a first contact hole, with the width larger than that of the second deep groove can be formed at the top of the second deep groove, the source polysilicon in the first deep groove is connected to the source polysilicon in the second deep groove and is connected to a source through the first contact hole, the photoetching process parameter of the first contact hole is not influenced by the width of the source polysilicon, and the influence of the line width and unilateral registration deviation of the source polysilicon when the contact hole is directly formed at the top of the source polysilicon in the prior art can be eliminated Short circuit or large grid source drain point. Therefore, the invention can lead out thinner source electrode polycrystalline silicon without adding extra photoetching technology, and the thinner source electrode polycrystalline silicon is beneficial to reducing the size of the device and increasing the performance of the device.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic diagram of a device structure of a first prior art shielded gate trench power mosfet device;
FIG. 2 is an enlarged view of FIG. 1 at dashed circle 201;
fig. 3 is a schematic diagram of a device structure of a second prior art shielded gate trench power mosfet device;
fig. 4 is a schematic device structure diagram of a shielded gate trench power mosfet device according to an embodiment of the invention;
fig. 5A-5H are schematic diagrams of device structures in various steps of a method according to an embodiment of the invention.
Detailed Description
Fig. 4 is a schematic diagram of a device structure of a shielded gate trench power mosfet device according to an embodiment of the present invention; the gate structure of the device unit area of the shielded gate trench power MOSTET device comprises the following components:
a plurality of first deep trenches 301 are formed in a semiconductor substrate 1, and bottom dielectric layers 2 are formed on the bottom surfaces and the side surfaces of the first deep trenches 301. Preferably, the semiconductor substrate 1 is a silicon substrate; the bottom dielectric layer 2 is an oxide layer.
The bottom dielectric layer 2 does not completely fill the first deep trench 301 and forms a gap region in the central region of the first deep trench 301; and filling the gap region with source polysilicon 3.
The bottom dielectric layer 2 on the side of the top region of the first deep trench 301 is removed and a top trench is formed on both sides of the source polysilicon 3 in the top region of the first deep trench 301.
And the gate dielectric layer is formed on the side surface of the top groove on one side of the semiconductor substrate 1, and the inter-polycrystalline silicon dielectric layer is formed on the side surface of the top groove on one side of the source polycrystalline silicon 3. Preferably, the gate dielectric layer is an oxide layer.
And the top groove with the side surfaces formed with the gate dielectric layer and the inter-polysilicon dielectric layer is filled with a polysilicon gate 4.
At least one second deep trench 302 communicated with all the first deep trenches 301, the process conditions of the second deep trench 302 and the first deep trenches 301 are the same, the bottom dielectric layer 2 and the source polysilicon 3 are formed in the second deep trench 302 the same as in the first deep trench 301, the source polysilicon 3 in the second deep trench 302 is connected to the source polysilicon 3 in the first deep trench 301, both sides of the source polysilicon 3 in the second deep trench 302 are protected by the bottom dielectric layer 2, first contact holes 8a are formed at the top of the second deep trench 302, the width of the first contact holes 8a is greater than or equal to the width of the second deep trench 302, and the bottom of the first contact holes 8a contacts with the source polysilicon 3 of the second deep trench 302 to lead out the source polysilicon 3 of each first deep trench 301.
The semiconductor substrate 1 is doped with a first conduction type, a well region 5 of a second conduction type is formed on the surface of the semiconductor substrate 1, the polysilicon gate 4 penetrates through the well region 5, and the surface of the well region 5 covered by the side surface of the polysilicon gate 4 is used for forming a channel.
A source region 6 heavily doped with the first conductivity type is formed on the surface of the well region 5.
An interlayer film 7, the first contact hole 8a, the second contact hole 8b, the third contact hole 8c and a front metal layer 9 are further formed on the front surface of the semiconductor substrate 1, a source electrode and a gate electrode are formed by photoetching and etching the front metal layer 9, the source electrode is in contact with the source region 6 through the second contact hole 8b, and the gate electrode is in contact with the polysilicon gate 4 through the third contact hole 8 c.
The drain region is composed of a first conductive type heavily doped region formed on the back surface of the thinned semiconductor substrate 1, and a back metal layer 11 is formed on the back surface of the drain region to serve as a drain.
The second contact hole 8b contacts the well region 5 through the source region 6. A well region contact region 10 heavily doped with the second conductive type is formed at the bottom of the second contact hole 8 b.
In the embodiment of the invention, the shielding gate trench power MOSTET device is an N-type device, the first conduction type is an N-type device, the second conduction type is a P-type device, and the semiconductor substrate 1 is doped with an N-type device. Other embodiments can also be: the shielding grid groove power MOSTET device is a P-type device, the first conduction type is a P type, the second conduction type is an N type, and the semiconductor substrate 1 is doped in a P type mode.
In the embodiment of the invention, one second deep trench 302 communicated with all the first deep trenches 301 is added in the active region 6, namely the device unit region, the second deep trench 302 and the first deep trench 301 are formed by adopting the same process, meanwhile, the second deep trench 302 is filled with the bottom dielectric layer 2 and the source polysilicon 3 which are the same as those in the first deep trench 301, the polysilicon gate 4 is not formed on two sides of the top of the source polysilicon 3 of the second deep trench 302, but the bottom dielectric layer 2 is reserved, so that a contact hole with the width larger than that of the second deep trench 302, namely a first contact hole 8a, can be formed on the top of the second deep trench 302, the source polysilicon 3 in the first deep trench 301 is connected to the source polysilicon 3 in the second deep trench 302 and is connected to the source through the first contact hole 8a, and thus the photoetching process parameters of the first contact hole 8a cannot be influenced by the width of the source polysilicon 3, the technical problem that in the prior art, when a contact hole is directly formed at the top of the source electrode polycrystalline silicon 3, the gate source short circuit or the large gate source drain point is caused by the influence of the line width of the source electrode polycrystalline silicon 3 and the unilateral registration deviation can be solved. Therefore, the invention can lead out thinner source polysilicon 3 without adding extra photoetching process, and the thinner source polysilicon 3 is beneficial to reducing the size of the device and increasing the performance of the device.
As shown in fig. 5A to 5H, which are schematic views of device structures in steps of a method according to an embodiment of the present invention, a gate structure of a device unit region in a method for manufacturing a shielded gate trench power mosfet device according to an embodiment of the present invention is formed by the following steps:
step one, as shown in fig. 5A, a semiconductor substrate such as a silicon substrate 1 is provided, and a plurality of first deep trenches 301 and at least one second deep trench 302 are formed in the semiconductor substrate 1 by using a photolithography and etching process. The deep trenches 301 and 302 are defined with a hard mask layer 303. A first conductive type epitaxial layer is formed on the surface of the semiconductor substrate 1, the first deep trench 301 and the second deep trench 302 are both formed in the first conductive type epitaxial layer, and a drift region is formed by the first conductive type epitaxial layer 1.
Step two, as shown in fig. 5B, a bottom dielectric layer 2 is formed on the bottom surface and the side surface of the first deep trench 301; the bottom dielectric layer 2 does not completely fill the first deep trench 301 and forms a gap region in the central region of the first deep trench 301; the bottom dielectric layer 2 is also formed in the second deep trench 302 at the same time, and the gap region is also formed in the second deep trench 302 at the same time. Preferably, the bottom dielectric layer 2 is an oxide layer.
Step three, as shown in fig. 5C, depositing polysilicon and simultaneously forming source polysilicon 3 in the first deep trench 301 and the second deep trench 302 to completely fill the corresponding gap region; the source polysilicon 3 in the second deep trench 302 is connected to the source polysilicon 3 in the first deep trench 301.
Step four, as shown in fig. 5D, etching the bottom dielectric layer 2 in the top region of the first deep trench 301 to form top trenches 304 on two sides of the source polysilicon 3 in the top region of the first deep trench 301; the bottom dielectric layer 2 of the second deep trench 302 is protected from etching.
Step five, as shown in fig. 5E, a gate dielectric layer is formed on the side surface of the top trench 304 in the first deep trench 301, which is located at one side of the semiconductor substrate 1, and an inter-polysilicon dielectric layer is formed on the side surface of the top trench 304, which is located at one side of the source polysilicon 3. Preferably, the gate dielectric layer is an oxide layer.
Step six, as shown in fig. 5E, polysilicon deposition is performed to fill the top trench 304 with polysilicon and form a polysilicon gate 4.
Seventhly, as shown in fig. 5G, an interlayer film 7 is formed, a first contact hole 8a penetrating through the interlayer film 7 is formed at the top of the second deep trench 302 by performing photolithography etching, the width of the first contact hole 8a is greater than or equal to the width of the second deep trench 302, and the bottom of the first contact hole 8a contacts with the source polysilicon 3 of the second deep trench 302 to lead out the source polysilicon 3 of each first deep trench 301.
The semiconductor substrate 1 is doped with a first conductive type, and after a gate structure is formed, the method further comprises the following steps:
step eight, as shown in fig. 5F, performing ion implantation to form a well region 5 of the second conductivity type in the semiconductor substrate 1; performing source injection of first conductive type heavy doping to form a source region 6 on the surface of the well region 5; carrying out thermal annealing propulsion process on the well region 5 and the source region 6; the surface of the well region 5 laterally covered by the polysilicon gate 4 is used to form a channel. Step eight of the embodiment of the present invention is performed before the formation of the interlayer film 7 of step seven.
Step nine, as shown in fig. 5G, an interlayer film 7, the first contact hole 8a, the second contact hole 8b, the third contact hole 8c and a front metal layer 9 are further formed on the front surface of the semiconductor substrate 1, the front metal layer 9 is subjected to photolithography etching to form a source electrode and a gate electrode, the source electrode is in contact with the source region 6 through the second contact hole 8b, and the gate electrode is in contact with the polysilicon gate 4 through the third contact hole 8 c. The step of forming the interlayer film 7 and the contact hole in the ninth step of the embodiment of the present invention is the same as the seventh step.
In the embodiment of the present invention, the second contact hole 8b passes through the source region 6 and contacts the well region 5. After the opening of the second contact hole 8b is formed and before the metal is filled, a step of performing second conductive type heavy doping injection at the bottom of the second contact hole 8b to form a well region contact region 10 is further included.
Step ten, as shown in fig. 4, thinning the back surface of the semiconductor substrate 1 and forming a drain region with a first conductivity type heavily doped, and forming a back metal layer 11 as a drain on the back surface of the drain region.
In the method of the embodiment of the invention, the shielding grid groove power MOSTET device is an N-type device, the first conduction type is an N-type device, the second conduction type is a P-type device, and the semiconductor substrate 1 is doped with the N-type device. In other embodiments the method can also be: the shielding grid groove power MOSTET device is a P-type device, the first conduction type is a P type, the second conduction type is an N type, and the semiconductor substrate 1 is doped in a P type mode.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A shielded gate trench power MOSTET device, wherein a gate structure of a device cell region comprises:
the semiconductor device comprises a plurality of first deep grooves formed in a semiconductor substrate, wherein bottom dielectric layers are formed on the bottom surfaces and the side surfaces of the first deep grooves;
the bottom dielectric layer does not completely fill the first deep trench and a gap region is formed in the central region of the first deep trench; filling source polysilicon in the gap region;
removing the bottom dielectric layer on the side surface of the top area of the first deep groove and forming top grooves on two sides of the source polycrystalline silicon in the top area of the first deep groove;
the gate dielectric layer is formed on the side surface of the top groove, which is positioned on one side of the semiconductor substrate, and the inter-polycrystalline silicon dielectric layer is formed on the side surface of the top groove, which is positioned on one side of the source polycrystalline silicon;
filling a polysilicon gate in the top groove with the side surfaces formed with the gate dielectric layer and the inter-polysilicon dielectric layer;
at least one second deep groove communicated with all the first deep grooves, wherein the process conditions of the second deep groove and the first deep grooves are the same, the bottom dielectric layer and the source polysilicon which are the same as those in the first deep grooves are formed in the second deep groove, the source polysilicon in the second deep groove is connected with the source polysilicon in the first deep groove, two sides of the source polysilicon in the second deep groove are protected by the bottom dielectric layer, and the bottom dielectric layer is reserved instead of forming a polysilicon gate on two sides of the top of the second deep groove; and a first contact hole is formed at the top of the second deep trench, the width of the first contact hole is greater than or equal to the width of the second deep trench, and the bottom of the first contact hole is in contact with the source polysilicon of the second deep trench to lead out the source polysilicon of each first deep trench.
2. The shielded gate trench power mosfet device of claim 1 further characterized by: the semiconductor substrate is doped with a first conductive type, a well region of a second conductive type is formed on the surface of the semiconductor substrate, the polysilicon gate penetrates through the well region, and the surface of the well region covered by the side surface of the polysilicon gate is used for forming a channel;
a source region with heavily doped first conductivity type is formed on the surface of the well region;
an interlayer film, the first contact hole, the second contact hole, the third contact hole and a front metal layer are further formed on the front surface of the semiconductor substrate, a source electrode and a grid electrode are formed by photoetching the front metal layer, the source electrode is in contact with the source region through the second contact hole, and the grid electrode is in contact with the polysilicon gate through the third contact hole;
the drain region is composed of a first conductive type heavily doped region formed on the back of the thinned semiconductor substrate, and a back metal layer is formed on the back of the drain region to serve as a drain electrode.
3. The shielded gate trench power mosfet device of claim 2 wherein: the second contact hole contacts the well region through the source region.
4. The shielded gate trench power mosfet device of claim 3 wherein: and a well region contact region with heavily doped second conductivity type is formed at the bottom of the second contact hole.
5. The shielded gate trench power mosfet device of claim 1 further characterized by: the bottom dielectric layer is an oxide layer, and the gate dielectric layer is an oxide layer.
6. The shielded gate trench power mosfet device of claim 2 wherein: the shielding grid groove power MOSTET device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, and the semiconductor substrate is doped with the N type; or, the shielding grid groove power MOSTET device is a P-type device, the first conduction type is a P type, the second conduction type is an N type, and the semiconductor substrate is doped in a P type.
7. The shielded gate trench power MOSTET device of any of claims 1 to 6, wherein: the semiconductor substrate is a silicon substrate.
8. A manufacturing method of a shielded gate trench power MOSTET device is characterized in that a gate structure of a device unit area is formed by the following steps:
providing a semiconductor substrate, and forming a plurality of first deep grooves and at least one second deep groove in the semiconductor substrate by adopting a photoetching process;
secondly, forming a bottom dielectric layer on the bottom surface and the side surface of the first deep groove; the bottom dielectric layer does not completely fill the first deep trench and a gap region is formed in the central region of the first deep trench; simultaneously forming the bottom dielectric layer in the second deep trench and simultaneously forming the gap region in the second deep trench;
step three, depositing polycrystalline silicon, forming source polycrystalline silicon in the first deep groove and the second deep groove at the same time, and completely filling the corresponding gap regions; the source polysilicon in the second deep trench is connected with the source polysilicon in the first deep trench;
etching the bottom dielectric layer in the top area of the first deep groove to form top grooves on two sides of the source electrode polycrystalline silicon in the top area of the first deep groove; the bottom dielectric layer of the second deep trench is protected from being etched;
fifthly, forming a gate dielectric layer on the side surface of the top groove in the first deep groove, which is positioned on one side of the semiconductor substrate, and forming an inter-polysilicon dielectric layer on the side surface of the top groove, which is positioned on one side of the source electrode polysilicon;
depositing polycrystalline silicon, filling the polycrystalline silicon in the top groove and forming a polycrystalline silicon gate;
seventhly, forming an interlayer film, and performing photoetching to form first contact holes penetrating through the interlayer film at the tops of the second deep trenches, wherein the width of each first contact hole is larger than or equal to that of the second deep trench, the bottoms of the first contact holes are contacted with the source polycrystalline silicon of the second deep trenches, and the source polycrystalline silicon of each first deep trench is led out.
9. The method of manufacturing a shielded gate trench power mosfet device as claimed in claim 8, wherein: the semiconductor substrate is doped with a first conductive type, and after the gate structure is formed, the method further comprises the following steps:
step eight, performing ion implantation to form a well region of a second conductivity type in the semiconductor substrate; performing source injection of first conductive type heavy doping to form a source region on the surface of the well region; carrying out thermal annealing propulsion process on the well region and the source region; the surface of the well region covered by the side face of the polysilicon gate is used for forming a channel;
step nine, forming an interlayer film, the first contact hole, the second contact hole, the third contact hole and a front metal layer on the front surface of the semiconductor substrate, carrying out photoetching on the front metal layer to form a source electrode and a grid electrode, wherein the source electrode is contacted with the source region through the second contact hole, and the grid electrode is contacted with the polysilicon gate through the third contact hole;
and step ten, thinning the back surface of the semiconductor substrate, forming a drain region with the first conduction type heavily doped, and forming a back metal layer on the back surface of the drain region to serve as a drain electrode.
10. The method of manufacturing a shielded gate trench power mosfet device as claimed in claim 9, wherein: the second contact hole contacts the well region through the source region.
11. The method of manufacturing a shielded gate trench power mosfet device as claimed in claim 9, wherein: and step nine, after the opening of the second contact hole is formed and before the metal is filled, a step of performing second conductive type heavy doping injection on the bottom of the second contact hole to form a well region contact region is further included.
12. The method of manufacturing a shielded gate trench power mosfet device as claimed in claim 9, wherein: the bottom dielectric layer is an oxide layer, and the gate dielectric layer is an oxide layer.
13. The method of manufacturing a shielded gate trench power mosfet device as claimed in claim 9, wherein: the shielding grid groove power MOSTET device is an N-type device, the first conduction type is an N type, the second conduction type is a P type, and the semiconductor substrate is doped with the N type; or, the shielding grid groove power MOSTET device is a P-type device, the first conduction type is a P type, the second conduction type is an N type, and the semiconductor substrate is doped in a P type.
14. The method of manufacturing a shielded gate trench power mosfet device as claimed in claim 9, wherein: a first conductive type epitaxial layer is formed on the surface of the semiconductor substrate, and the first deep groove and the second deep groove are both formed in the first conductive type epitaxial layer.
15. A method of fabricating a shielded gate trench power mosfet device as claimed in any of claims 8 to 14 wherein: the semiconductor substrate is a silicon substrate.
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