JP2010010263A - Vertical semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical semiconductor device which prevents generation of destruction of the device, even if an excess surge is impressed on the drain, without causing increase of the on-resistance. <P>SOLUTION: The device is provided with a transistor region 31 functioning as a MOS transistor, and a dummy region 32. The dummy region 32 is provided with an N-type epitaxial layer 2, which continuously extends, from the transistor region 31 and a body layer 4 which is continuously extended from the transistor region 31 on a surface part of the N-type epitaxial layer 2. Dummy trenches 15b are formed in the dummy region 32, in a state where they reach the N-type epitaxial layer 2 penetrating through the body layer 4 and at intervals larger than those of trenches 15a in the transistor region 31. Electrically floating dummy gate electrodes 6b are embedded in the dummy trenches 15b through dummy gate insulating films 5b. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a vertical semiconductor device having a vertical gate electrode.

  In recent years, with the reduction in power consumption, high functionality, and high speed in electronic devices, the accompanying semiconductor devices are also required to have low power consumption and high speed. MOS transistors incorporated in semiconductor integrated circuit devices generally used for DC-DC converters in electronic equipment are also required to reduce on-resistance during operation in order to meet these requirements. Yes.

  One technique for reducing the on-resistance of a MOS transistor is to increase the number of gate electrodes of one transistor arranged per unit area and increase the number of channels connecting the gate electrodes in parallel. As a semiconductor device to which the technique is applied, for example, there is a vertical gate semiconductor device in which the gate electrode of the semiconductor device is arranged in the vertical direction, that is, in the direction perpendicular to the surface of the semiconductor substrate. In this vertical gate semiconductor device, a source region and a body region exist above the gate electrode arranged in the vertical direction, and a drain region exists at the bottom of the gate electrode so as to face the source region and the body region. Even for such a vertical gate semiconductor device, it is required to further reduce the low on-resistance. In order to realize the low on-resistance, the vertical gate semiconductor device also reduces the distance between adjacent transistors by miniaturization, increases the number of gate electrodes of the transistor per unit area, and reduces the number of channels connected in parallel. An increasing structure is adopted.

  FIG. 22 is a plan layout view showing the structure of a conventional vertical semiconductor device. FIG. 23 is a cross-sectional view taken along line XX in FIG. 22 and 23 exemplify N-channel MOS transistors. In FIG. 22, various thin films formed on the semiconductor substrate and the insulating film on the gate electrode are not shown.

  As shown in FIG. 23, the conventional vertical semiconductor device includes a plurality of trench gate electrodes 106a. Each trench gate electrode 106 a is provided so as to penetrate the P-type first body layer 104 formed on the surface portion of the N-type epitaxial layer 102 on the N-type silicon substrate 101. A gate insulating film is disposed between the P-type first body layer 104 and the trench gate electrode 106a. As shown in FIG. 22, the trench gate electrodes 106a are linear in a plan view and are arranged in parallel to each other. As shown in FIGS. 22 and 23, an N-type source layer 110 is provided on the surface of the P-type first body layer 104 adjacent to the trench gate electrode 106a. The P-type first body layer 104 is exposed between the adjacent source layers 110 between the trench gate electrodes 106a. The aluminum wiring 111 is in contact with the source layer 110 and the P-type first body layer 104 exposed on the surface. The aluminum wiring 111 and each trench gate electrode 106a are insulated by an insulating film 107.

  In the above configuration, when the interval between the trench gate electrodes 106a is reduced, the width of the P-type first body layer 104 sandwiched between the adjacent trench gate electrodes 106 is reduced. For this reason, the vertical resistance (hereinafter referred to as body resistance) of the P-type first body layer 104 increases. When the body resistance increases, when a transient surge is applied to the drain side, the N-type drain side, that is, the N-type silicon substrate 101 and the N-type epilayer is a region where the potential is locally unstable due to the avalanche phenomenon. A hole current is intensively injected from 102 to the P-type first body layer 104, and a potential difference is generated between the P-type first body layer 104 and the N-type source layer 110 in this portion. Since the N-type drain, the P-type first body layer 104, and the N-type source layer 110 constitute a parasitic bipolar transistor having an NPN structure including a collector, a base, and an emitter, respectively, the P-type first body layer 104 and When a potential difference occurs between the N-type source layer 110 and the P-type first body layer 104 (base) and the N-type source layer 110 (emitter), the parasitic bipolar transistor operates (turns on). . As a result, latch-up occurs and the device is destroyed due to thermal destruction due to current concentration.

  As a countermeasure, a semiconductor device has been proposed in which a dummy trench gate electrode is formed to make it difficult to cause device breakdown due to current concentration.

  For example, in the vertical gate semiconductor device of Patent Document 1, a dummy trench gate in which a source layer is provided on both side walls of one trench gate electrode and is connected to the source layer so as to sandwich the trench gate electrode. An electrode is formed. Further, by providing contact portions connecting the source layer and the body layer to the wiring (emitter electrode) on both sides of the trench gate electrode, the degree of concentration of the avalanche current can be reduced.

Patent Document 2 discloses a vertical semiconductor device having a dummy trench gate electrode 106b in a region (dummy region) different from a region operating as a transistor, as shown in FIGS. That is, the dummy trench gate electrode 106b electrically connected to the source layer is disposed on the outer periphery of the transistor region. In this configuration, the dummy trench gate electrode 106b having a shape variation due to the microloading effect does not function as a gate electrode of the transistor. Therefore, the operation of the transistor can be prevented from becoming unstable. Further, since the dummy trench gate electrode 106b is connected to the source layer, unstable behavior of the region where the dummy trench gate electrode is formed is suppressed.
JP 2002-16252 A Japanese Patent Laid-Open No. 9-275212

  However, even in a vertical semiconductor device including a dummy trench gate electrode, in order to further reduce the on-resistance, if the interval between adjacent trench gate electrodes is narrowed to increase the number of channels connected in parallel, the trench The width of the body layer sandwiched between the gate electrodes is also narrowed, and the resistance of the body layer existing between the trench gate electrodes inevitably increases. Therefore, when a transient surge is applied from the outside to the drain and the hole current is concentrated and injected locally, it is composed of the drain, body layer, and source layer of the transistor operating region as described above. The parasitic bipolar transistor operates, and a large current flows between the source and drain. This large current causes thermal destruction of the gate insulating film on the channel side surface of the trench gate electrode, leading to device destruction. Therefore, device destruction cannot be reliably prevented.

  Further, in the structure described in Patent Document 1, in which dummy trench gate electrodes are arranged on both sides of the trench gate electrode, a trench gate electrode that operates as a transistor is provided in a region on the semiconductor substrate where the dummy trench gate electrode is arranged. It cannot be formed. In this configuration, the number of trench gate electrodes operating as a transistor per unit area is reduced, and as a result, it can be said to be a disadvantageous structure from the viewpoint of reducing the on-resistance per unit area on the semiconductor substrate plane.

  Further, in the structure in which the dummy trench gate electrode is fixed at the potential of the source layer described in Patent Document 2, when a transient surge is applied from the trench gate electrode or the drain side, the trench connected to the source layer is used. A strong electric field is applied to the gate electrode and the dummy trench gate electrode, and the gate insulating film of the dummy trench gate electrode may be destroyed. When the gate insulating film of the dummy trench gate electrode is broken, the dummy trench gate electrode is connected to the source layer, so that the source layer and the drain layer are short-circuited.

  In view of the above problems, the present invention provides a low-on-resistance vertical semiconductor device capable of reliably preventing device breakdown even when a transient surge is applied to the drain. Objective.

  In order to solve the above problems, the present invention employs the following technical means. First, the present invention is premised on a vertical semiconductor device having a MOS transistor having a vertical gate. The vertical semiconductor device according to the present invention includes a MOS transistor region and a dummy region adjacent to the MOS transistor region. The MOS transistor region includes a drain layer made of a first conductivity type semiconductor layer, and a body layer made of a second conductivity type semiconductor layer opposite to the first conductivity type provided on the drain layer. . In the MOS transistor region, a plurality of linear trenches arranged in parallel to each other in plan view are formed in a state of reaching the drain layer through the body layer. A gate insulating film is formed on the inner wall of each trench, and a gate electrode is embedded in each trench through the gate insulating film. A source layer made of a semiconductor layer of the first conductivity type is formed adjacent to the trench on a part of the surface portion of the body layer between the gate electrodes. On the other hand, the dummy region includes a drain layer continuously extended from the MOS transistor region and a body layer formed integrally with the body layer of the MOS transistor region. Further, in the dummy region, a plurality of linear dummy trenches arranged in parallel with each other in a plan view reach the drain layer through the body layer, and have an interval larger than the trench interval of the MOS transistor region. It is formed with. A dummy gate insulating film is formed on the inner wall of each dummy trench, and a dummy gate electrode is embedded in each dummy trench via the dummy gate insulating film. The dummy gate electrode is electrically floating. Further, the body layer of the dummy region, the body layer of the MOS transistor region, and the source layer are electrically connected by electrodes.

  According to the present invention, when the trench interval in the MOS transistor region is narrowed, the impurity concentration in the body layer in the dummy region is higher than the impurity concentration in the body layer in the MOS transistor region. Therefore, the breakdown voltage of the PN junction formed in the drain layer and the body layer is smaller in the dummy region than in the MOS transistor region. As a result, when a surge is applied from the drain layer side, a current caused by the surge can be guided to the dummy region, and device breakdown can be suppressed. Further, in this configuration, the body layer of the MOS transistor region and the body layer of the dummy region are integrally formed at the same time in the same process, so that the number of manufacturing steps does not increase in order to realize this structure. In addition, since the difference in impurity concentration between the body layer of the MOS transistor region and the body layer of the dummy region becomes more conspicuous as the trench interval is reduced to reduce the on-resistance, this structure reduces the on-resistance. For the purpose, it is very suitable for a vertical semiconductor device with a reduced trench interval. Although the number of manufacturing steps increases, the impurity concentration of the body layer in the dummy region may be further increased by ion implantation or the like.

  In the above configuration, the dummy region may include a connection dummy trench that penetrates the body layer and communicates the dummy trench with each other, and the body layer may be surrounded by the dummy trench and the connection dummy trench. A dummy gate insulating film and a dummy gate electrode are also formed in the connection dummy trench. In this configuration, the first conductivity type dummy source layer is formed on the entire surface of the body layer surface portion surrounded by the dummy trench and the connection dummy trench, and the dummy source layer is electrically connected to the electrode.

  According to this configuration, the dummy gate electrode and the body layer surrounded by the dummy gate electrode are electrically floating. Further, the impurity concentration of the body layer in the dummy region is higher than the impurity concentration in the body layer of the MOS transistor region. Therefore, when a surge is applied from the drain layer side, hole current is intensively injected from the drain layer to the body layer in the dummy region. Therefore, the parasitic bipolar transistor in the dummy region operates before the parasitic bipolar transistor in the MOS transistor region operates. As a result, when a surge is applied from the drain layer side, a current caused by the surge can be guided to the dummy region, and device breakdown can be suppressed. Further, in this configuration, the dummy source layer can be formed simultaneously with the source layer of the MOS transistor region in the same process, so that the number of manufacturing steps does not increase in order to realize this structure.

  In the semiconductor device described above, the dummy region may further include a first conductivity type semiconductor layer that includes a dummy trench that contacts the body layer and reaches the drain layer in the drain layer. In this case, the impurity concentration of the semiconductor layer is set higher than the impurity concentration of the drain layer.

  In this configuration, the PN junction composed of the high-concentration semiconductor layer and the body layer is lower than the breakdown voltage of the PN junction composed of the drain layer and the body layer in each configuration described above. Therefore, according to the present configuration, a surge current can be guided from a lower surge voltage to the dummy region, and device breakdown can be more reliably suppressed. Note that this structure only adds a process for forming a high-concentration impurity layer, and the manufacturing process is not significantly complicated.

  According to the present invention, even when the device is miniaturized to reduce the on-resistance, it is possible to reliably prevent the occurrence of device breakdown when a transient surge is applied to the drain. In addition, since the manufacturing process is not significantly complicated, a low on-resistance vertical semiconductor device can be realized at low cost.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the present invention is embodied as a vertical semiconductor device including an N-channel MOS transistor. In this case, the first conductivity type referred to in the present invention is N-type, and the second conductivity type is P-type. Note that the following description can be similarly applied to a semiconductor device including a P-channel MOS transistor by reversing the conductivity type of each impurity region.

(First embodiment)
FIG. 1 is a plan layout view showing the arrangement of gate electrodes of a vertical semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device of this embodiment includes a plurality of gate electrodes 6a arranged in parallel to each other. A plurality of dummy gate electrodes 6b arranged in parallel with each other and in parallel with the gate electrode 6a are provided outside the region where the plurality of gate electrodes 6a are formed. Each gate electrode 6a is electrically connected to a peripheral wiring portion 26 surrounding a region where the plurality of gate electrodes 6a and the plurality of dummy gate electrodes 6b are arranged. Further, each dummy gate electrode 6b and the peripheral wiring portion 26 are electrically separated.

  As will be described later, a source layer is formed on the front surface portion of the semiconductor substrate between the gate electrodes 6a, and a drain layer is formed on the back surface side of the semiconductor substrate. That is, a vertical MOS transistor is constituted by the source layer, the drain layer, and the gate electrode 6a. Here, a region including the gate electrode 6a and operating as a MOS transistor is a MOS transistor region 31 (hereinafter referred to as a transistor region 31), and a region including the dummy gate electrode 6b is a dummy region 32. In FIG. 1, a protective diode 25 is installed at the lower left. The protection diode 25 is connected in parallel with the gate electrode 6a and has a role of a protection circuit against a surge input to the gate electrode 6a.

  FIG. 2 is an enlarged plan view showing the main part of the vertical semiconductor device shown in FIG. 3 is a cross-sectional view taken along line AA in FIG. In FIG. 2, various thin films formed on the semiconductor substrate and the insulating film on the gate electrode are not shown.

  As shown in FIG. 3, the transistor region 31 and the dummy region 32 are provided on a surface portion of an N-type epitaxial layer 2 (hereinafter referred to as an N-type epi layer 2) provided on the N-type silicon substrate 1. . The N-type epi layer 2 and the N-type silicon substrate 1 function as the drain layer described above.

  Each gate electrode 6 a in the transistor region 31 is provided in a state of penetrating the P-type first body layer 4 formed on the surface portion of the N-type epi layer 2. Each gate electrode 6a has a gate insulating film 5a such as a silicon oxide film formed on the inner wall of the trench 15a in a trench (groove) 15a that penetrates the P-type first body layer 4 and reaches the N-type epi layer 2. It is made of a conductor such as polysilicon embedded via the. An N-type source layer 10 is provided on the surface portion of the P-type first body layer 4 adjacent to each gate electrode 6a. As shown in FIG. 2, the N-type source layer 10 is provided with a plurality of strips spaced apart from each other in a direction perpendicular to each gate electrode 6 a in a plan view. Further, as shown in FIG. 2, between the source layers 10, the P-type second body layer 9 is formed on the surface portion of the P-type first body layer 4 in a direction perpendicular to the gate electrodes 6a in plan view. Is provided. As shown in FIG. 3, the bottom of the P-type second body layer 9 is disposed shallower than the bottom of the P-type first body layer 4.

  The N-type source layer 10 and the P-type second body layer 9 exposed on the surface of the transistor region 31 are electrically connected to an aluminum (aluminum) wiring 11 a formed on the upper surface of the N-type epi layer 2. Also, the aluminum wiring 11a and the gate electrode 6a are electrically separated by the second interlayer insulating film 7 disposed on each gate electrode 6a.

For example, the P-type first body layer 4 has an impurity concentration of about 1E17 cm ⁻³ and is formed for the purpose of controlling the threshold value of the channel region formed along the side wall of the trench 15a. The P-type second body layer 9 has an impurity concentration of 1E19 cm ⁻³ or more and is formed for the purpose of forming an ohmic contact with the aluminum wiring 11a. In this configuration, the N-type source layer 10, the P-type first body layer 4, and the P-type second body layer 9 are commonly connected, and the same potential is applied through the aluminum wiring 11a.

  On the other hand, each dummy gate electrode 6 b in the dummy region 32 is provided so as to penetrate the P-type first body layer 4 continuously extended from the transistor region 31. As will be described later, the P-type first body layer 4 of the transistor region 31 and the dummy region 32 is formed integrally at the same time in the same process. Each dummy gate electrode 6b is formed on the inner wall of the dummy trench 15b in the dummy trench (dummy groove) 15b penetrating the P-type first body layer 4 and reaching the N-type epi layer 2 similarly to the gate electrode 6a. It is made of a conductor such as polysilicon buried through a dummy gate insulating film 5b such as a silicon oxide film. In the present embodiment, the interval between the dummy gate electrodes 6b is larger than the interval between the gate electrodes 6a. As shown in FIGS. 2 and 3, the P-type second body layer 9 which is the same as between the source layers 10 of the transistor region 31 is formed on the surface of the P-type first body layer 4 adjacent to the gate electrode 6b. Is provided. As described above, the bottom of the P-type second body layer 9 is disposed shallower than the bottom of the P-type first body layer 4. The aluminum wiring 11a is also formed on the dummy region 32, and the P-type second body layer 9 in the dummy region 32 and the aluminum wiring 11a constitute an ohmic contact.

  On the N-type epi layer 2 outside the dummy region 32, a polysilicon wiring 6f is formed via a first interlayer insulating film 3 having a step. The polysilicon wiring 6f is formed in the same process as the gate electrode 6a and the dummy gate electrode 6b as will be described later. The polysilicon wiring 6f is integrally formed in a state of being connected to each gate electrode 6a. An aluminum wiring 11b is formed on the polysilicon wiring 6f via a second interlayer insulating film 7 and a third interlayer insulating film 8, and the polysilicon wiring 6f and the aluminum wiring 11b are connected to the second interlayer insulating film 7 and They are electrically connected through contact holes that penetrate the third interlayer insulating film 8. That is, the laminated wiring of the polysilicon wiring 6f and the aluminum wiring 11b constitutes the peripheral wiring portion 26 that applies a voltage to the gate electrode 6a.

  In the vertical semiconductor device of this embodiment, as described above, the dummy gate electrode 6b is formed in a region including both the P-type first body layer 4 and the P-type second body layer 9, and the dummy region Similarly to the transistor region 31, the 32 P-type second body layers 9 form an ohmic contact with the aluminum wiring 11a. The dummy gate electrode 6b is not connected to any wiring and is electrically floating. Therefore, in the dummy region 32, it can be considered that the N-type epi layer 2 and the P-type first body layer 4 form an N / P diode.

  4 to 9 are process cross-sectional views showing a process of forming a semiconductor device having the above structure. Hereinafter, when a thin film is formed on the outermost surface, it is expressed that a film is appropriately formed on a semiconductor substrate.

  As shown in FIG. 4, first, an N-type epi layer 2 is formed on an N-type silicon substrate 1 by a known epitaxial growth method. Next, a first interlayer insulating film 3 made of a silicon oxide film having a thickness of 50 to 500 nm is formed on the surface of the N-type epi layer 2 by thermal oxidation. On the first interlayer insulating film 3, an opening is formed in a region including a region (the transistor region 31 and the dummy region 32) where the gate electrode 6 a and the dummy gate electrode 6 b are formed in a subsequent process by a known lithography technique. A resist pattern (not shown) is formed. A P-type first body layer 4 is formed by introducing P-type impurities into the surface portion of the N-type epi layer 2 by ion implantation using the resist pattern as a mask.

  Subsequently, on the first interlayer insulating film 3 from which the resist pattern used for forming the first body layer 4 has been removed, a resist pattern having an opening in a region where the trench 15a and the dummy trench 15b are formed in the subsequent steps ( (Not shown) is formed. By etching using the resist pattern as a mask, as shown in FIG. 5, the first interlayer insulating film 3 in the trench 15a and dummy trench 15b formation region is removed, and then the resist pattern is also removed. Next, a trench having a depth of 0.8 to 3.0 μm reaching the N-type epi layer 2 through the P-type first body layer 4 by dry etching using the patterned first interlayer insulating film 3 as a mask. 15a and dummy trench 15b are formed.

  As shown in FIG. 6, a gate oxide film 5a and a dummy gate oxide film 5b having a thickness of about 8 to 100 nm are formed on the inner surfaces of the formed trench 15a and dummy trench 15b by thermal oxidation or the like. . Thereafter, a 200 to 800 nm polysilicon film to be a gate electrode material is deposited on the entire surface. Conductivity is imparted to the polysilicon film by performing ion implantation of N-type impurities and annealing. Thereafter, a resist pattern (not shown) is formed on the polysilicon film so as to cover a region to be the polysilicon wiring 6f and a connection portion between each gate electrode 6a and the polysilicon wiring 6f, and the resist pattern is used as a mask. Etching is performed. Thereby, the polysilicon wiring 6f, the gate wiring 6f embedded in the trench 15a and the dummy trench 15b without being connected to the polysilicon wiring 6f are connected to the polysilicon wiring 6f on the first interlayer insulating film 3. And a dummy gate electrode 6b embedded in. At this time, the polysilicon film embedded in the trench 15a and the dummy trench 15b is formed in a state where the uppermost surface recedes about 100 to 800 nm below the surface of the P-type first body layer 4 (surface of the N-type epilayer 2). The In the present embodiment, as shown in FIG. 1, each gate electrode 6a is formed as an integral pattern continuously connected to the polysilicon wiring 6f at the end thereof, and each dummy gate electrode 6b is isolated from each other. Pattern.

  On the semiconductor substrate on which the gate electrode 6a and the dummy gate electrode 6b are formed, as shown in FIG. 7, a second interlayer insulating film 7 and a third interlayer insulating film 8 made of a silicon oxide film or the like are sequentially deposited from the lower layer. The The total film thickness of the second interlayer insulating film 7 and the third interlayer insulating film 8 is about 200 to 1000 nm.

  Next, as shown in FIG. 8, contact holes are formed in the second interlayer insulating film 7 and the third interlayer insulating film 8 for electrical connection with aluminum wirings 11a and 11b formed in the subsequent steps. The Here, a resist pattern (not shown) having an opening in the contact hole formation region is formed on the third interlayer insulating film 8, and the contact hole is formed by dry etching using the resist pattern as a mask. In the present embodiment, a contact hole in which the whole region of the transistor region 31 and the dummy region 32 is exposed at the bottom and a contact hole along the polysilicon wiring 6f in which the polysilicon wiring 6f is exposed at the bottom are formed. In the transistor region 31 and the dummy region 32, the third interlayer insulating film 8 and the first interlayer insulating film 3 are completely etched away by the etching, and the upper surface of the second interlayer insulating film 7 in the trench 15a and the dummy trench 15b. Is etched to be substantially flush with the surface of the first body layer 4. As a result, the trench 15a in which the gate electrode 6a and the dummy gate electrode 6b are formed and the upper part of the dummy trench 15b are filled with the material of the second interlayer insulating film 7, and at the same time, the first body of the transistor region 31 is formed. The surface of layer 4 and the surface of first body layer 4 in dummy region 32 are exposed on the surface of the semiconductor substrate.

  After the resist pattern used for etching the contact hole is removed, a resist pattern (not shown) having an opening in a region where the P-type second body layer 9 is formed in a subsequent process is formed on the semiconductor substrate. The Here, resist patterns having openings in the P-type second body layer 9 formation region of the transistor region 31 and the P-type second body layer 9 formation region of the dummy region 32 shown in FIG. 2 are formed. Then, P-type second body layer 9 is formed by ion-implanting P-type impurities into P-type first body layer 4 using the resist pattern as a mask. After the resist pattern is removed, a resist pattern (not shown) having an opening in the N-type source layer 10 formation region of the transistor region 31 shown in FIG. 2 is formed on the semiconductor substrate. An N-type source layer 10 is formed by ion-implanting N-type impurities into the P-type first body layer 4 using the resist pattern as a mask. Note that the resist pattern used when forming the P-type second body layer 9 and the resist pattern used when forming the N-type source layer 10 are covered on the transistor region 31 and the dummy region 32. And the opening are reversed.

  When the formation of the P-type second body layer 9 and the N-type source layer 10 is completed, as shown in FIG. 9, the second interlayer insulating film 7 filled on the gate electrode 6a and the dummy gate electrode 6b by the whole surface dry etching. Is etched back about 100 to 300 nm. As a result, the N-type source layer 10 and the P-type second body layer 9 which are the sidewalls of the trench 15a and the dummy trench 15b are exposed, and the upper portions of the trench 15a and the dummy trench 15b become concave. At the same time, the corner portions at the upper end of the trench 15a and the upper end of the dummy trench 15b are etched, and a curved surface is formed at the corner portion. In this dry etching, the etching amount is controlled so that the upper surfaces of the gate electrode 6a and the dummy gate electrode 6b are not exposed. Thereafter, aluminum wirings 11a and 11b are formed by applying a lithography technique and an etching technique to the aluminum film deposited on the semiconductor substrate. The drain electrode electrically connected to the drain layer (N-type silicon substrate 1 and N-type epi layer 2) is formed on the back side of the N-type silicon substrate 1, for example.

  The vertical semiconductor device formed as described above includes a dummy region 32 including a dummy gate electrode 6b that is electrically floating in the periphery of the transistor region 31. The dummy region 32 has a region regarded as an N / P diode composed of the N-type epi layer 2 and the P-type first body layer 4, and the P-type second layer on the P-type first body layer 4. The body layer 9 is connected to the aluminum wiring 11a.

  In the vertical semiconductor device of this embodiment, the interval between the dummy gate electrodes 6b is wider than the interval between the gate electrodes 6a in the transistor region 31. As shown in FIG. 6, when a gate insulating film is formed on a trench sidewall made of silicon containing P-type impurities, for example, boron, by thermal oxidation, the impurities are gate-insulated by the segregation effect of impurities in the course of thermal oxidation. It is sucked out to the (dummy gate insulating film 5b) side. That is, the impurity concentration of the P-type first body layer 4 existing between the gate electrodes 6a (between the dummy gate electrodes 6b) decreases. The degree of decrease in the impurity concentration depends on the absolute amount of impurities in the semiconductor layer where segregation occurs. That is, the smaller the absolute amount of impurities, the greater the proportion of impurities that move due to segregation in the absolute amount, and as a result of segregation, the impurity concentration is greatly reduced. Therefore, in the configuration of the present embodiment, since the interval between the dummy gate electrodes 6b is larger than the interval between the gate electrodes 6a, the impurity concentration of the P-type first body layer 4 between the dummy gate electrodes 6b is between the gate electrodes 6a. The impurity concentration of the P-type first body layer 4 is slightly higher. As a result, the breakdown voltage of the PN junction formed by the N-type epi layer 2 and the P-type first body layer 4 is lower in the dummy region 32 than in the transistor region 31.

  When a surge is applied to the semiconductor device having such a structure from the drain layer (N-type silicon substrate 1, N-type epi layer 2) side, the junction between the N-type epi layer 2 and the P-type first body layer 4. Since the withstand voltage is lower in the dummy region 32 than in the transistor region 31, the avalanche breakdown first occurs in the dummy region 32. Therefore, before the NPN parasitic bipolar transistor composed of the N-type epi layer 2, the P-type first body layer 4 and the N-type source layer 10 in the transistor region 31 operates and a large current flows, the N-type in the dummy region 32. A surge current can be guided to the N / P diode composed of the epi layer 2, the P-type first body layer 4 and the P-type second body layer 9. The surge current guided to the N / P diode composed of the N-type epi layer 2 in the dummy region 32, the P-type first body layer 4, and the P-type second body layer 9 is P in the dummy region 32. It flows into the aluminum wiring 11 b through the mold second body layer 9. As a result, destruction of the gate oxide film 5a in the transistor region 31 can be prevented.

  In this embodiment, since the interval between the dummy gate electrodes 6b is increased, the area occupied by the semiconductor device increases. However, the number of dummy gate electrodes 6b is much smaller than that of the gate electrode 6a of the transistor region 31 that occupies most of the chip area. Therefore, the chip area is not significantly increased by increasing the interval between the dummy trenches 15b.

  Further, in this configuration, the body layer of the MOS transistor region and the body layer of the dummy region are integrally formed at the same time in the same process, so that the number of manufacturing processes is increased as compared with the conventional process in order to realize this structure. There is nothing. In addition, since the difference in impurity concentration between the body layer of the MOS transistor region and the body layer of the dummy region becomes more conspicuous as the trench interval is reduced to reduce the on-resistance, this structure reduces the on-resistance. For the purpose, it is suitable for a vertical semiconductor device having a reduced trench interval. Although the number of manufacturing steps increases, the impurity concentration of the body layer in the dummy region may be further increased by ion implantation or the like.

(Second Embodiment)
FIG. 10 is an enlarged plan view showing the main part of the vertical semiconductor device according to the second embodiment of the present invention. Moreover, FIG. 11 is sectional drawing which follows the AA line in FIG. In FIG. 10, the various thin films formed on the semiconductor substrate and the insulating film on the gate electrode are not shown. In FIGS. 10 and 11, the same reference numerals are assigned to the portions having the same functions and effects as those of the semiconductor device of the first embodiment.

  As shown in FIGS. 10 and 11, the vertical semiconductor device according to the present embodiment basically has the same structure as the semiconductor device according to the first embodiment. In the N-type epi layer 2 (drain layer), an impurity that is in contact with the P-type first body layer 4 and includes the dummy trench 15b reaching the N-type epi layer 2 is higher than the N-type epi layer 2 It differs from the vertical semiconductor device of the first embodiment in that it further includes an N-type semiconductor layer 12 having a concentration (hereinafter referred to as an N-type high concentration layer 12).

  12 to 14 are process cross-sectional views illustrating a process of forming a semiconductor device having the above structure. In the manufacturing process of the vertical semiconductor device of this embodiment, as shown in FIG. 12, first, the N-type epitaxial layer is formed on the N-type silicon substrate 1 through the steps described with reference to FIG. 4 in the first embodiment. 2 is formed, and a first interlayer insulating film 3 made of a silicon oxide film having a thickness of 50 to 500 nm is formed on the surface of the N-type epi layer 2. Next, a resist pattern (not shown) having an opening in a region including a region (transistor region 31 and dummy region 32) where the gate electrode 6a and the dummy gate electrode 6b are formed in the subsequent steps on the first interlayer insulating film 3. Is formed. P-type first body layer 4 is formed on the surface portion of N-type epi layer 2 by ion implantation using the resist pattern as a mask.

  Subsequently, as shown in FIG. 13, the region where the N-type high concentration layer 12 is formed in the subsequent steps on the first interlayer insulating film 3 from which the resist pattern used for forming the first body layer 4 has been removed. A resist pattern 20 having an opening is formed. By ion implantation using the resist pattern 20 as a mask, an N-type epi layer is formed below the junction boundary surface where the P-type first body layer 4 and the N-type epi layer 2 are in contact (on the N-type epi layer 2 side of the junction boundary surface). An N-type high concentration layer 12 having a concentration higher than 2 is formed.

  Subsequently, on the first interlayer insulating film 3 from which the resist pattern 20 has been removed, a resist pattern (not shown) having an opening in a region where the trench 15a and the dummy trench 15b are to be formed in a subsequent process is formed. By etching using the resist pattern as a mask, as shown in FIG. 14, the first interlayer insulating film 3 in the trench 15a and dummy trench 15b formation region is removed, and then the resist pattern is also removed. Next, by dry etching using the patterned first interlayer insulating film 3 as a mask, a depth of 0.8 to 3.0 μm reaching the N-type high concentration layer 12 through the P-type first body layer 4 is achieved. A trench 15a and a dummy trench 15b are formed. In the dry etching, the etching amount is controlled so that the trench 15 a and the dummy trench 15 b do not penetrate the N-type high concentration layer 12.

  The subsequent steps are the same as those described with reference to FIGS. 6 to 9 in the first embodiment, and a description thereof will be omitted here.

  In the vertical semiconductor device formed as described above, the dummy region 32 has a region regarded as an N / P diode composed of the N-type high concentration layer 12 and the P-type first body layer 4. Yes. As described above, since the N-type high concentration layer 12 has a higher impurity concentration than the N-type epi layer 2, a PN junction composed of the N-type high concentration layer 12 and the P-type first body layer 4. Is lower than the breakdown voltage of the PN junction composed of the N-type epi layer 2 and the P-type first body layer 4 in the semiconductor device of the first embodiment.

  When a surge is applied to the semiconductor device having such a structure from the drain layer (N-type silicon substrate 1, N-type epi layer 2) side, first, avalanche breakdown occurs in the dummy region 32 as in the first embodiment. Occurs. In the configuration of the present embodiment, since the breakdown voltage of the PN junction of the dummy region 32 is lower than that of the configuration of the first embodiment, the N-type high concentration layer 12 and the P-type are generated from a lower surge voltage. A surge current can be guided to the N / P diode composed of the first body layer 4 and the P-type second body layer 9. Therefore, it is possible to prevent the gate insulating film 5a from being destroyed more efficiently than the semiconductor device according to the first embodiment. Note that this structure only adds a process for forming a high-concentration impurity layer, and the manufacturing process is not significantly complicated.

(Third embodiment)
FIG. 15 is a plan layout view showing the arrangement of the gate electrodes of the vertical semiconductor device according to the third embodiment of the present invention. FIG. 16 is an enlarged plan view showing the main part of the vertical semiconductor device shown in FIG. 15, and FIG. 17 is a cross-sectional view taken along line AA in FIG. In FIG. 16, various thin films formed on the semiconductor substrate and the insulating film on the gate electrode are not shown. In FIGS. 15 to 17, the same reference numerals are given to the portions having the same functions and effects as those of the semiconductor device of the first embodiment.

  As shown in FIGS. 15 to 17, the semiconductor device according to the present embodiment basically has the same structure as the semiconductor device according to the first embodiment. The dummy trench 15b in which the dummy gate electrode 6b is formed is connected to each other by the connecting dummy trench 15c penetrating the P-type first body layer 4, and the P-type first surrounded by the dummy trench 15b and the connecting dummy trench 15c. The difference from the vertical semiconductor device of the first embodiment is that an N-type dummy source layer 13 is further provided on the surface of the body layer 4. In the connection dummy trench 15c, a connection dummy gate electrode 6c is formed via a connection dummy gate oxide film 5c. Further, the dummy gate oxide film 5b and the connection dummy gate oxide film 5c are integrally formed, and the dummy gate electrode 5b and the connection dummy gate electrode 6c are formed integrally. Similar to the first embodiment, the dummy gate electrodes 6b connected to each other by the connection dummy gate electrodes 6c are not connected to any wiring and are electrically floating. Further, in plan view, the P-type second body layer 9 is formed outside the region surrounded by the dummy trench 15b and the connection dummy trench 15c, as in the first embodiment.

  In the vertical semiconductor device of this embodiment, as can be understood from FIGS. 15 to 17, the P-type first body layer 4 is surrounded by the dummy gate electrode 6 b and the connection dummy gate electrode 6 c through the gate insulating films 5 b and 5 c. In addition, a PN junction with the N-type epi layer exists below the P-type first body layer 4 and a PN junction with the N-type dummy source layer 13 exists above. Therefore, in addition to the dummy gate electrode 6b being electrically floating, the P-type first body layer 4 surrounded by the dummy gate electrode 6b and the connecting dummy gate electrode 6c is also in an electrically floating state.

  18 and 19 are process cross-sectional views illustrating a process of forming a semiconductor device having the above structure. In the manufacturing process of the vertical semiconductor device of the present embodiment, as shown in FIG. 18, first, it is formed on the N-type silicon substrate 1 through the steps described with reference to FIGS. 4 to 7 in the first embodiment. A P-type first body layer 4 is formed on the surface portion of the N-type epi layer 2, and a trench 15a and a dummy trench 15b penetrating the P-type first body layer 4 are formed. In the present embodiment, the resist pattern used in the step of forming the trench 15a and the dummy trench 15b further has an opening corresponding to the formation region of the connection dummy trench 15c, and the first interlayer to which the resist pattern is transferred. A connecting dummy trench 15c is also formed simultaneously by etching using the insulating film 3 as a mask. The trench 15a, the dummy trench 15b, and the connection dummy trench 15c are respectively connected to the gate electrode 6a via the oxide films (gate oxide film 5a, dummy gate oxide film 5b, connection dummy gate oxide film 5c) formed on the inner wall. A dummy gate electrode 6b and a connection dummy gate electrode 6c are formed. Then, deposition and etching of the second interlayer insulating film 7 and the third interlayer insulating film 8 are performed, and the contact hole where the entire region of the transistor region 31 and the dummy region 32 are exposed at the bottom, as in the first embodiment, A contact hole is formed along the polysilicon wiring 6f where the polysilicon wiring 6f is exposed at the bottom. At this time, in the transistor region 31 and the dummy region 32, the third interlayer insulating film 8 and the first interlayer insulating film 3 are completely etched away, and the second interlayer insulating film 7 in the trench 15a, the dummy trench 15b, and the connection dummy trench 15c. The second interlayer insulating film 7 is etched so that the upper surface of the first body layer 4 is substantially flush with the surface of the first body layer 4. Thereby, the trench 15a in which the gate electrode 6a, the dummy gate electrode 6b and the connection dummy gate electrode 6c are formed, and the upper part of the dummy trench 15b and the connection dummy trench 15c are filled with the material of the second interlayer insulating film 7 At the same time, the surface of the first body layer 4 in the transistor region 31 and the surface of the first body layer 4 in the dummy region 32 are exposed on the surface of the semiconductor substrate.

  After the resist pattern used for etching the contact hole is removed, as shown in FIG. 19, a resist pattern having an opening in a region where the P-type second body layer 9 is formed in a subsequent process on the semiconductor substrate. (Not shown) is formed. Here, resist patterns having openings in the P-type second body layer 9 formation region of the transistor region 31 and the P-type second body layer 9 formation region of the dummy region 32 shown in FIG. 16 are formed. Then, P-type second body layer 9 is formed by ion-implanting P-type impurities into P-type first body layer 4 using the resist pattern as a mask. After the resist pattern is removed, a resist pattern (not shown) having openings in the N-type source layer 10 formation region and the N-type dummy source layer 13 formation region of the transistor region 31 shown in FIG. ) Is formed. The N-type source layer 10 and the N-type dummy source layer 13 are formed by ion-implanting N-type impurities into the P-type first body layer 4 using the resist pattern as a mask. The resist pattern used when forming the second body layer 9 and the resist pattern used when forming the source layer 10 and the dummy source layer 13 are covered on the transistor region 31 and the dummy region 32. The pattern is such that the portion and the opening are reversed.

  The subsequent steps are the same as those described with reference to FIG. 9 in the first embodiment, and thus the description thereof is omitted here.

  In the vertical semiconductor device formed as described above, in the transistor region 31, the potentials of the N-type source layer 10, the P-type first body layer 4, and the gate electrode 6a are fixed, whereas the dummy region In 32, the P-type first body layer 4 surrounded by the dummy gate electrode 6b and the dummy gate electrode 6b itself are in an electrically floating state. Further, the impurity concentration of the P-type first body layer 4 in the dummy region 32 is higher than the impurity concentration of the P-type first body layer 4 in the transistor region 31. Therefore, when a surge is applied from the drain layer (N-type silicon substrate 1, N-type epi layer 2) side, hole current is concentrated from the N-type epi layer 2 to the P-type first body layer 4 in the dummy region 32. Injected. A potential difference is generated between the P-type first body layer 4 and the N-type dummy source layer 13, and the P-type first body layer 4 and the N-type dummy source layer 13 are forward-biased. As a result, the NPN bipolar transistor composed of the N-type epi layer 2, the P-type first body layer 4, and the N-type dummy source layer 13 operates.

  That is, according to the vertical semiconductor device of this embodiment, when a surge is applied from the drain layer (N-type silicon substrate 1, N-type epi layer 2) side, the N-type epi layer 2 and P-type in the transistor region 31. A surge current can be guided toward the dummy region 32 before the NPN parasitic bipolar transistor composed of the first body layer 4 and the N-type source layer 10 operates and a large current flows. The surge current guided to the dummy region 32 flows into the aluminum wiring 11 a through the N-type dummy source layer 13 in the dummy region 32. As a result, destruction of the gate oxide film 5a in the transistor region 31 can be prevented. In the configuration of the present embodiment, since the P-type first body layer 4 in the dummy region 32 is in an electrically floating state, the surge is lower than that in the configuration of the first embodiment in which the potential is fixed. A surge current can be guided from the voltage to the dummy region 32. Therefore, it is possible to prevent the gate insulating film 5a from being destroyed more efficiently than the semiconductor device according to the first embodiment.

  Further, in this configuration, the dummy source layer 13 can be formed simultaneously with the source layer 10 of the transistor region 31 in the same process, so that the number of manufacturing processes does not increase in order to realize this structure.

(Fourth embodiment)
FIG. 20 is an enlarged plan view showing the main part of the vertical semiconductor device according to the fourth embodiment of the present invention. FIG. 21 is a cross-sectional view taken along line AA in FIG. In FIG. 20, the various thin films formed on the semiconductor substrate and the insulating film on the gate electrode are not shown. In FIGS. 20 and 21, the same reference numerals are assigned to the portions having the same operational effects as those of the semiconductor device of the third embodiment.

  As shown in FIGS. 20 and 21, the vertical semiconductor device according to the present embodiment basically has the same structure as the semiconductor device according to the third embodiment. The N-type epi layer 2 includes a dummy trench 15b and a connecting dummy trench 15c that are in contact with the P-type first body layer 4 and reach the N-type epi layer 2 in the N-type epi layer 2 (drain layer). 2 is different from the vertical semiconductor device of the third embodiment in that an N-type high concentration layer 12 having an impurity concentration higher than 2 is further provided. That is, the vertical semiconductor device of this embodiment combines the features of the respective semiconductor devices described in the second and third embodiments.

  In the vertical semiconductor device having the above-described configuration, the N-type high-concentration layer 12 forming process described in the second embodiment with reference to FIGS. 13 and 14 is added to the manufacturing process described in the third embodiment. Can be realized by appropriately combining the above.

  In the vertical semiconductor device of this embodiment, in the dummy region 32, the PN junction constituted by the N-type high concentration layer 12 and the P-type first body layer 4 is an N-type epi layer in the semiconductor device of the third embodiment. 2 and the breakdown voltage of the PN junction composed of the P-type first body layer 4. That is, in the configuration of the present embodiment, hole current is more likely to be injected from the N-type epi layer 2 to the P-type first body layer 4 in the dummy region 32 than in the configuration of the third embodiment.

  When a surge is applied to the semiconductor device having such a structure from the drain layer (N-type silicon substrate 1, N-type epi layer 2) side, the N-type epi layer 2 and the P-type first body layer in the transistor region 31 The surge current can be guided toward the dummy region 32 before the NPN parasitic bipolar transistor composed of the 4 and N type source layers 10 operates and a large current flows. In the configuration of the present embodiment, a surge current can be guided to the dummy region 32 from a surge voltage lower than that of the configuration of the third embodiment. Therefore, the gate insulating film 5a can be more efficiently prevented from being destroyed than the semiconductor device according to the third embodiment. That is, according to the configuration of the present embodiment, the surge resistance of the semiconductor device can be improved as compared with the first to third embodiments.

  As described above, according to the present invention, it is possible to reliably prevent the occurrence of device destruction when a transient surge is applied to the drain even when the device is miniaturized to reduce the on-resistance. it can. In addition, since the manufacturing process is not significantly complicated, a low on-resistance vertical semiconductor device can be realized at low cost.

  The present invention is not limited to the above-described embodiments, and various modifications and applications are possible without departing from the technical idea of the present invention. In the above description, the P-type second body layer 9 is provided between the P-type first body layer 4 and the aluminum wiring 11a. However, the P-type second body layer 9 is disposed for the purpose of reducing contact resistance. However, the technical idea of the present application is not limited at all.

  The present invention can reliably prevent the occurrence of device breakdown when a transient surge is applied to the drain, and is useful as a vertical semiconductor device.

Plane layout view showing a vertical semiconductor device according to the first embodiment of the present invention; FIG. 4 is an enlarged plan layout view showing the vertical semiconductor device according to the first embodiment of the present invention. Sectional drawing which shows the vertical semiconductor device in the 1st Embodiment of this invention Sectional drawing which shows the manufacture process of the vertical semiconductor device in the 1st Embodiment of this invention Sectional drawing which shows the manufacture process of the vertical semiconductor device in the 1st Embodiment of this invention Sectional drawing which shows the manufacture process of the vertical semiconductor device in the 1st Embodiment of this invention Sectional drawing which shows the manufacture process of the vertical semiconductor device in the 1st Embodiment of this invention Sectional drawing which shows the manufacture process of the vertical semiconductor device in the 1st Embodiment of this invention The top view which shows the manufacturing process of the vertical semiconductor device in the 1st Embodiment of this invention The enlarged plane layout figure which shows the vertical semiconductor device in the 2nd Embodiment of this invention Sectional drawing which shows the vertical semiconductor device in the 2nd Embodiment of this invention Sectional drawing which shows the manufacture process of the vertical semiconductor device in the 2nd Embodiment of this invention Sectional drawing which shows the manufacture process of the vertical semiconductor device in the 2nd Embodiment of this invention The top view which shows the manufacture process of the vertical semiconductor device in the 2nd Embodiment of this invention Planar layout showing a vertical semiconductor device according to a third embodiment of the present invention FIG. 4 is an enlarged plan layout view showing a vertical semiconductor device according to a third embodiment of the present invention. Sectional drawing which shows the vertical semiconductor device in the 3rd Embodiment of this invention Sectional drawing which shows the manufacture process of the vertical semiconductor device in the 3rd Embodiment of this invention Sectional drawing which shows the manufacture process of the vertical semiconductor device in the 3rd Embodiment of this invention The enlarged plane layout figure which shows the vertical semiconductor device in the 4th Embodiment of this invention Sectional drawing which shows the vertical semiconductor device in the 4th Embodiment of this invention Planar layout showing a conventional vertical semiconductor device Sectional view showing a conventional vertical semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 N type silicon substrate 2 N type epitaxial layer 3 1st interlayer insulation film 4 P type 1st body layer 5a Gate insulation film 5b Dummy gate insulation film 6a Gate electrode 6b Dummy gate electrode 7 2nd interlayer insulation film 8 3rd interlayer insulation Film 9 P-type second body layer 10 N-type source layer 11a Aluminum wiring 11b Aluminum wiring 12 N-type high concentration layer 13 N-type dummy source layer 101 N-type silicon substrate 102 N-type epitaxial layer 103 First interlayer insulating film 104 P-type First body layer 105 Gate insulating film 106 Gate electrode 107 Second interlayer insulating film 108 Third interlayer insulating film 109 P-type second body layer 110 N-type source layer 111 Aluminum wiring 25 Protection diode 26 Peripheral wiring section

Claims (5)

In a vertical semiconductor device having a MOS transistor with a vertical gate,
A drain layer made of a semiconductor layer of the first conductivity type;
A body layer made of a semiconductor layer of a second conductivity type opposite to the first conductivity type provided on the drain layer;
A plurality of linear grooves formed in a state of reaching the drain layer through the body layer and arranged parallel to each other in a plan view;
A gate insulating film formed on the inner wall of each of the plurality of trenches;
A gate electrode embedded in each of the plurality of grooves via the gate insulating film;
A source layer made of a semiconductor layer of a first conductivity type formed adjacent to the groove on a part of the surface portion of the body layer between the gate electrodes;
A MOS transistor region comprising:
A drain layer continuously extended from the MOS transistor region;
A body layer formed integrally with the body layer of the MOS transistor region;
A plurality of linear dummy grooves formed in a state of penetrating the body layer and reaching the drain layer, and arranged in parallel with each other at an interval larger than an interval between the grooves of the MOS transistor region in plan view; ,
A dummy gate insulating film formed on the inner wall of each of the plurality of dummy grooves;
A dummy gate electrode embedded in each of the plurality of dummy grooves via the dummy gate insulating film and electrically floating;
A dummy region formed adjacent to the MOS transistor region;
An electrode electrically connected to the body layer of the dummy region, the body layer of the MOS transistor region, and the source layer;
A vertical semiconductor device comprising: The dummy area is
A connecting dummy groove penetrating the body layer and communicating the dummy grooves with each other;
The body layer surrounded by the dummy grooves and the connecting dummy grooves;
A connection dummy gate insulating film formed on the inner wall of the connection dummy groove;
A connection dummy gate electrode embedded in each of the connection dummy grooves via the connection dummy gate insulating film, and electrically connecting the dummy gate electrode;
A first conductivity type dummy source layer formed on the entire surface of the body layer surface portion surrounded by the dummy grooves and the connection dummy grooves;
The electrode electrically connected to the dummy source layer;
The vertical semiconductor device according to claim 1, further comprising:   A first conductivity type semiconductor layer having an impurity concentration higher than the impurity concentration of the drain layer, the dummy region being in contact with the body layer in the drain layer and including a dummy groove reaching the drain layer; The vertical semiconductor device according to claim 1, further comprising:   4. The vertical semiconductor device according to claim 1, wherein the impurity concentration of the body layer of the dummy region is higher than the impurity concentration of the body layer of the MOS transistor region. 5.   The vertical semiconductor device according to claim 2, wherein the body layer surrounded by the dummy grooves and the connecting dummy grooves is electrically floating.

Images