JP2008103375A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MOS semiconductor device having a stripe contact structure in which an on-resistance is reduced without reducing an L load tolerance. <P>SOLUTION: In forming an n<SP>+</SP>source region 24 on a region between adjacent trenches 25, an impurity is injected using a center portion of the region between the trenches as a mask, and the depth of the region of the adjacent trenches 25 of the n<SP>+</SP>source region 24 is made shallower than the depth of a portion near the trenches. Then, a high-concentration p-well region 32 having a concentration higher than that of the other portions of the p-well region 23 is formed on the shallow portion of the n<SP>+</SP>source region 24. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a trench gate structure and a method for manufacturing the same.

One of the semiconductor devices having a trench gate structure is a trench gate type MOSFET (insulated gate field effect transistor having a metal-oxide film-semiconductor structure). FIG. 10 is a cross-sectional view showing a main part of a conventional n-channel trench gate type MOSFET. In FIG. 10, reference numeral 1 denotes an n drain region, reference numeral 2 denotes an n ⁻ drift region, and reference numeral 3 denotes a p well region.

Reference numeral 4 denotes an n ⁺ source region. Reference numeral 5 denotes a trench, reference numeral 6 denotes a gate oxide film, and reference numeral 7 denotes a gate electrode. Reference numeral 8 denotes a p ⁺ well contact region. Reference numeral 9 denotes a source electrode, reference numeral 10 denotes a drain electrode, and reference numeral 11 denotes an interlayer insulating film.

In the trench gate type MOSFET having the configuration shown in FIG. 10, when the cell pitch is reduced by miniaturization, the contact area between the n ⁺ source region 4 and the source electrode 9 is reduced, which causes a problem that the source contact resistance increases. As means for solving this problem, a stripe contact structure has been proposed (see, for example, Patent Document 1).

According to this stripe contact structure, the width of a region between adjacent trenches 5 (hereinafter referred to as an inter-trench region) becomes narrow due to miniaturization, and the source electrode 9 can be n ⁺ even when a mask shift occurs. The source region 4 can be sufficiently contacted. Further, since the n ⁺ source regions 4 and the p ⁺ well contact regions 8 are alternately arranged in the longitudinal direction of the trench 5, mask alignment of the trench 5, the n ⁺ source region 4 and the p ⁺ well contact region 8 becomes unnecessary. Therefore, miniaturization becomes easy.

  FIG. 11 is a plan view showing an n-channel trench gate type MOSFET having a conventional stripe contact structure. In FIG. 11, the insulating film and the source electrode on the substrate surface are omitted. 12, FIG. 13, and FIG. 14 are cross-sectional views showing configurations at section lines AA, BB, and CC in FIG. 11, respectively.

As shown in FIG. 11, the trenches 5 are arranged in a stripe shape. In the inter-trench region, n ⁺ source regions 4 and p ⁺ well contact regions 8 extending in the short direction of the trench 5 from one side of the adjacent trench 5 to the other are alternately arranged in the longitudinal direction of the trench 5.

A p well region 3 (see FIGS. 12 and 13) is provided below the n ⁺ source region 4 and the p ⁺ well contact region 8 in the inter-trench region. In the adjacent inter-trench regions, the n ⁺ source regions 4 are adjacent to each other with the trench 5 interposed therebetween. The same applies to the p ⁺ well contact region 8.

Therefore, as shown in FIG. 12, only the n ⁺ source region 4 appears on the p-well region 3 in a cross section taken along a certain cutting line (AA in FIG. 11) parallel to the short direction of the trench 5. However, the source electrode 9 contacts only the n ⁺ source region 4. As shown in FIG. 13, only the p ⁺ well contact region 8 is above the p well region 3 in a cross section taken along another cutting line (BB in FIG. 11) parallel to the short direction of the trench 5. Appears on. The source electrode 9 is in contact only with the p ⁺ well contact region 8.

JP 2000-252468 A (FIG. 4, FIG. 5, paragraph numbers [0023] to [0024])

However, the conventional stripe contact structure described above has the following problems. As shown in FIG. 13, the source region does not exist in the portion where the p ⁺ well contact region 8 exists. Therefore, even if the MOSFET is turned on and a channel is formed, almost no current flows in the portion where the p ⁺ well contact region 8 exists. Accordingly, the on-resistance increases.

As a countermeasure, it is conceivable to increase the channel width by increasing the width of the n ⁺ source region 4. However, by simply increasing the width of the n ⁺ source region 4, as shown in FIG. 14, the p-well region 3, since the n ⁺ parasitic resistance 16 of the region under the source region 4 is increased, the bipolar operation As a result, there arises a problem that the L load withstand capability decreases.

  An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can reduce the on-resistance without reducing the L load withstand capability in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a first aspect of the present invention includes a first conductivity type semiconductor substrate layer, and a second conductivity type well region provided on the semiconductor substrate layer. A plurality of stripe-shaped trenches that penetrate the well region and reach the semiconductor substrate layer, a source region of a first conductivity type that is selectively provided on the well region, and selectively on the well region A well contact region of a second conductivity type provided, a gate electrode provided in the trench via a gate insulating film, a first electrode in common contact with the source region and the well contact region, and the semiconductor substrate A second electrode electrically connected to the layer, wherein the source region and the well contact region are both from one trench to the other between the adjacent trenches. In a semiconductor device that extends to the trench and is alternately arranged in the longitudinal direction of the trench, the depth of the central portion of the source region between the adjacent trenches is shallower than the depth of the vicinity of the trench of the source region. It is characterized by that.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the concentration of the shallow portion of the source region in the well region is higher than the concentration of other portions of the well region. It is characterized by.

  According to a third aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein the well region has a high concentration well in a shallow portion of the source region, the concentration of which is higher than other portions of the well region. A region is provided.

  A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the length of the source region in the trench longitudinal direction is the length of the well contact region in the trench longitudinal direction. It is characterized by being longer than twice the length.

  According to a fifth aspect of the present invention, there is provided a semiconductor device manufacturing method including a first conductivity type semiconductor substrate layer, a second conductivity type well region provided on the semiconductor substrate layer, and the well region. A plurality of stripe-shaped trenches reaching the semiconductor substrate layer, a first conductivity type source region selectively provided on the well region, and a second conductivity type selectively provided on the well region A well contact region, a gate electrode provided in the trench through a gate insulating film, a first electrode that is in common contact with the source region and the well contact region, and the semiconductor substrate layer are electrically connected A second electrode, and both the source region and the well contact region extend from one trench to the other trench between the adjacent trenches, Further, the depth of the central portion between the adjacent trenches in the source region is shallower than the depth in the vicinity of the trench in the source region, and the well region In the method of manufacturing a semiconductor device in which the concentration of the shallow portion of the source region is higher than the concentration of the other portion of the well region, the well region provided on the semiconductor substrate layer has the same concentration. Forming a plurality of stripe-shaped trenches penetrating through the well region and reaching the semiconductor substrate layer; and opening the region in the vicinity of the trench between the adjacent trenches in the region forming the source region; A source region type in which a first conductivity type impurity is implanted into the well region using a first mask having a pattern covering a central portion between trenches A second conductive type impurity is implanted into the well region using a step, a mask removing step of removing the first mask, and a second mask having a pattern in which a region for forming the well contact region is opened And a well contact region forming step.

  According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the fifth aspect of the present invention, wherein the entire area between adjacent trenches is formed after the mask removing step and before the well contact region forming step. And a high-concentration well region forming step of implanting a second conductivity type impurity.

  According to the present invention, the on-resistance is lowered by increasing the width of the source region to increase the channel width. In addition, the parasitic resistance component in the well region and the region under the source region is reduced, and the L load withstand capability can be prevented from being lowered.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, there is an effect that the on-resistance can be reduced without reducing the L load withstand capability.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, this MOSFET has an n ⁻ drift region 22 on an n drain region 21. N drain region 21 and n ⁻ drift region 22 constitute an n-type semiconductor substrate layer. P well region 23 is provided in the surface layer of n ⁻ drift region 22.

Trench 25 penetrates p well region 23 and reaches n ⁻ drift region 22. The planar pattern of the trench 25 is striped, as in the conventional MOS semiconductor device shown in FIG. The gate oxide film 26 is provided along the inner wall surface of the trench 25. The trench 25 is filled with a gate electrode 27 through a gate oxide film 26.

The n ⁺ source region 24 is selectively provided in the surface layer of the p well region 23. The n ⁺ source region 24 is in contact with the gate oxide film 26. The p ⁺ well contact region is selectively provided in the surface layer of the p well region 23. However, since the p ⁺ well contact region is arranged so as to appear in a cross section different from that in FIG. 1, it does not appear in FIG. The n ⁺ source regions 24 and the p ⁺ well contact regions are alternately formed in a stripe shape so as to be orthogonal to the stripe direction of the trench 25 as in the conventional configuration shown in FIG. The p ⁺ well contact region corresponds to the p ⁺ well contact region 8 in the conventional configuration shown in FIG.

Therefore, the n ⁺ source region 24 and the p ⁺ well contact region extend in the short direction of the trench 25 from one side to the other between the adjacent trenches 25 in the inter-trench region, and alternate in the longitudinal direction of the trench 25. Is arranged. The source electrode 29 that is the first electrode is in contact with the n ⁺ source region 24 and the p ⁺ well contact region, and is insulated from the gate electrode 27 by the interlayer insulating film 31. The drain electrode 30 as the second electrode is provided on the back surface thereof in contact with the n drain region 21.

Here, the n ⁺ source region 24 is shallower in the central portion of the inter-trench region than in the vicinity of the trench. The concentration of the shallow portion of the n ⁺ source region 24 is higher than the concentration of other portions of the p well region 23. That is, a high-concentration p-well region 32 having a higher concentration than other portions of the p-well region 23 is provided in a portion of the p-well region 23 where the n ⁺ source region 24 is shallow.

The length of the n ⁺ source region 24 in the longitudinal direction of the trench is longer than twice the length of the p ⁺ well contact region in the longitudinal direction of the trench. Although not particularly limited, for example, the length of the n ⁺ source region 24 in the trench longitudinal direction is four times the length of the p ⁺ well contact region in the trench longitudinal direction. The cell pitch is 2.2 μm, for example. In short, in the embodiment, the area of the p ⁺ well contact region is made smaller than in the prior art, and a high concentration p ⁺ region is arranged under the n ⁺ source region 24.

2 to 7 are sectional views or plan views for explaining a method of manufacturing a semiconductor device according to the embodiment of the present invention. First, the n ⁻ drift region 22 is epitaxially grown on the n drain region 21. At that time, the impurity concentration of the n ⁻ drift region 22 is, for example, 1 × 10 ¹⁶ cm ⁻³ . These n drain region 21 and n ⁻ drift region 22 are combined to form a semiconductor substrate layer.

  Next, the surface of the semiconductor substrate layer is selectively oxidized by a LOCOS (Local Oxidation of Silicon) process to form a field oxide film. Thereafter, a p-well region 23 is formed on the surface layer of the semiconductor substrate layer by a thermal diffusion technique or the like, and a mask oxide film is formed on the surface. Next, a resist is applied to the surface of the semiconductor substrate layer, and photolithography and etching are performed to form a mask oxide film as a trench formation pattern.

Using this mask oxide film as a mask, anisotropic dry etching such as RIE (Reactive Ion Etching) is performed to form a trench 25 having a depth reaching the n ⁻ drift region 22 through the p well region 23. Subsequently, soft etching such as CDE (Chemical Dry Etching) or sacrificial oxidation treatment is performed to flatten the roughness of the surface generated during the trench etching. Then, the mask oxide film is removed.

  Next, the inside of the trench 25 and the surface of the semiconductor substrate layer are oxidized to form a gate oxide film 26. Thereafter, for example, doped polysilicon is deposited, and the trench 25 is filled with the gate electrode 27. Then, except for a part of the gate electrode 27, a portion of the gate electrode 27 above the surface of the semiconductor substrate layer is removed. Next, after removing the gate oxide film 26 on the surface of the semiconductor substrate layer, a screen oxide film 41 is formed on the surfaces of the semiconductor substrate layer and the gate electrode 27 (FIG. 2).

  Next, a resist is applied to the surface of the semiconductor substrate layer, and a resist mask (first mask) for forming a source region is formed by photolithography. As shown by hatching in FIG. 3, the resist mask 42 has a pattern that covers the central portion of the p-well region 23 where the well contact region is formed and the region between the trenches. Next, using the resist mask 42, for example, arsenic (As) is implanted as the first conductivity type impurity ions perpendicularly to the surface of the semiconductor substrate layer.

In FIG. 3, “n ⁺ ” regions on both sides of the trench 25 represent regions where arsenic is implanted (the same applies to FIG. 5). Next, heat treatment is performed to diffuse and activate arsenic to selectively form an n ⁺ source region 24 in the surface layer of the p well region 23 (FIG. 4). FIG. 4 is a cross-sectional view showing the configuration at section line DD in FIG. 3 after forming the n ⁺ source region.

Note that, when the impurity implantation for forming the n ⁺ source region 24 is performed, the resist mask 43 having the pattern shown in FIG. 5 may be used instead of the resist mask having the pattern shown in FIG. As indicated by hatching in FIG. 5, the resist mask 43 has a pattern that covers only the central portion of the inter-trench region.

After removing the resist mask 42 (in the case of the pattern shown in FIG. 5, the resist mask 43), for example, boron fluoride (BF ₂ ) as the second conductivity type impurity ions is formed on the entire surface of the semiconductor substrate layer. Implant perpendicular to the surface of the layer. Subsequently, heat treatment is performed to form a high concentration p-well region 32. Next, a resist is applied again on the surface of the semiconductor substrate layer, and a resist mask (second mask) for forming a p ⁺ well contact region is formed by photolithography.

As shown by hatching in FIG. 6, the resist mask 44 has a pattern that covers the p-well region 23 other than the region where the well contact region is formed. Next, for example, boron (B) is implanted as impurity ions of the second conductivity type using the resist mask 44. In FIG. 6, “p ⁺ ” regions on both sides of the trench 25 represent regions where boron is implanted. Next, heat treatment is performed to form ap ⁺ well contact region in the surface layer of the p well region 23.

Further, when forming the p ⁺ well contact region, a pattern obtained by inverting the pattern shown in FIG. 6, that is, by using a resist mask having a pattern covering the p ⁺ well contact region, implanting a low acceleration for example, arsenic ions The concentration of the n ⁺ source region 24 in contact with the source electrode 29 may be set to 1 × 10 ²⁰ cm ⁻³ or more by performing heat treatment. At this time, the heat treatment may be performed together with the heat treatment for forming the p ⁺ well contact region.

FIG. 7 is a cross-sectional view showing the configuration at section line EE in FIG. 6 after the p ⁺ well contact region is formed. After removing the resist mask 44, an interlayer insulating film 31 is formed on the gate electrode 27 as shown in FIG. Further, a source electrode 29 and a metal gate electrode not shown in the figure are formed thereon. Further, the drain electrode 30 is formed on the back surface of the n drain region 21. As described above, the MOSFET is completed.

  Next, the vertical impurity profiles in the inter-trench region are compared between the MOSFET of the embodiment and the conventional stripe contact MOSFET. FIG. 8 is a characteristic diagram showing the impurity profile at FF ′ and GG ′ in FIG. 1, and FIG. 9 is a characteristic diagram showing the impurity profile at HH ′ in FIG. The threshold voltage of the MOSFET and the parasitic resistance under the source region are determined by the position where the characteristic curve of arsenic (As) and the characteristic curve of boron (B) intersect.

  In the embodiment, a boron profile indicated by B in FIG. 8 is obtained. In the vicinity of the trench, since the source region has the same depth as the conventional one, the characteristic curve of arsenic indicated by As (FF ′) and the characteristic curve of boron indicated by B are both the conventional characteristic curve shown in FIG. Will be the same. Therefore, since the intersection 51 of the arsenic characteristic curve and the boron characteristic curve in the embodiment is at the same position as the conventional intersection 53 shown in FIG. 9, the threshold in the embodiment is the same as the conventional threshold. Be the same.

  On the other hand, in the central portion of the inter-trench region, the source region is shallower than in the prior art, and a high-concentration p-well region exists below the source region. Therefore, the intersection 52 of the arsenic characteristic curve and the boron characteristic curve in the embodiment Shifts to a higher boron concentration than the conventional intersection 53 shown in FIG. Therefore, the parasitic resistance of the embodiment is lower than that of the prior art.

  When the on-resistance Ron was compared with the MOSFET of the embodiment and the MOSFET of the conventional stripe contact structure with the same L load withstand capability, the embodiment was 8% lower than the conventional structure. In the embodiment, since mask alignment of the trench and the source is necessary, the cell pitch is set to 2.2 μm, and the ratio of the length of the source region to the length of the well contact region is set to 4: l. On the other hand, in the conventional stripe contact structure, the cell pitch is set to 2 μm, but the ratio of the length of the source region and the length of the well contact region, which has the same L load resistance as in the embodiment, was 2: 1.

As described above, according to the embodiment, the on-resistance can be lowered without affecting the threshold voltage. Further, since the parasitic resistance component in the region under the n ⁺ source region 24 in the p well region 23 is reduced, it is possible to prevent the L load withstand capability from being lowered. Therefore, the on-resistance can be reduced without reducing the L load withstand capability.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the dimensions and concentrations described in the embodiments are examples, and the present invention is not limited to these values. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for a semiconductor device having a trench gate structure, and in particular, a source region and a well contact in an inter-trench region of a trench gate structure arranged in a stripe shape. This is suitable for a trench gate type power MOSFET having a structure in which regions are alternately arranged in the longitudinal direction of the trench.

It is sectional drawing which shows the structure of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a top view explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a top view explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a top view explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a characteristic view which shows the impurity profile of the semiconductor device concerning embodiment of this invention. It is a characteristic view which shows the impurity profile of the conventional MOSFET. It is sectional drawing which shows the principal part of the conventional trench gate type MOSFET. It is a top view which shows the trench gate type MOSFET which has the conventional stripe contact structure. It is sectional drawing which shows the structure in the cutting line AA of FIG. It is sectional drawing which shows the structure in the cutting line BB of FIG. It is sectional drawing which shows the structure in the cutting line CC of FIG.

Explanation of symbols

21 n drain region 22 n ⁻ drift region 23 p well region 24 n ⁺ source region 25 trench 26 gate oxide film 27 gate electrode 29 source electrode 30 drain electrode 32 high concentration p well region 42, 43, 44 resist mask

Claims (6)

A first conductivity type semiconductor substrate layer; a second conductivity type well region provided on the semiconductor substrate layer; a plurality of stripe-shaped trenches penetrating the well region to reach the semiconductor substrate layer; and the well region A first conductivity type source region selectively provided on the well region, a second conductivity type well contact region selectively provided on the well region, and a gate insulating film provided in the trench. A gate electrode, a first electrode in common contact with the source region and the well contact region, and a second electrode electrically connected to the semiconductor substrate layer, the source region and the well contact region However, both of the semiconductor devices extend from one trench to the other trench between adjacent trenches and are alternately arranged in the longitudinal direction of the trench. Te,
A semiconductor device, wherein a depth of a central portion between adjacent trenches of the source region is shallower than a depth of a portion in the vicinity of the trench of the source region.   2. The semiconductor device according to claim 1, wherein a concentration of a shallow portion of the well region in the well region is higher than a concentration of other portions of the well region.   2. The semiconductor device according to claim 1, wherein a high concentration well region having a higher concentration than other portions of the well region is provided in a shallow portion of the well region in the source region.   4. The semiconductor device according to claim 1, wherein the length of the source region in the longitudinal direction of the trench is longer than twice the length of the well contact region in the longitudinal direction of the trench. A first conductivity type semiconductor substrate layer; a second conductivity type well region provided on the semiconductor substrate layer; a plurality of stripe-shaped trenches penetrating the well region to reach the semiconductor substrate layer; and the well region A first conductivity type source region selectively provided on the well region, a second conductivity type well contact region selectively provided on the well region, and a gate insulating film provided in the trench. A gate electrode, a first electrode in common contact with the source region and the well contact region, and a second electrode electrically connected to the semiconductor substrate layer, the source region and the well contact region Are both extended from one trench to the other trench between the adjacent trenches, and alternately arranged in the longitudinal direction of the trench, The depth of the central portion between the adjacent trenches in the source region is shallower than the depth in the vicinity of the trench in the source region, and the concentration of the shallow portion of the source region in the well region is the same well region. In a method for manufacturing a semiconductor device for manufacturing a semiconductor device having a concentration higher than that of other portions,
Forming a plurality of stripe-shaped trenches that penetrate the well region and reach the semiconductor substrate layer in the well region provided on the semiconductor substrate layer;
In the well region, a first mask having a pattern that opens a portion in the vicinity of the trench between the adjacent trenches in a region forming the source region and covers a central portion between the adjacent trenches is formed in the well region. A source region forming step of implanting one conductivity type impurity;
A mask removing step of removing the first mask;
A well contact region forming step of implanting a second conductivity type impurity into the well region using a second mask having a pattern in which a region for forming the well contact region is opened;
A method for manufacturing a semiconductor device, comprising: A high-concentration well region forming step of implanting a second conductivity type impurity in the entire region between the adjacent trenches after the mask removing step and before the well contact region forming step;
The method of manufacturing a semiconductor device according to claim 5, further comprising:

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