JP5168876B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP5168876B2
JP5168876B2 JP2006282156A JP2006282156A JP5168876B2 JP 5168876 B2 JP5168876 B2 JP 5168876B2 JP 2006282156 A JP2006282156 A JP 2006282156A JP 2006282156 A JP2006282156 A JP 2006282156A JP 5168876 B2 JP5168876 B2 JP 5168876B2
Authority
JP
Japan
Prior art keywords
region
well
trench
well region
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2006282156A
Other languages
Japanese (ja)
Other versions
JP2008103375A (en
Inventor
祐司 佐野
明彦 大井
匡 蛇沼
Original Assignee
富士電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社 filed Critical 富士電機株式会社
Priority to JP2006282156A priority Critical patent/JP5168876B2/en
Publication of JP2008103375A publication Critical patent/JP2008103375A/en
Application granted granted Critical
Publication of JP5168876B2 publication Critical patent/JP5168876B2/en
Application status is Active legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Description

  The present invention relates to a semiconductor device having a trench gate structure and a method for manufacturing the same.

One of the semiconductor devices having a trench gate structure is a trench gate type MOSFET (insulated gate field effect transistor having a metal-oxide film-semiconductor structure). FIG. 10 is a cross-sectional view showing a main part of a conventional n-channel trench gate type MOSFET. In FIG. 10, reference numeral 1 denotes an n drain region, reference numeral 2 denotes an n drift region, and reference numeral 3 denotes a p well region.

Reference numeral 4 denotes an n + source region. Reference numeral 5 denotes a trench, reference numeral 6 denotes a gate oxide film, and reference numeral 7 denotes a gate electrode. Reference numeral 8 denotes a p + well contact region. Reference numeral 9 denotes a source electrode, reference numeral 10 denotes a drain electrode, and reference numeral 11 denotes an interlayer insulating film.

In the trench gate type MOSFET having the configuration shown in FIG. 10, when the cell pitch is reduced by miniaturization, the contact area between the n + source region 4 and the source electrode 9 is reduced, which causes a problem that the source contact resistance increases. As means for solving this problem, a stripe contact structure has been proposed (see, for example, Patent Document 1).

According to this stripe contact structure, the width of a region between adjacent trenches 5 (hereinafter referred to as an inter-trench region) becomes narrow due to miniaturization, and the source electrode 9 can be n + even when a mask shift occurs. The source region 4 can be sufficiently contacted. Further, since the n + source regions 4 and the p + well contact regions 8 are alternately arranged in the longitudinal direction of the trench 5, mask alignment of the trench 5, the n + source region 4 and the p + well contact region 8 becomes unnecessary. Therefore, miniaturization becomes easy.

  FIG. 11 is a plan view showing an n-channel trench gate type MOSFET having a conventional stripe contact structure. In FIG. 11, the insulating film and the source electrode on the substrate surface are omitted. 12, FIG. 13, and FIG. 14 are cross-sectional views showing configurations at section lines AA, BB, and CC in FIG. 11, respectively.

As shown in FIG. 11, the trenches 5 are arranged in a stripe shape. In the inter-trench region, n + source regions 4 and p + well contact regions 8 extending in the short direction of the trench 5 from one side of the adjacent trench 5 to the other are alternately arranged in the longitudinal direction of the trench 5.

A p well region 3 (see FIGS. 12 and 13) is provided below the n + source region 4 and the p + well contact region 8 in the inter-trench region. In the adjacent inter-trench regions, the n + source regions 4 are adjacent to each other with the trench 5 interposed therebetween. The same applies to the p + well contact region 8.

Therefore, as shown in FIG. 12, only the n + source region 4 appears on the p-well region 3 in a cross section taken along a certain cutting line (AA in FIG. 11) parallel to the short direction of the trench 5. However, the source electrode 9 contacts only the n + source region 4. As shown in FIG. 13, only the p + well contact region 8 is above the p well region 3 in a cross section taken along another cutting line (BB in FIG. 11) parallel to the short direction of the trench 5. Appears on. The source electrode 9 is in contact only with the p + well contact region 8.

JP 2000-252468 A (FIG. 4, FIG. 5, paragraph numbers [0023] to [0024])

However, the conventional stripe contact structure described above has the following problems. As shown in FIG. 13, the source region does not exist in the portion where the p + well contact region 8 exists. Therefore, even if the MOSFET is turned on and a channel is formed, almost no current flows in the portion where the p + well contact region 8 exists. Accordingly, the on-resistance increases.

As a countermeasure, it is conceivable to increase the channel width by increasing the width of the n + source region 4. However, by simply increasing the width of the n + source region 4, as shown in FIG. 14, the p-well region 3, since the n + parasitic resistance 16 of the region under the source region 4 is increased, the bipolar operation As a result, there arises a problem that the L load withstand capability decreases.

  An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can reduce the on-resistance without reducing the L load withstand capability in order to solve the above-described problems caused by the prior art.

In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention includes a first conductivity type semiconductor substrate layer, a second conductivity type well region provided on the semiconductor substrate layer, and the well. A plurality of stripe-shaped trenches that penetrate the region and reach the semiconductor substrate layer, a source region of a first conductivity type that is selectively provided on the well region, and selectively provided on the well region The second conductivity type well contact region, the gate electrode provided in the trench through the gate insulating film, the first electrode in common contact with the source region and the well contact region, and the semiconductor substrate layer are electrically connected And the source region and the well contact region are both connected between the adjacent trenches from one trench to the other trench. In the semiconductor device that extends to the gate and is alternately arranged in the longitudinal direction of the trench, the depth of the central portion of the source region between the adjacent trenches is shallower than the depth of the vicinity of the trench of the source region. It is characterized by that.

In the semiconductor device according to the present invention as set forth in the invention described above , the concentration of the shallow portion of the source region in the well region is higher than the concentration of other portions of the well region.

In the semiconductor device according to the present invention, in the above invention, a high concentration well region having a higher concentration than other portions of the well region is provided in a shallow portion of the source region in the well region. It is characterized by.

In the semiconductor device according to the present invention as set forth in the invention described above , the length of the source region in the longitudinal direction of the trench is longer than twice the length of the well contact region in the longitudinal direction of the trench.

The semiconductor device manufacturing method according to the present invention includes a first conductivity type semiconductor substrate layer, a second conductivity type well region provided on the semiconductor substrate layer, and penetrating through the well region. A plurality of stripe-shaped trenches reaching the layer, a first conductivity type source region selectively provided on the well region, and a second conductivity type well contact region selectively provided on the well region A gate electrode provided in the trench via a gate insulating film, a first electrode in common contact with the source region and the well contact region, and a second electrode electrically connected to the semiconductor substrate layer The source region and the well contact region both extend from one trench to the other trench between adjacent trenches, and Are arranged alternately in the longitudinal direction, and the depth of the central portion between the adjacent trenches of the source region is shallower than the depth of the vicinity of the trench of the source region, and the well region, In the method of manufacturing a semiconductor device in which the concentration of the shallow portion of the source region is higher than the concentration of the other portion of the well region, the well region is provided in the well region provided on the semiconductor substrate layer. Forming a plurality of stripe-shaped trenches that penetrate the region and reach the semiconductor substrate layer; and opening the region in the vicinity of the trench between the adjacent trenches in the region forming the source region; A source region forming step of implanting a first conductivity type impurity into the well region using a first mask having a pattern covering a central portion therebetween A well for implanting a second conductivity type impurity into the well region using a mask removing step for removing the first mask and a second mask having a pattern in which a region for forming the well contact region is opened. And a contact region forming step.

In the method of manufacturing a semiconductor device according to the present invention, in the above invention, after the mask removing step and before the well contact region forming step, a second conductivity type impurity is implanted over the entire region between adjacent trenches. And a high-concentration well region forming step.

  According to the present invention, the on-resistance is lowered by increasing the width of the source region to increase the channel width. In addition, the parasitic resistance component in the well region and the region under the source region is reduced, and the L load withstand capability can be prevented from being lowered.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, there is an effect that the on-resistance can be reduced without reducing the L load withstand capability.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, this MOSFET has an n drift region 22 on an n drain region 21. N drain region 21 and n drift region 22 constitute an n-type semiconductor substrate layer. P well region 23 is provided in the surface layer of n drift region 22.

Trench 25 penetrates p well region 23 and reaches n drift region 22. The planar pattern of the trench 25 is striped, as in the conventional MOS semiconductor device shown in FIG. The gate oxide film 26 is provided along the inner wall surface of the trench 25. The trench 25 is filled with a gate electrode 27 through a gate oxide film 26.

The n + source region 24 is selectively provided in the surface layer of the p well region 23. The n + source region 24 is in contact with the gate oxide film 26. The p + well contact region is selectively provided in the surface layer of the p well region 23. However, since the p + well contact region is arranged so as to appear in a cross section different from that in FIG. 1, it does not appear in FIG. The n + source regions 24 and the p + well contact regions are alternately formed in a stripe shape so as to be orthogonal to the stripe direction of the trench 25 as in the conventional configuration shown in FIG. The p + well contact region corresponds to the p + well contact region 8 in the conventional configuration shown in FIG.

Therefore, the n + source region 24 and the p + well contact region extend in the short direction of the trench 25 from one side to the other between the adjacent trenches 25 in the inter-trench region, and alternate in the longitudinal direction of the trench 25. Is arranged. The source electrode 29 that is the first electrode is in contact with the n + source region 24 and the p + well contact region, and is insulated from the gate electrode 27 by the interlayer insulating film 31. The drain electrode 30 as the second electrode is provided on the back surface thereof in contact with the n drain region 21.

Here, the n + source region 24 is shallower in the central portion of the inter-trench region than in the vicinity of the trench. The concentration of the shallow portion of the n + source region 24 is higher than the concentration of other portions of the p well region 23. That is, a high-concentration p-well region 32 having a higher concentration than other portions of the p-well region 23 is provided in a portion of the p-well region 23 where the n + source region 24 is shallow.

The length of the n + source region 24 in the longitudinal direction of the trench is longer than twice the length of the p + well contact region in the longitudinal direction of the trench. Although not particularly limited, for example, the length of the n + source region 24 in the trench longitudinal direction is four times the length of the p + well contact region in the trench longitudinal direction. The cell pitch is 2.2 μm, for example. In short, in the embodiment, the area of the p + well contact region is made smaller than in the prior art, and a high concentration p + region is arranged under the n + source region 24.

2 to 7 are sectional views or plan views for explaining a method of manufacturing a semiconductor device according to the embodiment of the present invention. First, the n drift region 22 is epitaxially grown on the n drain region 21. At that time, the impurity concentration of the n drift region 22 is, for example, 1 × 10 16 cm −3 . These n drain region 21 and n drift region 22 are combined to form a semiconductor substrate layer.

  Next, the surface of the semiconductor substrate layer is selectively oxidized by a LOCOS (Local Oxidation of Silicon) process to form a field oxide film. Thereafter, a p-well region 23 is formed on the surface layer of the semiconductor substrate layer by a thermal diffusion technique or the like, and a mask oxide film is formed on the surface. Next, a resist is applied to the surface of the semiconductor substrate layer, and photolithography and etching are performed to form a mask oxide film as a trench formation pattern.

Using this mask oxide film as a mask, anisotropic dry etching such as RIE (Reactive Ion Etching) is performed to form a trench 25 having a depth reaching the n drift region 22 through the p well region 23. Subsequently, soft etching such as CDE (Chemical Dry Etching) or sacrificial oxidation treatment is performed to flatten the roughness of the surface generated during the trench etching. Then, the mask oxide film is removed.

  Next, the inside of the trench 25 and the surface of the semiconductor substrate layer are oxidized to form a gate oxide film 26. Thereafter, for example, doped polysilicon is deposited, and the trench 25 is filled with the gate electrode 27. Then, except for a part of the gate electrode 27, a portion of the gate electrode 27 above the surface of the semiconductor substrate layer is removed. Next, after removing the gate oxide film 26 on the surface of the semiconductor substrate layer, a screen oxide film 41 is formed on the surfaces of the semiconductor substrate layer and the gate electrode 27 (FIG. 2).

  Next, a resist is applied to the surface of the semiconductor substrate layer, and a resist mask (first mask) for forming a source region is formed by photolithography. As shown by hatching in FIG. 3, the resist mask 42 has a pattern that covers the central portion of the p-well region 23 where the well contact region is formed and the region between the trenches. Next, using the resist mask 42, for example, arsenic (As) is implanted as the first conductivity type impurity ions perpendicularly to the surface of the semiconductor substrate layer.

In FIG. 3, “n + ” regions on both sides of the trench 25 represent regions where arsenic is implanted (the same applies to FIG. 5). Next, heat treatment is performed to diffuse and activate arsenic to selectively form an n + source region 24 in the surface layer of the p well region 23 (FIG. 4). FIG. 4 is a cross-sectional view showing the configuration at section line DD in FIG. 3 after forming the n + source region.

Note that, when the impurity implantation for forming the n + source region 24 is performed, the resist mask 43 having the pattern shown in FIG. 5 may be used instead of the resist mask having the pattern shown in FIG. As indicated by hatching in FIG. 5, the resist mask 43 has a pattern that covers only the central portion of the inter-trench region.

After removing the resist mask 42 (in the case of the pattern shown in FIG. 5, the resist mask 43), for example, boron fluoride (BF 2 ) as the second conductivity type impurity ions is formed on the entire surface of the semiconductor substrate layer. Implant perpendicular to the surface of the layer. Subsequently, heat treatment is performed to form a high concentration p-well region 32. Next, a resist is applied again on the surface of the semiconductor substrate layer, and a resist mask (second mask) for forming a p + well contact region is formed by photolithography.

As shown by hatching in FIG. 6, the resist mask 44 has a pattern that covers the p-well region 23 other than the region where the well contact region is formed. Next, for example, boron (B) is implanted as impurity ions of the second conductivity type using the resist mask 44. In FIG. 6, “p + ” regions on both sides of the trench 25 represent regions where boron is implanted. Next, heat treatment is performed to form ap + well contact region in the surface layer of the p well region 23.

Further, when forming the p + well contact region, a pattern obtained by inverting the pattern shown in FIG. 6, that is, by using a resist mask having a pattern covering the p + well contact region, implanting a low acceleration for example, arsenic ions The concentration of the n + source region 24 in contact with the source electrode 29 may be set to 1 × 10 20 cm −3 or more by performing heat treatment. At this time, the heat treatment may be performed together with the heat treatment for forming the p + well contact region.

FIG. 7 is a cross-sectional view showing the configuration at section line EE in FIG. 6 after the p + well contact region is formed. After removing the resist mask 44, an interlayer insulating film 31 is formed on the gate electrode 27 as shown in FIG. Further, a source electrode 29 and a metal gate electrode not shown in the figure are formed thereon. Further, the drain electrode 30 is formed on the back surface of the n drain region 21. As described above, the MOSFET is completed.

  Next, the vertical impurity profiles in the inter-trench region are compared between the MOSFET of the embodiment and the conventional stripe contact MOSFET. FIG. 8 is a characteristic diagram showing the impurity profile at FF ′ and GG ′ in FIG. 1, and FIG. 9 is a characteristic diagram showing the impurity profile at HH ′ in FIG. The threshold voltage of the MOSFET and the parasitic resistance under the source region are determined by the position where the characteristic curve of arsenic (As) and the characteristic curve of boron (B) intersect.

  In the embodiment, a boron profile indicated by B in FIG. 8 is obtained. In the vicinity of the trench, since the source region has the same depth as the conventional one, the characteristic curve of arsenic indicated by As (FF ′) and the characteristic curve of boron indicated by B are both the conventional characteristic curve shown in FIG. Will be the same. Therefore, since the intersection 51 of the arsenic characteristic curve and the boron characteristic curve in the embodiment is at the same position as the conventional intersection 53 shown in FIG. 9, the threshold in the embodiment is the same as the conventional threshold. Be the same.

  On the other hand, in the central portion of the inter-trench region, the source region is shallower than in the prior art, and the high-concentration p-well region exists below the source region. Shifts to a higher boron concentration than the conventional intersection 53 shown in FIG. Therefore, the parasitic resistance of the embodiment is lower than that of the prior art.

  When the on-resistance Ron was compared with the MOSFET of the embodiment and the MOSFET of the conventional stripe contact structure with the same L load withstand capability, the embodiment was 8% lower than the conventional structure. In the embodiment, since mask alignment of the trench and the source is necessary, the cell pitch is set to 2.2 μm, and the ratio of the length of the source region to the length of the well contact region is set to 4: l. On the other hand, in the conventional stripe contact structure, the cell pitch is set to 2 μm, but the ratio of the length of the source region and the length of the well contact region, which has the same L load resistance as in the embodiment, was 2: 1.

As described above, according to the embodiment, the on-resistance can be lowered without affecting the threshold voltage. Further, since the parasitic resistance component in the region under the n + source region 24 in the p well region 23 is reduced, it is possible to prevent the L load withstand capability from being lowered. Therefore, the on-resistance can be reduced without reducing the L load withstand capability.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the dimensions and concentrations described in the embodiments are examples, and the present invention is not limited to these values. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for a semiconductor device having a trench gate structure, and in particular, a source region and a well contact in an inter-trench region of a trench gate structure arranged in stripes This is suitable for a trench gate type power MOSFET having a structure in which regions are alternately arranged in the longitudinal direction of the trench.

It is sectional drawing which shows the structure of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a top view explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a top view explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a top view explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device concerning embodiment of this invention. It is a characteristic view which shows the impurity profile of the semiconductor device concerning embodiment of this invention. It is a characteristic view which shows the impurity profile of the conventional MOSFET. It is sectional drawing which shows the principal part of the conventional trench gate type MOSFET. It is a top view which shows the trench gate type MOSFET which has the conventional stripe contact structure. It is sectional drawing which shows the structure in the cutting line AA of FIG. It is sectional drawing which shows the structure in the cutting line BB of FIG. It is sectional drawing which shows the structure in the cutting line CC of FIG.

Explanation of symbols

21 n drain region 22 n drift region 23 p well region 24 n + source region 25 trench 26 gate oxide film 27 gate electrode 29 source electrode 30 drain electrode 32 high concentration p well region 42, 43, 44 resist mask

Claims (7)

  1. A first conductivity type semiconductor substrate layer; a second conductivity type well region provided on the semiconductor substrate layer; a plurality of stripe-shaped trenches penetrating the well region to reach the semiconductor substrate layer; and the well region A first conductivity type source region selectively provided on the well region, a second conductivity type well contact region selectively provided on the well region, and a gate insulating film provided in the trench. A gate electrode, a first electrode in common contact with the source region and the well contact region, and a second electrode electrically connected to the semiconductor substrate layer, the source region and the well contact region However, both of the semiconductor devices extend from one trench to the other trench between adjacent trenches and are alternately arranged in the longitudinal direction of the trench. Te,
    The source regions are adjacent to each other while decreasing in concentration from a portion in contact with the adjacent trench toward a central portion between the trenches,
    A semiconductor device, wherein a concentration of the well region under the central portion is higher than a concentration of other portions of the well region.
  2. High concentration portion of the well region under the central portion, the semiconductor device according to claim 1, characterized in that shallower than the source region.
  3. The second conductivity type impurity is implanted into the entire surface of the region between the adjacent trenches, so that the concentration of the well region under the central portion is higher than the concentration of other portions of the well region. The semiconductor device according to claim 1 or 2 .
  4. A first conductivity type semiconductor substrate layer; a second conductivity type well region provided on the semiconductor substrate layer; a plurality of stripe-shaped trenches penetrating the well region to reach the semiconductor substrate layer; and the well region A first conductivity type source region selectively provided on the well region, a second conductivity type well contact region selectively provided on the well region, and a gate insulating film provided in the trench. A gate electrode, a first electrode in common contact with the source region and the well contact region, and a second electrode electrically connected to the semiconductor substrate layer, the source region and the well contact region However, both of the semiconductor devices extend from one trench to the other trench between adjacent trenches and are alternately arranged in the longitudinal direction of the trench. Te,
    The source regions are adjacent to each other while decreasing in concentration from a portion in contact with the adjacent trench toward a central portion between the trenches,
    A semiconductor device characterized in that a high concentration well region having a higher concentration than other portions of the well region is provided in the well region under the central portion.
  5. The semiconductor device according to claim 4 , wherein the high-concentration well region is shallower than the source region.
  6. By implanting a second conductivity type impurity into the entire surface of the region between adjacent trenches, a high concentration well region having a higher concentration than other portions of the well region is provided in the well region below the central portion. 6. The semiconductor device according to claim 4 , wherein the semiconductor device is formed.
  7. A first conductivity type semiconductor substrate layer; a second conductivity type well region provided on the semiconductor substrate layer; a plurality of stripe-shaped trenches penetrating the well region to reach the semiconductor substrate layer; and the well region A first conductivity type source region selectively provided on the well region, a second conductivity type well contact region selectively provided on the well region, and a gate insulating film provided in the trench. A gate electrode, a first electrode in common contact with the source region and the well contact region, and a second electrode electrically connected to the semiconductor substrate layer, the source region and the well contact region Are both extended from one trench to the other trench between the adjacent trenches, and alternately arranged in the longitudinal direction of the trench, The depth of the central portion between the adjacent trenches in the source region is shallower than the depth in the vicinity of the trench in the source region, and the concentration of the shallow portion of the source region in the well region is the same well region. In a method for manufacturing a semiconductor device for manufacturing a semiconductor device having a concentration higher than that of other portions,
    Forming a plurality of stripe-shaped trenches that penetrate the well region and reach the semiconductor substrate layer in the well region provided on the semiconductor substrate layer;
    In the well region, a first mask having a pattern that opens a portion in the vicinity of the trench between the adjacent trenches in a region forming the source region and covers a central portion between the adjacent trenches is formed in the well region. A source region forming step of implanting one conductivity type impurity;
    A mask removing step of removing the first mask;
    A high-concentration well region forming step of implanting a second conductivity type impurity over the entire surface of the region between adjacent trenches;
    A well contact region forming step of implanting a second conductivity type impurity into the well region using a second mask having a pattern in which a region for forming the well contact region is opened;
    A method for manufacturing a semiconductor device, comprising:
JP2006282156A 2006-10-17 2006-10-17 Semiconductor device and manufacturing method thereof Active JP5168876B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006282156A JP5168876B2 (en) 2006-10-17 2006-10-17 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006282156A JP5168876B2 (en) 2006-10-17 2006-10-17 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2008103375A JP2008103375A (en) 2008-05-01
JP5168876B2 true JP5168876B2 (en) 2013-03-27

Family

ID=39437507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006282156A Active JP5168876B2 (en) 2006-10-17 2006-10-17 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP5168876B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009170629A (en) * 2008-01-16 2009-07-30 Nec Electronics Corp Method for manufacturing semiconductor device
JP5564763B2 (en) * 2008-06-05 2014-08-06 富士電機株式会社 Method for manufacturing MOS type semiconductor device
JP5546903B2 (en) * 2010-02-26 2014-07-09 本田技研工業株式会社 semiconductor device
JP6462367B2 (en) * 2015-01-13 2019-01-30 ルネサスエレクトロニクス株式会社 Semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3307785B2 (en) * 1994-12-13 2002-07-24 三菱電機株式会社 An insulated gate semiconductor device
US6204533B1 (en) * 1995-06-02 2001-03-20 Siliconix Incorporated Vertical trench-gated power MOSFET having stripe geometry and high cell density
US6429481B1 (en) * 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
US6351009B1 (en) * 1999-03-01 2002-02-26 Fairchild Semiconductor Corporation MOS-gated device having a buried gate and process for forming same
WO2005062386A1 (en) * 2003-12-22 2005-07-07 Matsushita Electric Industrial Co., Ltd. Vertical gate semiconductor device and process for fabricating the same
JP4760023B2 (en) * 2005-01-24 2011-08-31 株式会社デンソー Semiconductor device
JP2006228906A (en) * 2005-02-16 2006-08-31 Sanyo Electric Co Ltd Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
JP2008103375A (en) 2008-05-01

Similar Documents

Publication Publication Date Title
DE102008000660B4 (en) The silicon carbide semiconductor device
JP4833517B2 (en) Method of manufacturing a high voltage power MOSFET having a voltage sustaining region including a doped column formed by rapid diffusion
JP5588670B2 (en) Semiconductor device
KR101296984B1 (en) Charge balance field effect transistor
JP4590884B2 (en) Semiconductor device and manufacturing method thereof
US6617656B2 (en) EDMOS device having a lattice type drift region
WO2009119735A1 (en) Semiconductor device, and method for manufacturing the same
JP4414863B2 (en) Insulated gate semiconductor device and manufacturing method thereof
JP2006049543A (en) Semiconductor device and manufacturing method therefor
JP5530602B2 (en) Semiconductor device and manufacturing method thereof
JP2007189192A (en) Semiconductor device
KR100958421B1 (en) Power device and method for manufacturing the same
JP2006073740A (en) Semiconductor device and its manufacturing method
US20020038887A1 (en) Power semiconductor device
JP2007035841A (en) Semiconductor device
JP2004514265A5 (en)
JP3831602B2 (en) Manufacturing method of semiconductor device
US20050218472A1 (en) Semiconductor device manufacturing method thereof
JPWO2005062386A1 (en) Vertical gate semiconductor device and manufacturing method thereof
JP2007027266A (en) Semiconductor element and its fabrication process
US7335949B2 (en) Semiconductor device and method of fabricating the same
JP4201764B2 (en) Trench MOSFET with electric field relief characteristics
JP2009141243A (en) Semiconductor device
JP4836427B2 (en) Semiconductor device and manufacturing method thereof
JP2009239111A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090817

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20091112

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20091112

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20110422

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120719

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120724

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120924

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121016

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121106

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20121204

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20121217

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250