CN109817720A - Groove power MOSFET and manufacturing method - Google Patents
Groove power MOSFET and manufacturing method Download PDFInfo
- Publication number
- CN109817720A CN109817720A CN201910089924.6A CN201910089924A CN109817720A CN 109817720 A CN109817720 A CN 109817720A CN 201910089924 A CN201910089924 A CN 201910089924A CN 109817720 A CN109817720 A CN 109817720A
- Authority
- CN
- China
- Prior art keywords
- cellular construction
- mosfet
- gate
- sbr
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000001413 cellular effect Effects 0.000 claims abstract description 143
- 238000010276 construction Methods 0.000 claims abstract description 143
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 70
- 229920005591 polysilicon Polymers 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 110
- 239000000758 substrate Substances 0.000 claims description 42
- 239000004065 semiconductor Substances 0.000 claims description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000000407 epitaxy Methods 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000011084 recovery Methods 0.000 abstract description 7
- 230000008929 regeneration Effects 0.000 abstract description 4
- 238000011069 regeneration method Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of groove power MOSFET, including multiple trench gates, body area, source region and positioned at the drain region at the back side, trench gate includes gate trench, gate dielectric layer and polysilicon gate.Groove power MOSFET includes the multiple MOSFET cellular constructions and at least one SBR cellular construction being in parallel.The top of the polysilicon gate of MOSFET cellular construction is connected to the grid being made of front metal layer by contact hole, and the top in source region and the body area is connected to the source electrode being made of front metal layer by contact hole.Polysilicon gate, source region and the top in body area of SBR cellular construction are connected to the source electrode being made of front metal layer by contact hole.The invention also discloses the manufacturing methods of groove power MOSFET a kind of.The present invention can be embedded in SBR cellular construction, so as to improve the regeneration rate of device, realize fast quick-recovery.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacturing fields, more particularly to a kind of groove power MOSFET.
The invention further relates to the manufacturing methods of groove power MOSFET a kind of.
Background technique
As shown in Figure 1, being the structural schematic diagram of existing groove power MOSFET, existing groove power MOSFET includes
Multiple trench gates.
The trench gate includes gate trench, gate dielectric layer 102 and polysilicon gate 103, and the gate dielectric layer 102 is formed in
The bottom surface of the gate trench and side, the polysilicon gate 103 are filled in the trench gate.
The gate trench is formed in the first epitaxial layer 101 of the first conduction type.
The body area 104 of second conduction type is formed in the first epitaxial layer 101, and the depth of the polysilicon gate 103 is greater than
The junction depth in the body area 104 is used to form channel by the surface that 103 side of polysilicon gate covers the body area 104.
The source region 105 of the first conduction type heavy doping is formed in the top surface in the body area 104.
Drain region 110 is made of the first conduction type heavily doped region for being formed in 101 back side of the first epitaxial layer.
Drift region is formed by first epitaxial layer 101 between the body area 104 and the drain region 110.
Groove power MOSFET includes the MOSFET cellular construction 201 of multiple parallel connections.
The top of the polysilicon gate 103 of the MOSFET cellular construction 201 is connected to by contact hole 107 by front
The top in the grid that metal layer 109 forms, the source region 105 and the body area 104 is connected to by contact hole 107 by positive gold
Belong to the source electrode that layer 109 forms.
The contact hole 107 passes through interlayer film 106, and the front metal layer 109 is formed in the table of the interlayer film 106
Face.
The back side in the drain region 110 is formed with the drain electrode being made of metal layer on back 111.
In general, first epitaxial layer 101 is formed in semiconductor substrate surface.The semiconductor substrate is silicon substrate, institute
Stating the first epitaxial layer 101 is silicon epitaxy layer, and the gate dielectric layer 102 is gate oxide.
The gate trench of the trench gate of each MOSFET cellular construction 201 is connected and each MOSFET
The polysilicon gate 103 of the trench gate of cellular construction 201 connects.
Draw in the body that the bottom of the corresponding contact hole 107 of the source region 105 is formed with the second conduction type heavy doping
Area 108 out, the corresponding contact hole 107 of the source region 105 are contacted by the body draw-out area 108 and the body area 104.
The semiconductor substrate has the first conduction type heavy doping, and the drain region 110 is by the semiconductor after being thinned
Substrate directly forms；Or the drain region 110 is injected by the progress back side in the semiconductor substrate after being thinned and is formed.
When the groove power MOSFET is N-type device, the first conduction type is N-type, and the second conduction type is P
Type.Also can in other embodiments are as follows: when the groove power MOSFET is P-type device, the first conduction type is p-type,
Second conduction type is N-type.
As shown in Fig. 2, being the circuit diagram of existing groove power MOSFET；Source electrode indicates that drain electrode is indicated with D, grid with S
It is indicated with G, the corresponding electrode in 104 top of underlayer electrode, that is, body area is connected to source S.
Existing groove power MOSFET Reverse recovery shown in FIG. 1 is slower, can not achieve fast recovery.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of groove power MOSFET, can be embedded in super barrier rectifier
(Super Barrier Rectifier, SBR) cellular construction realizes fast quick-recovery so as to improve the regeneration rate of device.
For this purpose, the present invention also provides the manufacturing methods of groove power MOSFET a kind of.
In order to solve the above technical problems, groove power MOSFET provided by the invention includes multiple trench gates.
The trench gate includes gate trench, gate dielectric layer and polysilicon gate, and the gate dielectric layer is formed in the grid
The bottom surface of groove and side, the polysilicon gate are filled in the trench gate.
The gate trench is formed in the first epitaxial layer of the first conduction type.
The body area of second conduction type is formed in the first epitaxial layer, and the depth of the polysilicon gate is greater than the body area
Junction depth is used to form channel by the surface that the polysilicon gate side covers the body area.
The source region of the first conduction type heavy doping is formed in the top surface in the body area.
Drain region is made of the first conduction type heavily doped region for being formed in first epitaxial layer back side.
Drift region is formed by first epitaxial layer between the body area and the drain region.
Groove power MOSFET includes multiple MOSFET cellular constructions and at least one SBR cellular construction, each described
MOSFET cellular construction and the SBR cellular construction are in parallel.
The top of the polysilicon gate of the MOSFET cellular construction is connected to by contact hole by front metal layer group
At grid, the top in the source region and the body area is connected to the source electrode being made of front metal layer by contact hole.
The contact hole passes through interlayer film, and the front metal layer is formed in the surface of the interlayer film.
The polysilicon gate of the SBR cellular construction, the source region are connected with the top in the body area by contact hole
To the source electrode being made of front metal layer.
The back side in the drain region is formed with the drain electrode being made of metal layer on back, and the drain electrode is the MOSFET unit knot
Structure and the SBR cellular construction share.
A further improvement is that in the groove power MOSFET, the MOSFET cellular construction and the SBR unit
Structure is alternately arranged according to the number ratio of 1:1.
Alternatively, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of N:1, N is big
In 1 integer, the N in the region alternately arranged direction Shang Ge is identical or changes.
Alternatively, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of 1:N, N is big
In 1 integer, the N in the region alternately arranged direction Shang Ge is identical or changes.
Alternatively, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of M:N, N is big
In 1 integer, M is the integer greater than 1, and M and N are equal or unequal, and the N in the region alternately arranged direction Shang Ge is identical or becomes
Change, the M in the region alternately arranged direction Shang Ge is identical or changes.
A further improvement is that first epitaxial layer is formed in semiconductor substrate surface.
A further improvement is that the semiconductor substrate is silicon substrate, first epitaxial layer is silicon epitaxy layer, the grid
Dielectric layer is gate oxide.
A further improvement is that the gate trench of the trench gate of each MOSFET cellular construction be connected and
The polysilicon gate of the trench gate of each MOSFET cellular construction connects.
The institute of the polysilicon gate of the trench gate of each SBR cellular construction and each MOSFET cellular construction
The polysilicon gate for stating trench gate is not connected to.
A further improvement is that it is heavily doped to be formed with the second conduction type in the bottom of the corresponding contact hole of the source region
Miscellaneous body draw-out area, the corresponding contact hole of the source region are contacted by the body draw-out area and the body area.
A further improvement is that the semiconductor substrate has the first conduction type heavy doping, after the drain region is by being thinned
The semiconductor substrate directly form；Or the drain region is by carrying out back side injection in the semiconductor substrate after being thinned
It is formed.
A further improvement is that the groove power MOSFET is N-type device, the first conduction type is N-type, and second leads
Electric type is p-type；Alternatively, the groove power MOSFET is P-type device, the first conduction type is p-type, the second conduction type
For N-type.
In order to solve the above technical problems, the manufacturing method of groove power MOSFET provided by the invention includes following step
It is rapid:
Step 1: providing the first epitaxial layer of the first conduction type, multiple trench gates are formed in first epitaxial layer,
Including as follows step by step:
Step 11 forms multiple gate trench in first epitaxial layer.
Step 12 forms gate dielectric layer in the bottom surface of the gate trench and side.
Step 13 fills polysilicon formation polysilicon gate in the gate trench for being formed with the gate dielectric layer；Institute
Stating trench gate includes the structure being made of the gate trench, the gate dielectric layer and the polysilicon gate.
Step 2: the trap for carrying out the second conduction type is infused in formation body area, the polysilicon in first epitaxial layer
The depth of grid is greater than the junction depth in the body area, is used to form channel by the surface that the polysilicon gate side covers the body area.
Step 3: the source for carrying out the first conduction type heavy doping is infused in the top surface in the body area and forms source region.
Step 4: forming interlayer film, contact hole and front metal layer, the contact hole passes through interlayer film, to the front
Metal layer is patterned to form grid and source electrode.
Groove power MOSFET includes multiple MOSFET cellular constructions and at least one SBR cellular construction, each described
MOSFET cellular construction and the SBR cellular construction are in parallel.
The top of the polysilicon gate of the MOSFET cellular construction is connected to the grid, the source by contact hole
The top in area and the body area is connected to the source electrode by contact hole.
The polysilicon gate of the SBR cellular construction, the source region are connected with the top in the body area by contact hole
To the source electrode.
Step 5: forming the drain region being made of the first conduction type heavily doped region at the back side of first epitaxial layer；By
First epitaxial layer between the body area and the drain region forms drift region.
Step 6: form metal layer on back at the back side in the drain region and drain electrode is formed by the metal layer on back, it is described
Drain electrode is that the MOSFET cellular construction and the SBR cellular construction share.
A further improvement is that in the groove power MOSFET, the MOSFET cellular construction and the SBR unit
Structure is alternately arranged according to the number ratio of 1:1.
Alternatively, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of N:1, N is big
In 1 integer, the N in the region alternately arranged direction Shang Ge is identical or changes.
Alternatively, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of 1:N, N is big
In 1 integer, the N in the region alternately arranged direction Shang Ge is identical or changes.
Alternatively, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of M:N, N is big
In 1 integer, M is the integer greater than 1, and M and N are equal or unequal, and the N in the region alternately arranged direction Shang Ge is identical or becomes
Change, the M in the region alternately arranged direction Shang Ge is identical or changes.
A further improvement is that first epitaxial layer is formed in semiconductor substrate surface.
A further improvement is that the semiconductor substrate is silicon substrate, first epitaxial layer is silicon epitaxy layer；The grid
Dielectric layer is gate oxide, is formed using thermal oxidation technology.
A further improvement is that the gate trench of the trench gate of each MOSFET cellular construction be connected and
The polysilicon gate of the trench gate of each MOSFET cellular construction connects.
The institute of the polysilicon gate of the trench gate of each SBR cellular construction and each MOSFET cellular construction
The polysilicon gate for stating trench gate is not connected to.
A further improvement is that the contact hole opening formed after and in the opening fill metal before, also
Include the steps that forming the body draw-out area of the second conduction type heavy doping, institute in the bottom of the corresponding contact hole of the source region
The corresponding contact hole of source region is stated to contact by the body draw-out area and the body area.
A further improvement is that the semiconductor substrate has the first conduction type heavy doping, in step 5, the drain region
It is directly made of the semiconductor substrate after being thinned.
Alternatively, after the semiconductor substrate is thinned, passing through the semiconductor after being thinned in step 5
The back side is carried out in substrate to inject to form the drain region.
The present invention by the way that the connection structure of the trench gate of groove power MOSFET is made corresponding change, i.e., at least one
The polysilicon gate of trench gate is connected to source electrode, and being connected to the corresponding cellular construction of polysilicon gate of source electrode in this way, to form SBR mono-
Meta structure, SBR cellular construction and MOSFET cellular construction realize parallel connection together, to be able to achieve in groove power MOSFET
It is embedded in SBR cellular construction, SBR cellular construction has lesser threshold voltage and forward conduction voltage, so as to improve device
Regeneration rate realizes fast quick-recovery.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the structural schematic diagram of existing groove power MOSFET；
Fig. 2 is the circuit diagram of existing groove power MOSFET；
Fig. 3 is the structural schematic diagram of groove power of embodiment of the present invention MOSFET；
Fig. 4 is the circuit diagram of groove power of embodiment of the present invention MOSFET；
Fig. 5 A- Fig. 5 E is the device architecture meaning of each step of manufacturing method of groove power of embodiment of the present invention MOSFET
Figure.
Specific embodiment
As shown in figure 3, being the structural schematic diagram of groove power of embodiment of the present invention MOSFET, groove of the embodiment of the present invention
Gate power MOS FET includes multiple trench gates.
The trench gate includes gate trench 401 (please referring to shown in Fig. 5 A), gate dielectric layer 2 and polysilicon gate 3, the grid
Dielectric layer 2 is formed in bottom surface and the side of the gate trench 401, and the polysilicon gate 3 is filled in the trench gate.
The gate trench 401 is formed in the first epitaxial layer 1 of the first conduction type.
The body area 4 of second conduction type is formed in the first epitaxial layer 1, and the depth of the polysilicon gate 3 is greater than the body
The junction depth in area 4 is used to form channel by the surface that 3 side of polysilicon gate covers the body area 4.
The source region 5 of the first conduction type heavy doping is formed in the top surface in the body area 4.
Drain region 10 is made of the first conduction type heavily doped region for being formed in 1 back side of the first epitaxial layer.
Drift region is formed by first epitaxial layer 1 between the body area 4 and the drain region 10.
Groove power MOSFET includes multiple MOSFET cellular constructions 301 and at least one SBR cellular construction 302, respectively
The MOSFET cellular construction 301 and the SBR cellular construction 302 are in parallel.
The top of the polysilicon gate 3 of the MOSFET cellular construction 301 is connected to by contact hole 7 by front metal
The grids of 9 composition of layer, the top in the source region 5 and the body area 4 is connected to by contact hole 7 to be made of front metal layer 9
Source electrode.
The contact hole 7 passes through interlayer film 6, and the front metal layer 9 is formed in the surface of the interlayer film 6.
The polysilicon gate 3, the source region 5 and the top in the body area 4 of the SBR cellular construction 302 pass through contact
Hole 7 is connected to the source electrode being made of front metal layer 9.
The back side in the drain region 10 is formed with the drain electrode being made of metal layer on back 11, and the drain electrode is that the MOSFET is mono-
Meta structure 301 and the SBR cellular construction 302 share.
In the groove power MOSFET, the MOSFET cellular construction 301 and the SBR cellular construction 302 according to
The number ratio of 1:1 is alternately arranged.
Alternatively, the MOSFET cellular construction 301 and the SBR cellular construction 302 are according to the number of N:1 than alternately arranging
Column, N are the integer greater than 1, and the N in the region alternately arranged direction Shang Ge is identical or changes.
Alternatively, the MOSFET cellular construction 301 and the SBR cellular construction 302 are according to the number of 1:N than alternately arranging
Column, N are the integer greater than 1, and the N in the region alternately arranged direction Shang Ge is identical or changes.
Alternatively, the MOSFET cellular construction 301 and the SBR cellular construction 302 are according to the number of M:N than alternately arranging
Column, N are the integer greater than 1, and M is the integer greater than 1, and M and N are equal or unequal, the N in the region alternately arranged direction Shang Ge
Identical or variation, the M in the region alternately arranged direction Shang Ge is identical or changes.
First epitaxial layer 1 is formed in semiconductor substrate surface.It is more preferably selected as, the semiconductor substrate is silicon lining
Bottom, first epitaxial layer 1 are silicon epitaxy layer, and the gate dielectric layer 2 is gate oxide.
The gate trench 401 of the trench gate of each MOSFET cellular construction 301 is connected and each described
The polysilicon gate 3 of the trench gate of MOSFET cellular construction 301 connects.
The polysilicon gate 3 of the trench gate of each SBR cellular construction 302 and each MOSFET cellular construction
The polysilicon gate 3 of 301 trench gate is not connected to.
The body draw-out area of the second conduction type heavy doping is formed in the bottom of the corresponding contact hole 7 of the source region 5
8, the corresponding contact hole 7 of the source region 5 is contacted by the body draw-out area 8 and the body area 4.
The semiconductor substrate has the first conduction type heavy doping, and the drain region 10 is served as a contrast by the semiconductor after being thinned
Bottom directly forms；Or the drain region 10 is injected by the progress back side in the semiconductor substrate after being thinned and is formed.
In the embodiment of the present invention, the groove power MOSFET is N-type device, and the first conduction type is N-type, and second leads
Electric type is p-type.Also can in other embodiments are as follows: the groove power MOSFET is P-type device, and the first conduction type is
P-type, the second conduction type are N-type.
The embodiment of the present invention is by making corresponding change for the connection structure of the trench gate of groove power MOSFET, i.e., extremely
The polysilicon gate 3 of a few trench gate is connected to source electrode, and the corresponding cellular construction of polysilicon gate 3 for being connected to source electrode in this way can group
At SBR cellular construction 302, SBR cellular construction 302 and MOSFET cellular construction 301 realize parallel connection together, to be able to achieve in ditch
SBR cellular construction 302 is embedded in slot gate power MOS FET, SBR cellular construction 302 has lesser threshold voltage and forward conduction
Voltage realizes fast quick-recovery so as to improve the regeneration rate of device.
As shown in figure 4, being the circuit diagram of groove power of embodiment of the present invention MOSFET；It can be seen that SBR cellular construction
302 and MOSFET cellular construction 301 is in parallel, and the enlarged drawing of SBR cellular construction 302 is given in Fig. 4.Individually consider SBR
Cellular construction 302 can be, and it is positive source-drain voltage VFSD, VFSD that SBR cellular construction 302, which has lesser forward conduction voltage,
About 0.7V.As shown in Figure 4 it is found that grid G, source S and underlayer electrode B link together in SBR cellular construction 302, drain D
Individually connect voltage.By taking N-type device as an example, when drain D voltage is larger, SBR cellular construction 302 can be connected, and at this moment VFSD is
The voltage difference of source S and drain D is also equal to the electricity of underlayer electrode B and drain D equal to voltage difference, that is, VGD of grid G and drain D
Pressure difference, that is, VBD, VGD correspond to threshold V T ', according to threshold V T ' formula can calculate VFSD, formula is as follows:
In formula (1), VFB is flat-band voltage, φFFor the Fermi potential in the body area 4, εsFor silicon dielectric coefficient, q is electronics
The quantity of electric charge, NAFor the doping concentration in the body area 4, VT is VBD when being 0V threshold voltage.VBD is equal in the embodiment of the present invention
VT′.VFSD does not add the threshold V T of the voltage of degree electrode B also to want small it can be seen from formula (1), therefore the present invention is implemented
Example can reduce VFSD, be conducive to the fast quick-recovery of device in this way.
As seen from Figure 4, when the voltage of drain D is less than the voltage of source S, SBR cellular construction 302 ends.
It is the device of each step of manufacturing method of groove power of embodiment of the present invention MOSFET as shown in Fig. 5 A to Fig. 5 E
Structure is intended to, and the manufacturing method of groove power of embodiment of the present invention MOSFET includes the following steps:
Step 1 provides the first epitaxial layer 1 of the first conduction type, and first epitaxial layer 1 is formed in semiconductor substrate table
Face.Preferably, the semiconductor substrate is silicon substrate, and first epitaxial layer 1 is silicon epitaxy layer.
Multiple trench gates are formed in first epitaxial layer 1, including as follows step by step:
Step 11, as shown in Figure 5A, multiple gate trench 401 are formed in first epitaxial layer 1.
Step 12, as shown in Figure 5 B, forms gate dielectric layer 2 in the bottom surface of the gate trench 401 and side.It is described
Gate dielectric layer 2 is gate oxide, is formed using thermal oxidation technology.
Step 13, as shown in Figure 5 B, fill polysilicon in the gate trench 401 for being formed with the gate dielectric layer 2
Form polysilicon gate 3；The trench gate includes by the gate trench 401, the gate dielectric layer 2 and 3 groups of the polysilicon gate
At structure.
In the embodiment of the present invention, the grid ditch of the trench gate of subsequent corresponding each MOSFET cellular construction 301
Slot 401 is connected and the polysilicon gate 3 of the trench gate of each MOSFET cellular construction 301 connects.
The polysilicon gate 3 and each MOSFET of the trench gate of subsequent corresponding each SBR cellular construction 302 are mono-
The polysilicon gate 3 of the trench gate of meta structure 301 is not connected to.
Step 2: as shown in Figure 5 C, the trap for carrying out the second conduction type is infused in formation body area in first epitaxial layer 1
4, the depth of the polysilicon gate 3 is greater than the junction depth in the body area 4, and the table in the body area 4 is covered by 3 side of polysilicon gate
Face is used to form channel.
Step 3: as shown in Figure 5 C, the source for carrying out the first conduction type heavy doping is infused in the top surface in the body area 4
Middle formation source region 5.
Step 4: as shown in Figure 5 D, forming interlayer film 6, the opening 402 of contact hole 7, opening 402 passes through the interlayer film
6。
It further include in institute before filling metal after the opening 402 of the contact hole 7 is formed and in opening 402
The step of stating body draw-out area 8 of bottom the second conduction type heavy doping of formation of the corresponding contact hole 7 of source region 5, the source
The corresponding contact hole 7 in area 5 is contacted by the body draw-out area 8 and the body area 4.
As shown in fig. 5e, filling metal forms contact hole 7 in opening 402, forms front metal layer 9 later, described to connect
Contact hole 7 passes through interlayer film 6, is patterned to form grid and source electrode to the front metal layer 9.
Groove power MOSFET includes multiple MOSFET cellular constructions 301 and at least one SBR cellular construction 302, respectively
The MOSFET cellular construction 301 and the SBR cellular construction 302 are in parallel.
The top of the polysilicon gate 3 of the MOSFET cellular construction 301 is connected to the grid by contact hole 7,
The top in the source region 5 and the body area 4 is connected to the source electrode by contact hole 7.
The polysilicon gate 3, the source region 5 and the top in the body area 4 of the SBR cellular construction 302 pass through contact
Hole 7 is connected to the source electrode.
In the groove power MOSFET, the MOSFET cellular construction 301 and the SBR cellular construction 302 according to
The number ratio of 1:1 is alternately arranged.
Alternatively, the MOSFET cellular construction 301 and the SBR cellular construction 302 are according to the number of N:1 than alternately arranging
Column, N are the integer greater than 1, and the N in the region alternately arranged direction Shang Ge is identical or changes.
Alternatively, the MOSFET cellular construction 301 and the SBR cellular construction 302 are according to the number of 1:N than alternately arranging
Column, N are the integer greater than 1, and the N in the region alternately arranged direction Shang Ge is identical or changes.
Alternatively, the MOSFET cellular construction 301 and the SBR cellular construction 302 are according to the number of M:N than alternately arranging
Column, N are the integer greater than 1, and M is the integer greater than 1, and M and N are equal or unequal, the N in the region alternately arranged direction Shang Ge
Identical or variation, the M in the region alternately arranged direction Shang Ge is identical or changes.
Step 5: as shown in fig. 5e, being formed at the back side of first epitaxial layer 1 by the first conduction type heavy doping district's groups
At drain region 10；Drift region is formed by first epitaxial layer 1 between the body area 4 and the drain region 10.
The semiconductor substrate has the first conduction type heavy doping, and the drain region 10 is served as a contrast by the semiconductor after being thinned
Bottom directly forms.Alternatively, after the semiconductor substrate is thinned, by the semiconductor substrate after being thinned
The back side is carried out to inject to form the drain region 10.
Step 6: as shown in fig. 5e, forming metal layer on back 11 at the back side in the drain region 10 and by the back metal
11 composition drain electrode of layer, the drain electrode are that the MOSFET cellular construction 301 and the SBR cellular construction 302 share.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of groove power MOSFET, which is characterized in that including multiple trench gates；
The trench gate includes gate trench, gate dielectric layer and polysilicon gate, and the gate dielectric layer is formed in the gate trench
Bottom surface and side, the polysilicon gate be filled in the trench gate；
The gate trench is formed in the first epitaxial layer of the first conduction type；
The body area of second conduction type is formed in the first epitaxial layer, and the depth of the polysilicon gate is greater than the knot in the body area
It is deep, channel is used to form by the surface that the polysilicon gate side covers the body area；
The source region of the first conduction type heavy doping is formed in the top surface in the body area；
Drain region is made of the first conduction type heavily doped region for being formed in first epitaxial layer back side；
Drift region is formed by first epitaxial layer between the body area and the drain region；
Groove power MOSFET includes multiple MOSFET cellular constructions and at least one SBR cellular construction, each MOSFET
Cellular construction and the SBR cellular construction are in parallel；
The top of the polysilicon gate of the MOSFET cellular construction is connected to by contact hole to be made of front metal layer
The top in grid, the source region and the body area is connected to the source electrode being made of front metal layer by contact hole；
The contact hole passes through interlayer film, and the front metal layer is formed in the surface of the interlayer film；
The polysilicon gate, the source region and the top in the body area of the SBR cellular construction by contact hole be connected to by
The source electrode of front metal layer composition；
The back side in the drain region is formed with the drain electrode being made of metal layer on back, the drain electrode be the MOSFET cellular construction and
The SBR cellular construction shares.
2. groove power MOSFET as described in claim 1, it is characterised in that: in the groove power MOSFET, institute
MOSFET cellular construction and the SBR cellular construction is stated to be alternately arranged according to the number ratio of 1:1；
Alternatively, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of N:1, N is greater than 1
Integer, the N in the region alternately arranged direction Shang Ge it is identical or variation；
Alternatively, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of 1:N, N is greater than 1
Integer, the N in the region alternately arranged direction Shang Ge it is identical or variation；
Alternatively, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of M:N, N is greater than 1
Integer, M is integer greater than 1, and M and N are equal or unequal, and the N in the region alternately arranged direction Shang Ge is identical or variation,
M in the region alternately arranged direction Shang Ge is identical or changes.
3. groove power MOSFET as described in claim 1, it is characterised in that: first epitaxial layer is formed in semiconductor
Substrate surface.
4. groove power MOSFET as claimed in claim 3, it is characterised in that: the semiconductor substrate is silicon substrate, institute
Stating the first epitaxial layer is silicon epitaxy layer, and the gate dielectric layer is gate oxide.
5. groove power MOSFET as described in claim 1, it is characterised in that: each MOSFET cellular construction it is described
The gate trench of trench gate is connected and the polysilicon gate of the trench gate of each MOSFET cellular construction connects
It connects；
The ditch of the polysilicon gate of the trench gate of each SBR cellular construction and each MOSFET cellular construction
The polysilicon gate of slot grid is not connected to.
6. groove power MOSFET as described in claim 1, it is characterised in that: in the corresponding contact hole of the source region
Bottom be formed with the body draw-out area of the second conduction type heavy doping, the corresponding contact hole of the source region is drawn by the body
Area and body area contact out.
7. groove power MOSFET as claimed in claim 3, it is characterised in that: the semiconductor substrate has the first conduction
Type heavy doping, the drain region are directly made of the semiconductor substrate after being thinned；Or the drain region is by after being thinned
The back side is carried out in the semiconductor substrate to inject to be formed.
8. the groove power MOSFET as described in claim any in claim 1 to 7, it is characterised in that: the trench gate function
Rate MOSFET is N-type device, and the first conduction type is N-type, and the second conduction type is p-type；Alternatively, the groove power
MOSFET is P-type device, and the first conduction type is p-type, and the second conduction type is N-type.
9. a kind of manufacturing method of groove power MOSFET, which comprises the steps of:
Step 1: providing the first epitaxial layer of the first conduction type, multiple trench gates are formed in first epitaxial layer, including
As follows step by step:
Step 11 forms multiple gate trench in first epitaxial layer；
Step 12 forms gate dielectric layer in the bottom surface of the gate trench and side；
Step 13 fills polysilicon formation polysilicon gate in the gate trench for being formed with the gate dielectric layer；The ditch
Slot grid include the structure being made of the gate trench, the gate dielectric layer and the polysilicon gate；
Step 2: the trap for carrying out the second conduction type is infused in formation body area in first epitaxial layer, the polysilicon gate
Depth is greater than the junction depth in the body area, is used to form channel by the surface that the polysilicon gate side covers the body area；
Step 3: the source for carrying out the first conduction type heavy doping is infused in the top surface in the body area and forms source region；
Step 4: forming interlayer film, contact hole and front metal layer, the contact hole passes through interlayer film, to the front metal
Layer is patterned to form grid and source electrode；
Groove power MOSFET includes multiple MOSFET cellular constructions and at least one SBR cellular construction, each MOSFET
Cellular construction and the SBR cellular construction are in parallel；
The top of the polysilicon gate of the MOSFET cellular construction is connected to the grid by contact hole, the source region and
The top in the body area is connected to the source electrode by contact hole；
The polysilicon gate, the source region and the top in the body area of the SBR cellular construction are connected to institute by contact hole
State source electrode；
Step 5: forming the drain region being made of the first conduction type heavily doped region at the back side of first epitaxial layer；By being located at
First epitaxial layer between the body area and the drain region forms drift region；
Step 6: forming metal layer on back at the back side in the drain region and forming drain electrode, the drain electrode by the metal layer on back
It is shared for the MOSFET cellular construction and the SBR cellular construction.
10. the manufacturing method of groove power MOSFET as claimed in claim 9, it is characterised in that: the groove power
In MOSFET, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of 1:1；
Alternatively, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of N:1, N is greater than 1
Integer, the N in the region alternately arranged direction Shang Ge it is identical or variation；
Alternatively, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of 1:N, N is greater than 1
Integer, the N in the region alternately arranged direction Shang Ge it is identical or variation；
Alternatively, the MOSFET cellular construction and the SBR cellular construction are alternately arranged according to the number ratio of M:N, N is greater than 1
Integer, M is integer greater than 1, and M and N are equal or unequal, and the N in the region alternately arranged direction Shang Ge is identical or variation,
M in the region alternately arranged direction Shang Ge is identical or changes.
11. the manufacturing method of groove power MOSFET as claimed in claim 9, it is characterised in that: first epitaxial layer
It is formed in semiconductor substrate surface.
12. the manufacturing method of groove power MOSFET as claimed in claim 11, it is characterised in that: the semiconductor substrate
For silicon substrate, first epitaxial layer is silicon epitaxy layer；
The gate dielectric layer is gate oxide, is formed using thermal oxidation technology.
13. the manufacturing method of groove power MOSFET as claimed in claim 9, it is characterised in that: each MOSFET is mono-
The gate trench of the trench gate of meta structure is connected and the institute of the trench gate of each MOSFET cellular construction
State polysilicon gate connection；
The ditch of the polysilicon gate of the trench gate of each SBR cellular construction and each MOSFET cellular construction
The polysilicon gate of slot grid is not connected to.
14. the manufacturing method of groove power MOSFET as described in claim 1, it is characterised in that: in the contact hole
It further include the bottom shape in the corresponding contact hole of the source region before after opening formation and filling metal in the opening
At the second conduction type heavy doping body draw-out area the step of, the corresponding contact hole of the source region passes through the body draw-out area
It is contacted with the body area.
15. the manufacturing method of groove power MOSFET as claimed in claim 11, it is characterised in that: the semiconductor substrate
With the first conduction type heavy doping, in step 5, the drain region is directly made of the semiconductor substrate after being thinned；
Alternatively, after the semiconductor substrate is thinned, passing through the semiconductor substrate after being thinned in step 5
The middle progress back side is injected to form the drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910089924.6A CN109817720A (en) | 2019-01-30 | 2019-01-30 | Groove power MOSFET and manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910089924.6A CN109817720A (en) | 2019-01-30 | 2019-01-30 | Groove power MOSFET and manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109817720A true CN109817720A (en) | 2019-05-28 |
Family
ID=66605926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910089924.6A Pending CN109817720A (en) | 2019-01-30 | 2019-01-30 | Groove power MOSFET and manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109817720A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113314592A (en) * | 2021-05-28 | 2021-08-27 | 滁州华瑞微电子科技有限公司 | SBR (styrene butadiene rubber) -integrated low-loss high-voltage super junction device and preparation method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080012050A1 (en) * | 2006-07-14 | 2008-01-17 | Denso Corporation | Semiconductor device |
| US20110278642A1 (en) * | 2010-05-13 | 2011-11-17 | Great Power Semiconductor Corp. | Power semiconductor structure with field effect rectifier and fabrication method thereof |
| US20150349112A1 (en) * | 2014-05-30 | 2015-12-03 | Texas Instruments Incorporated | Trench mosfet having reduced gate charge |
| CN105957892A (en) * | 2016-04-29 | 2016-09-21 | 深圳尚阳通科技有限公司 | Shield grid power device and manufacture method thereof |
| US9576841B2 (en) * | 2011-06-08 | 2017-02-21 | Rohm Co., Ltd. | Semiconductor device and manufacturing method |
| CN107799601A (en) * | 2017-09-29 | 2018-03-13 | 上海华虹宏力半导体制造有限公司 | Shield grid groove power MOSTET devices and its manufacture method |
-
2019
- 2019-01-30 CN CN201910089924.6A patent/CN109817720A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080012050A1 (en) * | 2006-07-14 | 2008-01-17 | Denso Corporation | Semiconductor device |
| US20110278642A1 (en) * | 2010-05-13 | 2011-11-17 | Great Power Semiconductor Corp. | Power semiconductor structure with field effect rectifier and fabrication method thereof |
| US9576841B2 (en) * | 2011-06-08 | 2017-02-21 | Rohm Co., Ltd. | Semiconductor device and manufacturing method |
| US20150349112A1 (en) * | 2014-05-30 | 2015-12-03 | Texas Instruments Incorporated | Trench mosfet having reduced gate charge |
| CN105957892A (en) * | 2016-04-29 | 2016-09-21 | 深圳尚阳通科技有限公司 | Shield grid power device and manufacture method thereof |
| CN107799601A (en) * | 2017-09-29 | 2018-03-13 | 上海华虹宏力半导体制造有限公司 | Shield grid groove power MOSTET devices and its manufacture method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113314592A (en) * | 2021-05-28 | 2021-08-27 | 滁州华瑞微电子科技有限公司 | SBR (styrene butadiene rubber) -integrated low-loss high-voltage super junction device and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI675477B (en) | Scalable SGT structure with improved FOM | |
| CN103579345B (en) | High-voltage field budget metals oxide field-effect transistor | |
| TWI469347B (en) | Configurations and methods for manufacturing devices with trench-oxide-nano-tube super-junctions | |
| KR101279574B1 (en) | High voltage semiconductor device and method of fabricating the same | |
| CN107316899B (en) | Semi-super junction device and manufacturing method thereof | |
| CN105742346B (en) | Double division trench gate charge storage type RC-IGBT and its manufacturing method | |
| CN109830532A (en) | Superjunction IGBT device and its manufacturing method | |
| CN105206660A (en) | Nano Mosfet With Trench Bottom Oxide Shielded And Third Dimensional P-Body Contact | |
| CN104201206A (en) | Horizontal SOI power LDMOS (lateral double-diffusion metal oxide semiconductor) device | |
| CN104425582B (en) | Semiconductor device | |
| CN108122975A (en) | Superjunction devices | |
| CN103137661B (en) | Lateral double-diffused metal-oxide semiconductor device and its manufacture method | |
| CN113990757B (en) | MOS device structure and manufacturing method | |
| CN102184856A (en) | Method for manufacturing groove type longitudinal semiconductor device | |
| CN103730501A (en) | Dielectrically-terminated superjunction FET | |
| CN107768442A (en) | Superjunction devices and its manufacture method | |
| CN109119463A (en) | A kind of lateral trench type MOSFET element and preparation method thereof | |
| CN106129117A (en) | A kind of lateral double-diffused metallic oxide semiconductor tube of high reliability | |
| CN103474463B (en) | There is the MOSFET in the induction net charge district in thick bottom insulator | |
| CN105993076A (en) | Bi-directional MOS device and manufacturing method thereof | |
| CN108598166A (en) | The enhanced integrated power device of depletion type based on superjunction self-isolation and manufacturing method | |
| CN105932064B (en) | Groove power MOSFET and manufacturing method | |
| CN108074963B (en) | Super junction device and manufacturing method thereof | |
| CN117497600B (en) | Structure, manufacturing method and electronic equipment of super-junction silicon carbide transistor | |
| CN117476774B (en) | Structure, manufacturing method and electronic equipment of vertical silicon carbide transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190528 |