CN109148585B - Trench MOSFET and method of manufacturing the same - Google Patents

Trench MOSFET and method of manufacturing the same Download PDF

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Publication number
CN109148585B
CN109148585B CN201810920140.9A CN201810920140A CN109148585B CN 109148585 B CN109148585 B CN 109148585B CN 201810920140 A CN201810920140 A CN 201810920140A CN 109148585 B CN109148585 B CN 109148585B
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layer
contact hole
opening
trench
groove
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CN109148585A (en
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范让萱
缪进征
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Abstract

The invention discloses a trench MOSFET, which consists of a plurality of device unit structures, wherein a trench of a trench gate is defined by a hard mask layer, the self-alignment definition of a first contact hole penetrating through a source region between the trenches can be realized by transversely etching the hard mask layer after the trench is etched, and the self-alignment definition of the first contact hole is realized by etching the hard mask layer and a gate oxide layer which take a polysilicon gate as masks after polysilicon is filled in the trench, etching silicon which takes the gate oxide layer as masks and forming self-aligned metal silicide which takes the gate oxide layer as masks. The invention also discloses a manufacturing method of the trench MOSFET. The invention can define the contact hole passing through the source region between the trench gates in a self-alignment way, can reduce the size of the device, increases the channel density and reduces the on-resistance.

Description

Trench MOSFET and method of manufacturing the same
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench MOSFET. The invention also relates to a manufacturing method of the trench MOSFET.
Background
In a semiconductor integrated circuit, a trench MOSFET structure with a smaller cell size, which is currently common, is shown in fig. 1, and is generally used in a cell size design of 1.0 micron to 1.8 microns. A semiconductor epitaxial layer such as a silicon epitaxial layer 102 is formed on a semiconductor substrate such as a silicon substrate 101, and a body region (body)105 and a source region 106 are sequentially formed on the surface of the semiconductor epitaxial layer 102; a plurality of gate trenches are formed in the semiconductor epitaxial layer 102, gate dielectric layers such as a gate oxide layer 103 are formed on the bottom surface and the side surface of the gate trenches, and polysilicon gates 104 are filled in the gate trenches formed with the gate dielectric layers 103.
An interlayer film 107 is formed on the surface of the semiconductor epitaxial layer 102, and a contact hole 109 is connected to the source region 106 or the polysilicon gate 104 at the bottom through the interlayer film 107. A body region extraction region 108 is also formed at the bottom of the contact hole 109 corresponding to the source region 106. Only through the contact hole 109 at the top of the polysilicon gate outside the device region, the polysilicon gate corresponding to the contact hole 109 is marked by 104a, the gate dielectric layer is marked by 103a, and the polysilicon gate 104a is connected with the polysilicon gate 104 in the device region.
A front metal layer 110 is formed on the surface of the interlayer film 107, and the front metal layer 110 is patterned to form a source electrode and a gate electrode. Wherein the gate is connected to the polysilicon gate 104a outside the device region through the contact hole 109 and connected to the polysilicon gate 104 in the device region through the polysilicon gate 104; the source is connected to the source region 106 at the bottom and the body region extraction region 108 through the contact hole 109, and the body region extraction region 108 is connected to the body region 05.
In order to further improve the channel density and reduce the on-resistance (Rdon) of the device, the simplest method is to further reduce the size design of the unit cell; in the process of reducing the design size, the groove further reduces the size, the equipment (cost) and the difficulty of the grid forming process are increased, and the like, and the factors basically reach the limit, but the simple reduction of the cell size needs to reduce the distance from the contact hole to the groove, the existing method has the problems that a grid source short circuit device fails due to insufficient registration precision between the contact hole and the grid groove, the uniformity of the channel opening voltage is poor due to the large difference of the channel doping concentration influenced by the injection of the contact hole, and the like, and the method cannot be produced in large quantities. The concrete description is as follows: in the prior art, the contact hole 109 is defined by using a photolithography process, that is, the size and the position of the contact hole 109 are defined by using the photolithography process, and the gate trench and the gate lead-out trench are also defined by using the photolithography process, because the photolithography process has certain accuracy limitation, the positions and the widths of the contact hole 109 and the gate trench and the gate lead-out trench have deviation within the accuracy range of the photolithography process, and the deviation caused by the accuracy of the photolithography process causes that the register redundancy between the contact hole 109 and the bottom trench, such as the gate trench and the gate lead-out trench, needs to be considered when manufacturing the trench gate power transistor, and the gap between the contact hole 109 and the trench needs to be large enough to prevent the problems of threshold voltage, i.e., channel turn-on voltage drift, and the like caused by the exposure cover deviation of the contact hole 109. This limits the potential for reducing on-resistance by increasing channel density by reducing the mesa size between the gate trenches. That is, the pitch between the gate trenches in the prior art has a limit value related to the photolithography process, and cannot be further reduced, so that the on-resistance cannot be further reduced by increasing the channel density by reducing the pitch between the gate trenches.
Disclosure of Invention
The invention provides a trench MOSFET, which can define a contact hole penetrating through a source region in a self-alignment manner between trench gates, reduce the size of a device, increase the channel density and reduce the on-resistance. Therefore, the invention also provides a manufacturing method of the trench MOSFET.
In order to solve the technical problem, the trench MOSFET provided by the invention is composed of a plurality of device unit structures;
each of the device unit structures includes:
the trench gate comprises a trench, gate oxide layers formed on the side surfaces and the bottom surface of the trench and a polysilicon gate filled in the trench;
the groove is formed on a silicon substrate, a body region doped with a second conduction type is formed on the silicon substrate, the groove penetrates through the body region, and a source region heavily doped with a first conduction type is formed on the surface of the body region.
The arrangement structure of each device unit structure in the trench MOSFET is as follows:
the trench gates are arranged in parallel, the source region and the body region between every two adjacent trench gates are shared, a first contact hole is formed between every two adjacent trench gates, and the first contact hole penetrates through the corresponding source region and the corresponding body region.
The first contact hole has a self-aligned structure as follows:
the groove is defined by a hard mask layer formed on the surface of the silicon substrate, a forming area of the groove is defined by a first opening formed by opening the hard mask layer, after the groove is formed, the hard mask layer is transversely etched to enable the first opening to be expanded to form a second opening which is larger than the width of the groove, and the gate oxide layer and the polysilicon gate are formed in the groove and the second opening;
under the self-alignment definition of the polysilicon gate, removing the hard mask layer and the gate oxide layer between the second openings and forming a third opening, wherein the surface of the silicon substrate is exposed by the third opening;
performing comprehensive silicon etching by taking the gate oxide layer as a mask to form a fourth opening corresponding to the first contact hole at the bottom of the third opening and simultaneously etching the polysilicon gate back to a position below the top surface of the groove and above the bottom surface of the source region;
and completely filling metal silicide in the fourth opening by taking the gate oxide layer as a mask in a self-alignment manner to form the first contact hole and simultaneously forming the metal silicide on the surface of the polysilicon gate.
And filling an interlayer film in the groove at the top of the polysilicon gate, wherein the interlayer film is positioned in the groove in a self-alignment manner through a back-etching process taking the surface of the silicon substrate outside the groove as a stop layer and is level with the surface of the silicon substrate outside the groove, and the gate oxide layer remained outside the groove is also removed through the back-etching process of the interlayer film.
The trenches of the device cell structures are connected together and the polysilicon gates are connected together, and a second contact hole is formed at the top of the polysilicon gate of the selected device cell structure, the second contact hole penetrating through the interlayer film.
The pattern structure of the front metal layer forms a grid electrode and a source electrode, the front metal layer corresponding to the grid electrode covers the surface of the interlayer film corresponding to the second contact hole and is connected with the polysilicon gate through the second contact hole, the front metal layer corresponding to the source electrode covers the source region, the interlayer film and the surface of the first contact hole outside the grid electrode, a gap is formed between the front metal layer corresponding to the source electrode and the front metal layer corresponding to the grid electrode, and the source electrode is connected with the source region and the body region through the first contact hole.
In a further improvement, a drain region heavily doped with the first conductivity type is formed on the back surface of the silicon substrate, and the silicon substrate between the drain region and the body region forms a drift region.
And a drain electrode consisting of a back metal layer is formed on the back surface of the drain region.
In a further improvement, a silicon epitaxial layer of the first conductivity type is formed on the surface of the silicon substrate, and the body region, the source region and the drift region are all formed in the silicon epitaxial layer.
In a further improvement, the metal silicide is titanium silicide or cobalt silicide.
In a further improvement, the hard mask layer is made of an oxide layer.
In a further improvement, the second contact hole is filled with a tungsten layer.
In a further improvement, a barrier layer and an adhesion layer are formed between the tungsten layer and the silicon of the second contact hole.
In order to solve the above technical problem, the method for manufacturing a trench MOSFET provided by the present invention comprises the following steps:
step one, forming a body region doped with a second conduction type on a silicon substrate, and forming a source region heavily doped with a first conduction type on the surface of the body region.
And secondly, forming a hard mask layer on the surface of the silicon substrate with the active region.
And step three, carrying out photoetching to form a first opening in the hard mask layer, wherein the first opening defines a forming area of the groove.
Etching the silicon substrate by taking the hard mask layer as a mask and forming the groove at the bottom of the first opening; the trench passes through the body region.
The trench MOSFET is comprised of a plurality of device cell structures, each of which includes the trench.
The trenches are arranged in parallel, and the source region and the body region between two adjacent trenches are shared.
And fifthly, performing transverse etching on the hard mask layer to enable the first opening to be expanded to form a second opening which is larger than the width of the groove.
And step six, forming a gate oxide layer, wherein the gate oxide layer is positioned on the inner side surface of the groove and extends to the surface of the silicon substrate at the bottom of the second opening outside the groove.
And seventhly, forming a polysilicon gate by adopting polysilicon deposition and a chemical mechanical polishing process with the hard mask layer as a stop layer, wherein the polysilicon gate is filled in the groove and the second opening.
And step eight, removing the hard mask layer and the gate oxide layer between the second openings by taking the polysilicon gate as a self-aligned mask, and forming a third opening, wherein the surface of the silicon substrate is exposed by the third opening.
Ninthly, performing comprehensive silicon etching by taking the gate oxide layer as a mask to form a fourth opening at the bottom of the third opening and simultaneously etching the polysilicon gate back to a position below the top surface of the groove and above the bottom surface of the source region; the fourth opening penetrates through the corresponding source region.
And step ten, completely filling metal silicide in the fourth opening by taking the gate oxide layer as a mask in a self-alignment manner to form the first contact hole and simultaneously forming the metal silicide on the surface of the polysilicon gate.
Step eleven, depositing to form an interlayer film; and carrying out back etching on the interlayer film by taking the surface of the silicon substrate outside the groove as a stop layer, wherein the interlayer film after back etching is self-aligned and positioned in the groove and is level to the surface of the silicon substrate outside the groove, and the residual gate oxide outside the groove is also removed by the back etching process of the interlayer film.
Step twelve, the trenches of the device unit structures are communicated together and the polysilicon gates are connected together, and a second contact hole is formed at the top of the polysilicon gate of the selected device unit structure and penetrates through the interlayer film.
And thirteen, forming a front metal layer, patterning the front metal layer by adopting a photoetching process to form a grid electrode and a source electrode, wherein the front metal layer corresponding to the grid electrode covers the surface of the interlayer film corresponding to the second contact hole and is connected with the polysilicon gate through the second contact hole, the front metal layer corresponding to the source electrode covers the source region, the interlayer film and the surface of the first contact hole except the grid electrode, a gap is formed between the front metal layer corresponding to the source electrode and the front metal layer corresponding to the grid electrode, and the source electrode is connected with the source region and the body region through the first contact hole.
In a further improvement, after the patterning process of the front metal layer is completed, the method further comprises a back process:
and forming a drain region with a heavily doped first conductivity type on the back surface of the silicon substrate, wherein the silicon substrate between the drain region and the body region forms a drift region.
And forming a back metal layer on the back of the drain region and forming the drain electrode by the back metal layer.
In a further improvement, a silicon epitaxial layer of the first conductivity type is formed on the surface of the silicon substrate, and the body region, the source region and the drift region are all formed in the silicon epitaxial layer.
In a further improvement, the process for forming the metal silicide comprises the following sub-steps:
step 10a, forming a metal layer corresponding to the metal silicide;
step 10b, carrying out silicification reaction on the metal, forming the metal silicide in a self-alignment manner at the contact position of the metal layer and the silicon, and keeping the metal layer in contact with the gate oxide layer unchanged;
and 10c, removing the metal layer contacted with the gate oxide layer.
The further improvement is that the metal material corresponding to the metal silicide is titanium or cobalt, and the metal silicide is titanium silicide or cobalt silicide.
In a further improvement, the hard mask layer is made of an oxide layer.
The further improvement is that the step twelve comprises the following sub-steps:
step 12a, forming a fifth opening in the forming area of the second contact hole by adopting a photoetching process;
and step 12b, performing tungsten deposition and tungsten back etching to fill tungsten in the fifth opening and form the second contact hole.
A further improvement is to include the step of forming a barrier layer and an adhesion layer prior to performing the tungsten deposition of step 12 b.
The method comprises the steps that a hard mask layer for defining a groove is utilized to define a contact hole which penetrates through a source region, namely a first contact hole, in a self-alignment mode between the grooves, the first opening of the hard mask layer for defining the groove is enlarged to form a second opening, and after a gate oxide layer and a polysilicon gate are formed in the groove and the second opening, the hard mask layer and the gate oxide layer between the second openings can be used as masks through the polysilicon gate in the second opening and are removed in the self-alignment mode, so that a third opening which opens the region of the first contact hole is formed; then, a fourth opening corresponding to the first contact hole can be formed at the bottom of the third opening by taking the gate oxide layer as a mask to carry out comprehensive silicon etching, the polysilicon gate is etched back to the surface lower than the top of the groove, and then the gate oxide layer is still taken as the mask to be capable of self-aligning to completely fill metal silicide in the fourth opening to form the first contact hole and simultaneously form metal silicide on the surface of the polysilicon gate; and an interlayer film can be filled in the groove at the top of the polysilicon gate by deposition and etching back, so that a contact hole penetrating through a source region can be completely defined in a self-alignment manner between groove gates, and finally, the size of the device can be reduced, the channel density can be increased, and the on-resistance can be reduced.
In addition, because the first contact hole does not need to be defined by photoetching, a layer of photomask can be saved, and the process cost can be reduced.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a prior art trench MOSFET structure;
FIG. 2 is a schematic structural diagram of a trench MOSFET in accordance with an embodiment of the present invention;
fig. 3A-3W are schematic views of device structures at various steps of a method for manufacturing a trench MOSFET according to an embodiment of the present invention.
Detailed Description
Fig. 2 is a schematic structural diagram of a trench MOSFET according to an embodiment of the present invention; the trench MOSFET in the embodiment of the invention is composed of a plurality of device unit structures;
each of the device unit structures includes:
the trench gate comprises a trench 302, a gate oxide layer 4 formed on the side surface and the bottom surface of the trench 302 and a polysilicon gate 5 filled in the trench 302; the trench 302 is shown in FIG. 3G.
The trench 302 is formed on a silicon substrate 1, a body region 2 doped with a second conductivity type is formed on the silicon substrate 1, the trench 302 penetrates through the body region 2, and a source region 3 heavily doped with a first conductivity type is formed on the surface of the body region 2.
The arrangement structure of each device unit structure in the trench MOSFET is as follows:
the trench gates are arranged in parallel, the source region 3 and the body region 2 between two adjacent trench gates are shared, a first contact hole 6a is formed between two adjacent trench gates, and the first contact hole 6a penetrates through the corresponding source region 3 and the corresponding body region 2.
The first contact hole 6a has a self-aligned structure of:
the trench 302 is defined by a hard mask layer 202 formed on the surface of the silicon substrate 1, a first opening 301 formed by opening the hard mask layer 202 defines a formation region of the trench 302, after the trench 302 is formed, the hard mask layer 202 is laterally etched to expand the first opening 301 to form a second opening 303 larger than the width of the trench 302, and the gate oxide layer 4 and the polysilicon gate 5 are formed in the trench 302 and the second opening 303. Fig. 3F shows the first opening 301, and fig. 3H shows the second opening 303.
The hard mask layer 202 and the gate oxide layer 4 between the second openings 303 under the self-aligned definition of the polysilicon gate 5 are removed and a third opening 304 is formed, wherein the third opening 304 exposes the surface of the silicon substrate 1. The third opening 304 is shown with reference to fig. 3L.
Performing overall silicon etching by using the gate oxide layer 4 as a mask to form a fourth opening 305 corresponding to the first contact hole 6a at the bottom of the third opening 304 and etch back the polysilicon gate 5 to a position below the top surface of the trench 302 and above the bottom surface of the source region 3; the fourth opening 305 is shown in fig. 3M.
And completely filling metal silicide 6a in the fourth opening 305 by taking the gate oxide layer 4 as a mask in a self-alignment manner to form the first contact hole 6a and simultaneously forming metal silicide 6b on the surface of the polysilicon gate 5. In fig. 2, the metal silicide filled in the fourth opening 305 and the first contact hole are both denoted by reference numeral 6 a.
An interlayer film 7 is filled in the groove 302 at the top of the polysilicon gate 5, the interlayer film 7 is self-aligned in the groove 302 and is level with the surface of the silicon substrate 1 outside the groove 302 through a back etching process taking the surface of the silicon substrate 1 outside the groove 302 as a stop layer, and the residual gate oxide layer 4 outside the groove 302 is also removed through the back etching process of the interlayer film 7.
The trenches 302 of the device unit structures are communicated together and the polysilicon gates 5 are connected together, and a second contact hole 9 is formed at the top of the polysilicon gate 5 of the selected device unit structure, wherein the second contact hole 9 penetrates through the interlayer film 7.
The pattern structure of the front metal layer 10 forms a gate and a source, the front metal layer 10 corresponding to the gate covers the surface of the interlayer film 7 corresponding to the second contact hole 9 and is connected with the polysilicon gate 5 through the second contact hole 9, the front metal layer 10 corresponding to the source covers the source region 3 outside the gate, the interlayer film 7 and the surface of the first contact hole 6a, a gap is formed between the front metal layer 10 corresponding to the source and the front metal layer 10 corresponding to the gate, and the source is connected with the source region 3 and the body region 2 through the first contact hole 6 a.
A drain region with a heavy doping of the first conductivity type is formed on the back surface of the silicon substrate 1, and the silicon substrate 1 between the drain region and the body region 2 forms a drift region.
A drain electrode composed of a back metal layer 11 is formed on the back surface of the drain region.
In the embodiment of the present invention, a silicon epitaxial layer of a first conductivity type is formed on the surface of the silicon substrate 1, and the body region 2, the source region 3, and the drift region are all formed in the silicon epitaxial layer.
The metal silicides 6a and 6b are titanium silicide or cobalt silicide.
The hard mask layer 202 is made of an oxide layer.
The second contact hole 9 is filled with a tungsten layer 9. In the embodiment of the present invention, the second contact hole and the tungsten layer are both denoted by reference numeral 9, and the tungsten layer 9 is usually formed by a tungsten deposition and tungsten etching process, so that the tungsten layer 9 is completely located in the fifth opening 306 corresponding to the second contact hole 9.
A barrier layer and an adhesive layer 8 are formed between the tungsten layer 9 and the silicon of the second contact hole 9, the barrier layer and the adhesive layer 8 are optional structures, and the barrier layer and the adhesive layer 8 are not formed, and the barrier layer and the adhesive layer 8 are not shown in fig. 2.
In the embodiment of the invention, the trench MOSFET is an N-type device, the first conduction type is an N-type device, and the second conduction type is a P-type device; in other embodiments can also be: the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
In the embodiment of the invention, the hard mask layer 202 defining the trench 302 is used for self-aligning and defining the contact hole passing through the source region 3, namely the first contact hole 6a, between the trenches 302, mainly by expanding the first opening 301 of the hard mask layer 202 defining the trench 302 and forming the second opening 303, after the gate oxide layer 4 and the polysilicon gate 5 are formed in the trench 302 and the second opening 303, the hard mask layer 202 and the gate oxide layer 4 between the second openings 303 can be masked by the polysilicon gate 5 in the second opening 303 and removed in a self-aligning manner, so that the third opening 304 for opening the region of the first contact hole 6a is formed; then, a fourth opening 305 corresponding to the first contact hole 6a can be formed at the bottom of the third opening 304 and the polysilicon gate 5 can be etched back to be lower than the top surface of the trench 302 by performing overall silicon etching with the gate oxide layer 4 as a mask, and then the gate oxide layer 4 is still used as a mask to be capable of self-aligning and completely filling metal silicide in the fourth opening 305 to form the first contact hole 6a and simultaneously form metal silicide on the surface of the polysilicon gate 5; and the interlayer film 7 can be filled in the groove 302 at the top of the polysilicon gate 5 only by deposition and etching back, so that the contact hole penetrating through the source region 3 can be completely defined in a self-alignment way between the groove gates, and finally, the size of the device can be reduced, the channel density can be increased, and the on-resistance can be reduced.
In addition, as the first contact hole 6a in the embodiment of the invention does not need to be defined by photoetching, a layer of photomask can be saved, and the process cost can be reduced.
As shown in fig. 3A to 3W, which are schematic views of device structures in the steps of the method for manufacturing a trench MOSFET according to the embodiment of the present invention, the method for manufacturing a trench MOSFET according to the embodiment of the present invention includes the following steps:
step one, a body region 2 doped with a second conduction type is formed on a silicon substrate 1, and a source region 3 heavily doped with a first conduction type is formed on the surface of the body region 2. The method comprises the following steps:
as shown in fig. 3A, a Screen Oxide layer (Screen Oxide)201 is formed on the surface of the silicon substrate 1.
As shown in fig. 3B, a global body region ion implantation is performed and an annealing process is performed to form the body region 2.
As shown in fig. 3C, the source region 3 is formed by performing a global source ion implantation or performing a source ion implantation in a selected region by using a photolithographic definition.
Step two, as shown in fig. 3D, a hard mask layer 202 is formed on the surface of the silicon substrate 1 where the active region 3 is formed.
The hard mask layer 202 is made of an oxide layer.
Step three, as shown in fig. 3E, performing a photolithography process to form a photoresist pattern 203; as shown in fig. 3F, a first opening 301 is formed in the hard mask layer 202 by etching using the photoresist pattern 203 as a mask, and the first opening 301 defines a formation region of a trench 302. The photoresist pattern 203 is then removed.
Step four, as shown in fig. 3G, etching the silicon substrate 1 by using the hard mask layer 202 as a mask, and forming the trench 302 at the bottom of the first opening 301; the trench 302 passes through the body region 2.
A trench MOSFET is comprised of a plurality of device cell structures, each of which includes the trench 302.
The trenches 302 are arranged in parallel, and the source region 3 and the body region 2 between two adjacent trenches 302 are shared.
Step five, as shown in fig. 3H, the hard mask layer 202 is laterally etched to enlarge the first opening 301 to form a second opening 303 larger than the width of the trench 302.
Sixthly, as shown in fig. 3I, forming a gate oxide layer 4, wherein the gate oxide layer 4 is located on the inner side surface of the trench 302 and extends to the surface of the silicon substrate 1 at the bottom of the second opening 303 outside the trench 302.
Step seven, as shown in fig. 3J, a polysilicon layer 5a is formed by polysilicon deposition.
As shown in fig. 3K, a polysilicon gate 5 is formed by performing a chemical mechanical polishing process using the hard mask layer 202 as a stop layer, and the polysilicon gate 5 is filled in the trench 302 and the second opening 303.
Step eight, as shown in fig. 3L, removing the hard mask layer 202 and the gate oxide layer 4 between the second openings 303 with the polysilicon gate 5 as a self-aligned mask, and forming third openings 304, where the third openings 304 expose the surface of the silicon substrate 1.
Ninthly, as shown in fig. 3M, performing overall silicon etching by using the gate oxide layer 4 as a mask to form a fourth opening 305 at the bottom of the third opening 304 and etching the polysilicon gate 5 back to a position below the top surface of the trench 302 and above the bottom surface of the source region 3; the fourth opening 305 passes through the corresponding source region 3, and the bottom of the fourth opening 305 enters the body region 2.
Step ten, as shown in fig. 3O, completely filling metal silicide 6a in the fourth opening 305 by taking the gate oxide layer 4 as a mask in a self-alignment manner to form the first contact hole 6a and simultaneously forming metal silicide 6b on the surface of the polysilicon gate 5.
The forming process of the metal silicide comprises the following sub-steps:
step 10a, as shown in fig. 3N, forming a metal layer 6 corresponding to the metal silicide; the metal material corresponding to the metal silicide is titanium or cobalt, and the metal silicide is titanium silicide or cobalt silicide.
And step 10b, as shown in fig. 3N, performing a silicification reaction on the metal, forming the metal silicide in a self-aligned manner at a position where the metal layer is contacted with the silicon, and keeping the metal layer contacted with the gate oxide layer 4 unchanged.
Step 10c, as shown in fig. 3O, removes the metal layer 6 in contact with the gate oxide layer 4, thereby forming metal silicides 6a and 6 b.
Step eleven, as shown in fig. 3P, the interlayer film 7 is deposited.
As shown in fig. 3Q, the surface of the silicon substrate 1 outside the trench 302 is used as a stop layer to perform the etching back of the interlayer film 7, the interlayer film 7 after the etching back is self-aligned and located in the trench 302 and is level with the surface of the silicon substrate 1 outside the trench 302, and the gate oxide layer 4 remaining outside the trench 302 is also removed by the etching back process of the interlayer film 7. The etch-back process of the interlayer film 7 includes etching and chemical mechanical polishing processes.
Step twelve, the trenches 302 of the device unit structures are communicated together, and the polysilicon gates 5 are connected together, and a second contact hole 9 is formed at the top of the polysilicon gate 5 of the selected device unit structure, wherein the second contact hole 9 penetrates through the interlayer film 7.
The twelfth step comprises the following sub-steps:
in step 12a, as shown in fig. 3R, a photoresist pattern 204 is formed using a photolithography process.
Etching by using the photoresist pattern 204 as a mask to form a fifth opening 306 in the formation region of the second contact hole 9;
as shown in fig. 3S, the photoresist pattern 204 is removed.
Step 12b, as shown in fig. 3V, performing tungsten deposition and tungsten etching back to fill tungsten in the fifth opening 306 and form the second contact hole 9.
In other embodiments, the following steps can also be included:
as shown in fig. 3T, a step of forming a barrier layer and an adhesion layer 8. The barrier layer and the adhesion layer 8 are for example a stack of Ti and TiN.
As shown in fig. 3U, tungsten deposition and tungsten etching back are performed to fill tungsten in the fifth opening 306 and form the second contact hole 9.
Step thirteen, as shown in fig. 3V, a front metal layer 10 is formed.
As shown in fig. 3W, a photoresist pattern 205 is formed using a photolithography process.
Patterning the front metal layer 10 by using an etching process with the photoresist pattern 205 as a mask to form a gate and a source, wherein the front metal layer 10 corresponding to the gate covers the surface of the interlayer film 7 corresponding to the second contact hole 9 and is connected with the polysilicon gate 5 through the second contact hole 9, the front metal layer 10 corresponding to the source covers the source region 3, the interlayer film 7 and the surface of the first contact hole 6a outside the gate, a gap is formed between the front metal layer 10 corresponding to the source and the front metal layer 10 corresponding to the gate, and the source is connected with the source region 3 and the body region 2 through the first contact hole 6 a.
After the patterning process of the front metal layer 10 is completed, the method further includes the following back process:
as shown in fig. 2, a drain region heavily doped with the first conductivity type is formed at the back surface of the silicon substrate 1, and the silicon substrate 1 between the drain region and the body region 2 constitutes a drift region.
And forming a back metal layer 11 on the back of the drain region and forming a drain electrode by the back metal layer 11.
In the method of the embodiment of the present invention, a silicon epitaxial layer of a first conductivity type is formed on the surface of the silicon substrate 1, and the body region 2, the source region 3 and the drift region are all formed in the silicon epitaxial layer.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A trench MOSFET, comprising: the trench MOSFET is composed of a plurality of device unit structures;
each of the device unit structures includes:
the trench gate comprises a trench, gate oxide layers formed on the side surfaces and the bottom surface of the trench and a polysilicon gate filled in the trench;
the groove is formed on a silicon substrate, a body region doped with a second conduction type is formed on the silicon substrate, the groove penetrates through the body region, and a source region heavily doped with a first conduction type is formed on the surface of the body region;
the arrangement structure of each device unit structure in the trench MOSFET is as follows:
the trench gates are arranged in parallel, the source region and the body region between every two adjacent trench gates are shared, a first contact hole is formed between every two adjacent trench gates, and the first contact hole penetrates through the corresponding source region and the corresponding body region;
the first contact hole has a self-aligned structure as follows:
the groove is defined by a hard mask layer formed on the surface of the silicon substrate, a forming area of the groove is defined by a first opening formed by opening the hard mask layer, after the groove is formed, the hard mask layer is transversely etched to enable the first opening to be expanded to form a second opening which is larger than the width of the groove, and the gate oxide layer and the polysilicon gate are formed in the groove and the second opening;
under the self-alignment definition of the polysilicon gate, removing the hard mask layer and the gate oxide layer between the second openings and forming a third opening, wherein the surface of the silicon substrate is exposed by the third opening;
performing comprehensive silicon etching by taking the gate oxide layer as a mask to form a fourth opening corresponding to the first contact hole at the bottom of the third opening and simultaneously etching the polysilicon gate back to a position below the top surface of the groove and above the bottom surface of the source region;
completely filling metal silicide in the fourth opening in a self-alignment mode by taking the gate oxide layer as a mask to form the first contact hole and simultaneously forming metal silicide on the surface of the polysilicon gate;
filling an interlayer film in the groove at the top of the polysilicon gate, wherein the interlayer film is self-aligned in the groove and is level with the surface of the silicon substrate outside the groove through a back etching process taking the surface of the silicon substrate outside the groove as a stop layer, and the rest gate oxide outside the groove is also removed through the back etching process of the interlayer film;
the trenches of the device unit structures are communicated together and the polysilicon gates are connected together, a second contact hole is formed at the top of the polysilicon gate of the selected device unit structure, and the second contact hole penetrates through the interlayer film;
the pattern structure of the front metal layer forms a grid electrode and a source electrode, the front metal layer corresponding to the grid electrode covers the surface of the interlayer film corresponding to the second contact hole and is connected with the polysilicon gate through the second contact hole, the front metal layer corresponding to the source electrode covers the source region, the interlayer film and the surface of the first contact hole outside the grid electrode, a gap is formed between the front metal layer corresponding to the source electrode and the front metal layer corresponding to the grid electrode, and the source electrode is connected with the source region and the body region through the first contact hole.
2. The trench MOSFET of claim 1 wherein: a drain region with a first conductive type heavy doping is formed on the back surface of the silicon substrate, and a drift region is formed between the drain region and the body region of the silicon substrate;
and a drain electrode consisting of a back metal layer is formed on the back surface of the drain region.
3. The trench MOSFET of claim 2 wherein: and a silicon epitaxial layer of a first conduction type is formed on the surface of the silicon substrate, and the body region, the source region and the drift region are formed in the silicon epitaxial layer.
4. The trench MOSFET of claim 1 wherein: the metal silicide is titanium silicide or cobalt silicide.
5. The trench MOSFET of claim 1 wherein: the hard mask layer is made of an oxide layer.
6. The trench MOSFET of claim 1 wherein: and a tungsten layer is filled in the second contact hole.
7. The trench MOSFET of claim 6 wherein: and a barrier layer and an adhesive layer are formed between the tungsten layer and the silicon of the second contact hole.
8. A method for manufacturing a trench MOSFET, comprising the steps of:
forming a body region doped with a second conduction type on a silicon substrate, and forming a source region heavily doped with a first conduction type on the surface of the body region;
secondly, forming a hard mask layer on the surface of the silicon substrate with the active region;
step three, photoetching is carried out to form a first opening in the hard mask layer, and the first opening defines a forming area of a groove;
etching the silicon substrate by taking the hard mask layer as a mask and forming the groove at the bottom of the first opening; the trench passes through the body region;
the trench MOSFET is composed of a plurality of device unit structures, and each device unit structure comprises the trench;
the trenches are arranged in parallel, and the source region and the body region between two adjacent trenches are shared;
fifthly, the hard mask layer is transversely etched to enable the first opening to be enlarged to form a second opening which is larger than the width of the groove;
step six, forming a gate oxide layer, wherein the gate oxide layer is positioned on the inner side surface of the groove and extends to the surface of the silicon substrate at the bottom of the second opening outside the groove;
step seven, forming a polysilicon gate by adopting polysilicon deposition and a chemical mechanical polishing process taking the hard mask layer as a stop layer, wherein the polysilicon gate is filled in the groove and the second opening;
eighthly, removing the hard mask layer and the gate oxide layer between the second openings by taking the polysilicon gate as a self-aligned mask, and forming a third opening, wherein the surface of the silicon substrate is exposed by the third opening;
ninthly, performing comprehensive silicon etching by taking the gate oxide layer as a mask to form a fourth opening at the bottom of the third opening and simultaneously etching the polysilicon gate back to a position below the top surface of the groove and above the bottom surface of the source region; the fourth opening penetrates through the corresponding source region;
step ten, completely filling metal silicide in the fourth opening by taking the gate oxide layer as a mask in a self-alignment manner to form a first contact hole and simultaneously forming metal silicide on the surface of the polysilicon gate;
step eleven, depositing to form an interlayer film; the silicon substrate surface outside the groove is used as a stop layer to carry out back etching of the interlayer film, the interlayer film after back etching is self-aligned and positioned in the groove and is level to the silicon substrate surface outside the groove, and the residual gate oxide layer outside the groove is also removed through the back etching process of the interlayer film;
twelfth, the grooves of the device unit structures are communicated together and the polysilicon gates are connected together, a second contact hole is formed at the top of the polysilicon gate of the selected device unit structure, and the second contact hole penetrates through the interlayer film;
and thirteen, forming a front metal layer, patterning the front metal layer by adopting a photoetching process to form a grid electrode and a source electrode, wherein the front metal layer corresponding to the grid electrode covers the surface of the interlayer film corresponding to the second contact hole and is connected with the polysilicon gate through the second contact hole, the front metal layer corresponding to the source electrode covers the source region, the interlayer film and the surface of the first contact hole except the grid electrode, a gap is formed between the front metal layer corresponding to the source electrode and the front metal layer corresponding to the grid electrode, and the source electrode is connected with the source region and the body region through the first contact hole.
9. The method of manufacturing a trench MOSFET of claim 8 wherein: after the patterning process of the front metal layer is finished, the method also comprises the following back process:
forming a drain region with a first conductive type heavy doping on the back surface of the silicon substrate, wherein a drift region is formed between the drain region and the body region of the silicon substrate;
and forming a back metal layer on the back of the drain region and forming the drain electrode by the back metal layer.
10. The method of manufacturing a trench MOSFET of claim 9 wherein: and a silicon epitaxial layer of a first conduction type is formed on the surface of the silicon substrate, and the body region, the source region and the drift region are formed in the silicon epitaxial layer.
11. The method of manufacturing a trench MOSFET of claim 8 wherein: the forming process of the metal silicide comprises the following sub-steps:
step 10a, forming a metal layer corresponding to the metal silicide;
step 10b, carrying out silicification reaction on the metal, forming the metal silicide in a self-alignment manner at the contact position of the metal layer and the silicon, and keeping the metal layer in contact with the gate oxide layer unchanged;
and 10c, removing the metal layer contacted with the gate oxide layer.
12. The method of manufacturing a trench MOSFET of claim 11 wherein: the metal material corresponding to the metal silicide is titanium or cobalt, and the metal silicide is titanium silicide or cobalt silicide.
13. The method of manufacturing a trench MOSFET of claim 8 wherein: the hard mask layer is made of an oxide layer.
14. The method of manufacturing a trench MOSFET of claim 8 wherein: the twelfth step comprises the following sub-steps:
step 12a, forming a fifth opening in the forming area of the second contact hole by adopting a photoetching process;
and step 12b, performing tungsten deposition and tungsten back etching to fill tungsten in the fifth opening and form the second contact hole.
15. The method of manufacturing a trench MOSFET of claim 14 wherein: a step of forming a barrier layer and an adhesion layer is also included prior to performing the tungsten deposition of step 12 b.
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