CN112397506A - Trench gate power device and manufacturing method thereof - Google Patents

Trench gate power device and manufacturing method thereof Download PDF

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Publication number
CN112397506A
CN112397506A CN201910742228.0A CN201910742228A CN112397506A CN 112397506 A CN112397506 A CN 112397506A CN 201910742228 A CN201910742228 A CN 201910742228A CN 112397506 A CN112397506 A CN 112397506A
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charge balance
trench
source
contact hole
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刘坚
肖胜安
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Nantong Shangyangtong Integrated Circuit Co ltd
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Nantong Shangyangtong Integrated Circuit Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Abstract

The invention discloses a trench gate power device.A charge balance trench is formed in a drift region between trench gates, and the depth of the charge balance trench is greater than that of a gate trench of the trench gates; forming a charge balance region at the bottom of the charge balance groove, wherein the charge balance region and the adjacent drift region are mutually depleted; forming an active region in a self-aligned manner in a surface region of the channel region outside the charge balance trench; and a source contact hole penetrating through the interlayer film is formed at the top of the source region, the opening transverse dimension of the source contact hole is larger than the transverse dimension of the charge balance groove, a source lead-out structure made of a conductive material is formed in the charge balance groove at the opening and the bottom of the source contact hole, the bottom of the source lead-out structure forms ohmic contact with the charge balance region, the channel region and the source region, and the top of the source lead-out structure is connected with a source electrode made of a front metal layer. The invention also discloses a manufacturing method of the trench gate power device. The invention can improve the breakdown voltage of the device with lower cost and simultaneously reduce the on-resistance of the device.

Description

Trench gate power device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench gate power device; the invention also relates to a manufacturing method of the trench gate power device.
Background
The conventional trench gate power device such as a trench gate power MOSFET device can increase the cell density of the device by reducing the width of the gate trench and the step size of the device, thereby reducing the channel resistance and reducing the on-resistance of the device. However, the resistance of the drift region of the device is still determined by the resistivity of the drift region, i.e. the impurity concentration, and higher breakdown voltage of the device requires higher resistivity of the drift region, thereby increasing the on-resistance of the device.
The prior art has the following problems:
the voltage bearing region of the device is mainly a drift region, the drift region is made of a single-conductivity-type semiconductor material, for example, for an NMOS (N-type metal oxide semiconductor), the drift region is made of an N-type semiconductor such as an N-type silicon epitaxial layer, the resistivity of the trench gate drift region is limited by the breakdown voltage of the device, and generally, the higher the breakdown voltage is, the higher the resistance of the drift region needs to be, so that the resistance of the drift region becomes higher.
The existing method for solving the problem that the resistance of the drift region becomes high is to adopt a super junction structure, that is, the drift region of the device is composed of P-type semiconductors and N-type semiconductors which are alternately arranged, and the limitation on the impurity concentration of the conducted drift region is removed through the charge balance of two different impurities, so that the limitation on the impurity concentration of the drift region is reduced or eliminated, but the formation of the original cell of the super junction structure device generally requires 7-8 times of photoetching or more times of photoetching, which results in the increase of the manufacturing cost. This is suitable for high voltage devices above 500V but is too costly for devices with breakdown voltages of 30-100V.
Disclosure of Invention
The invention aims to provide a trench gate power device, which can improve the breakdown voltage of the device and reduce the on-resistance of the device at the same time by adopting lower cost. Therefore, the invention also provides a manufacturing method of the trench gate power device.
In order to solve the technical problem, the trench gate power device provided by the invention is formed in a semiconductor substrate, and a current flowing area of the trench gate power device is formed by periodically arranging a plurality of original cells.
The drift region doped with the first conductive type is formed on the surface of the semiconductor substrate, and the trench gate of each primitive cell comprises a gate trench, a gate dielectric layer and a gate conductive material layer; the gate trenches are formed in the drift region, and a region between each adjacent gate trenches is a semiconductor platform region.
The gate dielectric layer is formed on the bottom surface and the side surface of the gate groove, and the gate conductive material layer is filled in the gate groove.
And a channel region doped with the second conductive type is formed in the drift region surface region of the semiconductor platform region in a self-alignment manner, the junction depth of the channel region is smaller than the depth of the gate groove, and the surface of the channel region covered by the side surface of the gate conductive material layer is used for forming a channel.
A charge balance trench is formed in the drift region of the semiconductor mesa region, the charge balance trench having a depth greater than a depth of the gate trench.
And a charge balance region consisting of a second conductive type doped region is formed in the drift region at the bottom of the charge balance groove in a self-alignment manner, and the charge balance region and the adjacent drift region are mutually depleted, so that the voltage endurance of the device can be improved, and the doping concentration of the drift region is improved, so that the on-resistance of the device is reduced.
And a source region with heavily doped first conductivity type is formed in the surface region of the channel region outside the charge balance groove in a self-alignment manner.
And a source contact hole penetrating through an interlayer film is formed at the top of the source region, the opening transverse dimension of the source contact hole is larger than the transverse dimension of the charge balance groove, the top of the charge balance groove is completely exposed, the opening of the source contact hole is communicated with the charge balance groove in the longitudinal direction, the bottom of the opening of the source contact hole penetrates through the source region in the longitudinal direction and exposes the surface of the channel region, a source leading-out structure composed of a conductive material is formed in the charge balance groove at the opening and the bottom of the source contact hole, the source leading-out structure and the charge balance region at the bottom, the channel region and the source region form ohmic contact, and the top of the source leading-out structure is connected with a source electrode composed of a front metal layer.
In a further improvement, the semiconductor substrate is a silicon substrate; the gate dielectric layer is a gate oxide layer; the grid conductive material layer is a polysilicon grid.
In a further improvement, the conductive material layer of the source lead-out structure comprises a second polysilicon layer, the second polysilicon layer is filled in the charge balance groove and extends into the opening of the source contact hole, and the second polysilicon layer and the charge balance area at the bottom, the channel area and the source area form ohmic contact.
The source contact hole is filled with a metal layer, the source contact hole is formed by the metal layer filled in the opening of the source contact hole at the top of the second polycrystalline silicon layer, and the source lead-out structure is formed by overlapping the second polycrystalline silicon layer and the source contact hole.
In a further improvement, the second polysilicon layer is heavily doped with the first conductivity type; or, the second polysilicon layer is heavily doped with the second conductive type.
In a further improvement, a second dielectric layer is formed on the side surface of the charge balance groove in a self-alignment manner, and the second dielectric layer located at the bottom of the charge balance groove, at the top corner of the charge balance groove and at the bottom of the opening of the source contact hole outside the charge balance groove is removed.
And a first contact region and a second contact region which are composed of a second conductive type heavily doped injection region are formed in the region where the second dielectric layer is removed.
The first contact region is located on the top surface of the charge balance region, and the second contact region is located at the top corner of the charge balance groove and the surface of the channel region at the bottom of the opening of the source contact hole outside the charge balance groove.
In a further improvement, the conductive material layer of the source lead-out structure is directly composed of a metal layer constituting the source contact hole, and the metal layer of the source contact hole is simultaneously filled in the opening of the source contact hole and the charge balance groove at the bottom of the opening of the source contact hole.
In a further improvement, the trench-gate power device is a trench-gate power MOSFET.
The trench gate power MOSFET is an N-type device, the first conduction type is an N-type device, and the second conduction type is a P-type device; or, the trench gate power MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
The breakdown voltage of the trench gate power MOSFET is 30V-100V.
The depth of the grid groove is 0.4-1.5 microns.
In order to solve the technical problem, the manufacturing method of the trench gate power device provided by the invention comprises the following steps:
the method comprises the steps of firstly, providing a semiconductor substrate, and forming a drift region doped with a first conduction type on the surface of the semiconductor substrate.
Forming a trench gate power device in a semiconductor substrate, wherein a current flowing area of the trench gate power device is formed by periodically arranging a plurality of original cells; forming a trench gate of each original cell, wherein the trench gate of each original cell comprises a gate trench, a gate dielectric layer and a gate conductive material layer, and the method comprises the following steps:
and forming the grid grooves in the drift region by adopting a photoetching and etching process, wherein the region between every two adjacent grid grooves is a semiconductor platform region.
And forming the gate dielectric layer on the bottom surface and the side surface of the gate groove.
And filling an electric material layer in the grid groove to form the grid conductive material layer.
Step three, injecting second conductive type doped ions into the surface area of the drift area of the semiconductor platform area by taking the trench gate as a self-alignment definition condition to form a channel area in a self-alignment manner; the junction depth of the channel region is smaller than the depth of the grid groove, and the surface of the channel region covered by the side face of the grid conductive material layer is used for forming a channel.
And fourthly, forming a charge balance groove in the drift region of the semiconductor platform region by adopting a photoetching and etching process, wherein the depth of the charge balance groove is greater than that of the grid groove.
Fifthly, self-aligned second conductive type doped ions are implanted into the drift region at the bottom of the charge balance groove to form a charge balance region; the charge balance region and the adjacent drift region are mutually depleted, so that the voltage endurance of the device can be improved, and the doping concentration of the drift region is increased, so that the on-resistance of the device is reduced.
And sixthly, filling a third dielectric layer in the charge balance groove, and performing self-aligned ion implantation of the first conduction type heavy doping on the surface area of the channel region outside the charge balance groove to form a source region.
Forming an interlayer film, wherein the interlayer film covers the trench gate, the source region and the third dielectric layer; forming a contact hole penetrating through the interlayer film, the contact hole at the top of the source region being a source contact hole; the step of forming the contact hole comprises the steps of firstly forming an opening of the contact hole by adopting a photoetching and etching process, and then filling metal into the opening of the contact hole to form the contact hole.
The lateral size of the opening of the source contact hole is larger than that of the charge balance groove, the top of the charge balance groove is completely exposed, and the step of removing the third dielectric layer in the charge balance groove after the opening of the source contact hole is formed is further included, so that the opening of the source contact hole and the charge balance groove are communicated in the longitudinal direction.
The opening bottom of the source contact hole penetrates the source region in the longitudinal direction and exposes the surface of the channel region.
Eighthly, forming a source leading-out structure made of a conductive material in the charge balance groove at the opening and the bottom of the source contact hole, wherein the source leading-out structure and the charge balance area at the bottom, the channel area and the source area form ohmic contact; and forming a front metal layer, imaging the front metal layer to form a source electrode, and connecting the top of the source lead-out structure with the source electrode.
In a further improvement, the semiconductor substrate is a silicon substrate; the gate dielectric layer is a gate oxide layer; the grid conductive material layer is a polysilicon grid.
The further improvement is that the step eight comprises the following sub-steps:
and growing a second dielectric layer, then carrying out overall etching on the second dielectric layer to form the second dielectric layer on the side surface of the charge balance groove in a self-alignment manner, and removing the second dielectric layer which is positioned at the bottom of the charge balance groove, at the top corner of the charge balance groove and at the bottom of the opening of the source contact hole outside the charge balance groove.
Performing ion implantation of second conductive type heavy doping to form a first contact region and a second contact region in a self-alignment manner in the region where the second dielectric layer is removed; the first contact region is located on the top surface of the charge balance region, and the second contact region is located at the top corner of the charge balance groove and the surface of the channel region at the bottom of the opening of the source contact hole outside the charge balance groove.
And growing a second polycrystalline silicon layer and carrying out back etching on the second polycrystalline silicon layer, wherein the second polycrystalline silicon layer after back etching is filled in the charge balance groove and extends into the opening of the source contact hole, the second polycrystalline silicon layer forms ohmic contact with the charge balance area at the bottom, the channel area and the source area, and the second polycrystalline silicon layer is used as a component of a conductive material layer of the source leading-out structure.
And filling a metal layer in the opening of the source contact hole at the top of the second polysilicon layer, forming the source contact hole by the metal layer filled in the opening of the source contact hole at the top of the second polysilicon layer, and overlapping the second polysilicon layer and the source contact hole to form the source lead-out structure.
In a further improvement, the second polysilicon layer is heavily doped with the first conductivity type; or, the second polysilicon layer is heavily doped with the second conductive type.
The further improvement is that the step eight comprises the following sub-steps:
performing ion implantation self-alignment of second conductive type heavy doping to form a first contact region and a second contact region; the first contact region is located on the top surface of the charge balance region, and the second contact region is located at the top corner of the charge balance groove and the surface of the channel region at the bottom of the opening of the source contact hole outside the charge balance groove.
And filling metal layers in the openings of the source contact holes and the charge balance grooves at the bottoms of the openings of the source contact holes to form the source contact holes, wherein the conductive material layer of the source leading-out structure directly consists of the metal layers forming the source contact holes.
The further improvement is that the trench gate power device is a trench gate power MOSFET;
the trench gate power MOSFET is an N-type device, the first conduction type is an N-type device, and the second conduction type is a P-type device; or, the trench gate power MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
The breakdown voltage of the trench gate power MOSFET is 30V-100V.
The depth of the grid groove is 0.4-1.5 microns.
A further improvement is that, when the trench gate power MOSFET is an N-type device, the implanted impurity of the charge balance region in step five is boron or boron difluoride.
The ion implantation of the charge balance area is single implantation; or, the ion implantation of the charge balance region comprises multiple implantation, the implantation energy is different between the multiple implantation, and the distribution uniformity of the charge balance region in the longitudinal direction is improved by the multiple implantation.
The trench gate power device is additionally provided with a charge balance groove formed in a drift region between trench gates by a photoetching process on the basis of the conventional device, and a charge balance region is formed at the bottom of the charge balance groove in a self-aligning manner, and the doping type of the charge balance region is opposite to that of the drift region, so that the adjacent drift regions can be mutually depleted when the device is reversely biased, the voltage resistance of the device can be improved, the doping concentration of the drift region can be improved, and the on-resistance of the device can be reduced.
Compared with the existing trench gate power device adopting the super junction structure, namely the super junction device, the trench gate power device adopting the super junction structure can be realized by adopting four times of photoetching processes, and compared with the existing super junction device needing 7-8 times of photoetching processes, the trench gate power device adopting the super junction structure has the advantages that the process cost is greatly reduced, and the trench gate power device is very suitable for being applied to power devices with breakdown voltages of 30-100V.
In addition, the invention does not need to adopt a shielding grid structure, and compared with the existing trench grid power device with the shielding grid, namely an SGT device, the invention has smaller process difficulty, such as: the depth of the grid groove of the invention is smaller, and an isolating dielectric film such as an oxide film is not required to be arranged between the source polysilicon of the shielding grid and the polysilicon grid of the groove grid, so that the process difficulty can be reduced, and the consistency of devices can be improved.
In addition, the charge balance groove is positioned at the bottom of the opening of the source contact hole, so that good ohmic contact with a channel region and a source region can be realized through the source lead-out structure formed in the charge balance groove, and good reliability of a device can be ensured.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic structural diagram of a trench gate power device according to a first embodiment of the present invention;
fig. 2A to fig. 2N are schematic device structures in steps of a method for manufacturing a trench-gate power device according to a first embodiment of the present invention.
Detailed Description
The trench gate power device of the first embodiment of the present invention:
as shown in fig. 1, which is a schematic structural diagram of a trench gate power device according to a first embodiment of the present invention, the trench gate power device according to the first embodiment of the present invention is formed in a semiconductor substrate 1, and a current flowing region of the trench gate power device is formed by periodically arranging a plurality of primitive cells.
The drift region 2 doped with the first conductive type is formed on the surface of the semiconductor substrate 1, and the trench gate of each cell comprises a gate trench 102, a gate dielectric layer 3 and a gate conductive material layer 4; the gate trenches 102 are formed in the drift region 2, and a region between each adjacent gate trenches 102 is a semiconductor mesa region. The structure of the gate trench 102 is shown in fig. 2B.
In the first embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate; the gate dielectric layer 3 is a gate oxide layer; the gate conductive material layer 4 is a polysilicon gate.
The gate dielectric layer 3 is formed on the bottom surface and the side surface of the gate trench 102, and the gate conductive material layer 4 is filled in the gate trench 102.
A channel region 5 doped with the second conductive type is formed in a self-aligned manner in the surface region of the drift region 2 of the semiconductor platform region, the junction depth of the channel region 5 is smaller than the depth of the gate trench 102, and the surface of the channel region 5 covered by the side surface of the gate conductive material layer 4 is used for forming a channel.
A charge balance trench 107 is formed in the drift region 2 of the semiconductor mesa region, the depth of the charge balance trench 107 is greater than the depth of the gate trench 102, and the structure of the charge balance trench 107 is shown in fig. 2G.
A charge balance region 6 composed of a second conductivity type doped region is formed in the drift region 2 at the bottom of the charge balance trench 107 in a self-aligned manner, and the charge balance region 6 and the adjacent drift region 2 are mutually depleted so as to improve the withstand voltage capability of the device and simultaneously improve the doping concentration of the drift region 2 so as to reduce the on-resistance of the device.
A source region 7 heavily doped with the first conductivity type is formed in a surface region of the channel region 5 outside the charge balance trench 107 in self-alignment.
A source contact hole 12 penetrating through an interlayer film 8 is formed at the top of the source region 7, an opening 110 of the source contact hole 12 is larger in lateral size than the charge balance trench 107 and exposes the top of the charge balance trench 107 entirely, the opening 110 of the source contact hole 12 and the charge balance trench 107 are communicated in the longitudinal direction, the bottom of the opening 110 of the source contact hole 12 penetrates through the source region 7 and exposes the surface of the channel region 5 in the longitudinal direction, a source extraction structure composed of a conductive material is formed in the charge balance trench 107 at the bottom and the opening 110 of the source contact hole 12, the source extraction structure and the charge balance region 6 at the bottom, the channel region 5 and the source region 7 form an ohmic contact, and the top of the source extraction structure is connected to a source composed of a front metal layer 13.
In the first embodiment of the present invention, the conductive material layer of the source lead-out structure includes the second polysilicon layer 11, the second polysilicon layer 11 is filled in the charge balance trench 107 and extends into the opening 110 of the source contact hole 12, and the second polysilicon layer 11 and the bottom charge balance region 6, the channel region 5 and the source region 7 form an ohmic contact. The second polysilicon layer 11 is heavily doped with a first conductive type; alternatively, the second polysilicon layer 11 is heavily doped with the second conductivity type.
The opening 110 of the source contact hole 12 at the top of the second polysilicon layer 11 is filled with a metal layer, the source contact hole 12 is formed by the metal layer filled in the opening 110 of the source contact hole 12 at the top of the second polysilicon layer 11, and the second polysilicon layer 11 and the source contact hole 12 are overlapped to form the source lead-out structure.
A second dielectric layer 9 is formed on the side surface of the charge balance groove 107 in a self-aligned manner, and the second dielectric layer 9 located at the bottom of the charge balance groove 107, at the top corner of the charge balance groove 107 and at the bottom of the opening 110 of the source contact hole 12 outside the charge balance groove 107 is removed. Preferably, the second dielectric layer 9 is a silicon oxide film; or, the second dielectric layer 9 is a combined film of silicon oxide and silicon nitride.
A first contact region 10a and a second contact region 10b composed of a second conductive type heavily doped implantation region are formed in the region where the second dielectric layer 9 is removed.
The first contact region 10a is located at the top surface of the charge balance region 6, and the second contact region 10b is located at the top corner of the charge balance trench 107 and the surface of the channel region 5 at the bottom of the opening 110 of the source contact hole 12 outside the charge balance trench 107.
In the first embodiment of the present invention, the trench gate power device is a trench gate power MOSFET, the trench gate power MOSFET is an N-type device, i.e., an NMOS, the first conductivity type is an N-type, and the second conductivity type is a P-type. In other embodiments can also be: the trench gate power MOSFET is a P-type device, the first conduction type is P-type, and the second conduction type is N-type. The breakdown voltage of the trench gate power MOSFET is 30V-100V. The depth of the gate trench 102 is 0.4 to 1.5 microns.
The device of the first embodiment of the present invention is described in more detail below with specific process parameters:
since the trench gate power MOSFET of the first embodiment of the present invention is an NMOS, the semiconductor substrate 1 is doped with N +, the doped impurity can be phosphorus or arsenic, and the resistivity of the semiconductor substrate 1 is 0.001 ohm cm to 0.003 ohm cm; in addition, in low voltage devices, Red P substrates (Red P substrates) can be used, and the resistivity can be less than 0.0017 ohm.
The drift region 2 is formed by an N-type epitaxial layer formed on the semiconductor substrate 1, the doping impurities of the N-type epitaxial layer 2 can be phosphorus or arsenic, and the resistivity and the thickness of the N-type epitaxial layer 2 are selected according to the structure of a device and the breakdown voltage of the device, for example: the device with the breakdown voltage of 40-60V can obtain the N-type epitaxial layer 2 with the resistivity of 0.1-0.15 ohm-cm and the thickness of 3-4 microns.
The depth of the gate trench 102 can be designed according to the characteristics required by the device, and can be 0.4 to 1 micron, and the width of the gate trench 102 is 0.1 to 1 micron; in one embodiment, the gate trench 102 has a depth of 0.45 microns and a width of 0.45 microns.
The thickness of the gate dielectric layer 3 is 25 nm-100 nm.
The polysilicon gate of the gate conductive material layer 4 is of a high-concentration doping structure, and the impurity concentration is higher than 1E19cm-3。
The ion-implanted impurity of the source region 7 can be phosphorus or arsenic, and the implantation dose is generally several E15cm-2。
The metal layer filled in the opening of the contact hole including the opening 110 of the source contact hole 12 includes a Ti layer and a TiN layer deposited in sequence on the inner surface of the opening of the contact hole and a W layer filling the opening completely, and the W layer outside the opening needs to be removed by a back etching process.
The material of the front-side metal layer 13 adopts ALCu.
The trench gate power device of the first embodiment of the invention adds a photolithography process on the basis of the existing device to form the charge balance trench 107 in the drift region 2 between the trench gates and form the charge balance region 6 in the bottom of the charge balance trench 107 in a self-alignment manner, the doping type of the charge balance region 6 is opposite to that of the drift region 2, so that mutual depletion of the adjacent drift regions 2 can be realized when the device is reversely biased, the withstand voltage capability of the device can be improved, the doping concentration of the drift region 2 can be improved, and the on-resistance of the device can be reduced.
Compared with the existing trench gate power device adopting the super junction structure, namely the super junction device, the first embodiment of the invention can be realized by adopting four times of photoetching processes, and compared with the existing super junction device which needs 7-8 times of photoetching processes, the first embodiment of the invention has the advantages that the process cost is greatly reduced, and the invention is very suitable for the application of the power device with the breakdown voltage of 30-100V.
In addition, the first embodiment of the present invention does not need to adopt a shield gate structure, and compared to the existing trench gate power device with a shield gate, i.e., an SGT device, the process difficulty of the first embodiment of the present invention is small, for example: the depth of the gate trench 102 of the first embodiment of the present invention is small, and there is no need to provide an isolation dielectric film, such as an oxide film, between the source polysilicon of the shield gate and the polysilicon gate of the trench gate, which can both reduce process difficulties and improve device uniformity.
In addition, the charge balance trench 107 according to the first embodiment of the present invention is located at the bottom of the opening 110 of the source contact hole 12, so that a good ohmic contact with the channel region 5 and the source region 7 can be realized by the source lead structure formed in the charge balance trench 107, and good reliability of the device can be ensured.
The device structure of the first embodiment of the present invention adopts 4 times of lithography, and forms a charge balance region 6 through lithography and etching of the charge balance trench 107 and ion implantation, and the P-type impurity of the charge balance region 6 and the adjacent N-type drift region 2 are mutually depleted, thereby ensuring that the impurity concentration of the N-type drift region 2 can be designed to be much higher than that of the device on the common trench, and reducing the on-resistance.
The device only adopts 4 times of photoetching, so that the cost is saved.
The device does not adopt the structure of a conventional shielding grid MOSFET, so that the process difficulty is reduced, an oxide film between the polysilicon of the isolated source electrode and the drain region in the shielding grid MOSFET is eliminated, a deep groove required by the formation of the shielding grid is eliminated, the process difficulty is reduced, and the consistency of the device is improved.
The second polysilicon layer 11 with high concentration of the device forms good ohmic contact with the channel region 5 and the source region 7 of the N +, thereby ensuring the reliability of the device
In the device according to the first embodiment of the present invention, the first contact region 10a is implanted with a larger distance from the channel region 5, and the energy and dose of the implantation of the first contact region 10a do not affect the impurity distribution of the channel region 5 of the device, so that the uniformity of the device can be improved. Thus, the implantation dosage of the first contact region 10a can be independently adjusted, and the flow impact resistance, i.e. the EAS resistance, of the device can be improved.
The depth of the gate trench 102 of the trench gate of the device according to the first embodiment of the present invention can be adjusted according to the requirements of the device, which is different from the structure of a common SGT device, in which the gate trench of the common SGT device contains both source polysilicon and polysilicon gate, and the depth of the source polysilicon is related to the voltage of the device, so that the depth of the whole gate trench is generally large, which causes the stress (stress) of the device after the whole gate trench process is completed to increase, and causes the problems of device performance consistency and reliability.
In the manufacturing process of the device of the first embodiment of the invention, the thicknesses of the screen oxide layer (screen oxide) before the P-type well of the channel region 5 is injected, namely the thickness of the oxide layer 3 and the thickness of the screen oxide before the N + source region 7 are injected can be well controlled, and the consistency of the device performance is ensured
In the corresponding manufacturing process of the device according to the first embodiment of the present invention, the polysilicon gate 4 in the trench gate is completed by CMP, and the polysilicon gate 4 does not have a notch (notch) of the top polysilicon of the conventional MOSFET at the top of the gate trench 102, so that the uniformity of the device performance is improved.
In the device according to the first embodiment of the present invention, the depth of the gate trench 102 may be adjusted according to the requirement of the device, and may be designed to be a short channel, for example, the depth is 0.4 to 0.5 micrometers, or the depth may be increased to 0.8 to 1.5 micrometers, so as to adjust the Cgd of the device.
In the device according to the first embodiment of the present invention, the injection of the charge balance region 6 may be performed multiple times with different energies, so as to ensure that the concentration of the P-type impurity after injection is relatively uniformly distributed in the longitudinal direction; b can be injected, BF2 can also be injected, or the combination of the two can be injected, and the high-energy B injection with the injection energy of 1 Mev-6 Mev is adopted, so that the longitudinal depth of the charge balance area 6 can be increased, and the requirements of devices with different voltages can be met.
The trench gate power device of the second embodiment of the present invention:
the difference between the trench gate power device according to the second embodiment of the present invention and the trench gate power device according to the first embodiment of the present invention is that the conductive material layer of the source lead-out structure in the trench gate power device according to the second embodiment of the present invention is directly composed of the metal layer constituting the source contact hole 12, and the metal layer of the source contact hole 12 is simultaneously filled in the opening 110 of the source contact hole 12 and the charge balance trench 107 at the bottom of the opening 110 of the source contact hole 12. At the same time, the second dielectric layer 9 can be omitted.
The manufacturing method of the trench gate power device of the first embodiment of the invention comprises the following steps:
as shown in fig. 2A to fig. 2N, the schematic device structures in the steps of the manufacturing method of the trench-gate power device according to the first embodiment of the present invention are shown, and the manufacturing method of the trench-gate power device according to the first embodiment of the present invention includes the following steps:
step one, as shown in fig. 2A, a semiconductor substrate 1 is provided, and a drift region 2 doped with a first conductivity type is formed on a surface of the semiconductor substrate 1.
The semiconductor substrate 1 is a silicon substrate.
Step two, a trench gate power device is formed in the semiconductor substrate 1, and a current flowing area of the trench gate power device is formed by periodically arranging a plurality of original cells; forming a trench gate of each cell, wherein the trench gate of each cell comprises a gate trench 102, a gate dielectric layer 3 and a gate conductive material layer 4, and the method comprises the following steps:
as shown in fig. 2B, a photoresist pattern 101 is formed by photolithography, an etching process is performed under the definition of the photoresist pattern 101 to form the gate trenches 102 in the drift region 2, and a region between each adjacent gate trenches 102 is a semiconductor platform region.
As shown in fig. 2C, the gate dielectric layer 3 is formed on the bottom surface and the side surface of the gate trench 102. The gate dielectric layer 3 is a gate oxide layer and is formed by adopting a thermal oxidation process. Preferably, before the gate oxide layer 3 is formed by a thermal oxidation process, an oxidation process for forming a sacrificial oxide film is further performed, the thickness of the sacrificial oxide film is 40-50 microns, and then the sacrificial oxide film is removed by wet etching.
As shown in fig. 2D, the gate conductive material layer 4 is formed by filling an electric material layer in the gate trench 102. The gate conductive material layer 4 is a polysilicon gate. The polysilicon gate 3 is first filled in the gate trench 102 by a deposition process, and then polysilicon on the surface of the semiconductor substrate 1 is removed by a Chemical Mechanical Polishing (CMP) process.
Step three, as shown in fig. 2E, performing ion implantation of second conductivity type doping as shown by arrow line 103 under the self-aligned definition condition of the trench gate to self-align the surface region of the drift region 2 of the semiconductor platform region to form a channel region 5; the junction depth of the channel region 5 is smaller than the depth of the gate trench 102, and the surface of the channel region 5 covered by the side surface of the gate conductive material layer 4 is used for forming a channel.
The channel region 5 is formed by adopting a second conductive type well implantation process, and the implantation dosage of the second conductive type well implantation process is set according to the requirement of the designed threshold voltage of the device.
Step four, as shown in fig. 2F, a hard mask layer formed by stacking the nitride layer 104, the oxide layer 105, and the nitride layer 106 is formed.
As shown in fig. 2G, a charge balance trench 107 is formed in the drift region 2 of the semiconductor platform region by using a photolithography and etching process, and the depth of the charge balance trench 107 is greater than the depth of the gate trench 102.
Step five, as shown in fig. 2H, performing self-aligned ion implantation of second conductivity type doping in the drift region 2 at the bottom of the charge balance trench 107 to form a charge balance region 6; the charge balance region 6 and the adjacent drift region 2 are mutually depleted, so that the voltage endurance of the device can be improved, and the doping concentration of the drift region 2 is increased, so that the on-resistance of the device is reduced.
The thickness of the charge balance region 6 needs to be achieved by ion implantation and subsequent thermal process diffusion, and this charge balance region 6 needs to withstand the voltage when the device is reverse biased.
Sixthly, as shown in fig. 2I, the nitride layer 106 and the oxide layer 105 are removed.
The charge balance trench 107 is filled with a third dielectric layer 108.
In the method according to the first embodiment of the present invention, the third dielectric layer 108 is an oxide layer, and after the charge balance trench 107 is completely filled with the oxide layer, a CMP process using the nitride layer 104 as a stop layer is required to remove the third dielectric layer 108 on the surface of the nitride layer 104 outside the charge balance trench 107.
As shown in fig. 2J, the nitride layer 104 is removed, and the surface of the polysilicon gate 4 is oxidized by a thermal oxidation process to form an oxide layer 3 a.
As shown in fig. 2K, a self-aligned ion implantation of a heavily doped first conductivity type is performed in a surface region of the channel region 5 outside the charge balance trench 107 to form a source region 7.
Seventhly, as shown in fig. 2L, an interlayer film 8 is formed, and the trench gate, the source region 7 and the third dielectric layer 108 are all covered by the interlayer film 8; forming a contact hole through the interlayer film 8, the contact hole at the top of the source region 7 being a source contact hole 12; the step of forming the contact hole comprises the steps of firstly forming an opening of the contact hole by adopting a photoetching and etching process, and then filling metal into the opening of the contact hole to form the contact hole.
The lateral dimension of the opening 110 of the source contact hole 12 is larger than the lateral dimension of the charge balance trench 107 and the top of the charge balance trench 107 is fully exposed, and after the opening 110 of the source contact hole 12 is formed, the step of removing the third dielectric layer 108 in the charge balance trench 107 is further included so that the opening 110 of the source contact hole 12 and the charge balance trench 107 are longitudinally communicated.
The opening 110 of the source contact hole 12 passes through the source region 7 at the bottom in the longitudinal direction and exposes the surface of the channel region 5.
Step eight, as shown in fig. 1, a source lead-out structure made of a conductive material is formed in the opening 110 of the source contact hole 12 and the charge balance trench 107 at the bottom, and the source lead-out structure forms an ohmic contact with the charge balance region 6 at the bottom, the channel region 5 and the source region 7. And forming a front metal layer 13, patterning the front metal layer 13 to form a source electrode, and connecting the top of the source lead-out structure with the source electrode. The front metal layer 13 is patterned to form a gate, and the gate is contacted with the polysilicon gate 4 at the bottom through a corresponding contact hole.
In the method of the first embodiment of the present invention, the eighth step includes the following sub-steps:
as shown in fig. 2M, a second dielectric layer 9 is grown, and then the second dielectric layer 9 is fully etched to form the second dielectric layer 9 in a self-aligned manner on the side surface of the charge balance trench 107, and the second dielectric layer 9 located at the bottom of the charge balance trench 107, at the top corner of the charge balance trench 107, and at the bottom of the opening 110 of the source contact hole 12 outside the charge balance trench 107 is removed.
Performing ion implantation of second conductive type heavy doping to form a first contact region 10a and a second contact region 10b in a self-alignment manner in the region where the second dielectric layer 9 is removed; the first contact region 10a is located at the top surface of the charge balance region 6, and the second contact region 10b is located at the top corner of the charge balance trench 107 and the surface of the channel region 5 at the bottom of the opening 110 of the source contact hole 12 outside the charge balance trench 107.
As shown in fig. 2N, a second polysilicon layer 11 is grown and etched back, the etched-back second polysilicon layer 11 is filled in the charge balance trench 107 and extends into the opening 110 of the source contact hole 12, the second polysilicon layer 11 forms an ohmic contact with the charge balance region 6, the channel region 5 and the source region 7 at the bottom, and the second polysilicon layer 11 is used as a component of the conductive material layer of the source lead-out structure. In the method according to the first embodiment of the present invention, the second polysilicon layer 11 is heavily doped with the first conductive type. In other embodiments the method can also be: the second polysilicon layer 11 is heavily doped with the second conductivity type.
As shown in fig. 1, a metal layer is filled in the opening 110 of the source contact hole 12 at the top of the second polysilicon layer 11, the source contact hole 12 is composed of the metal layer filled in the opening 110 of the source contact hole 12 at the top of the second polysilicon layer 11, and the source lead-out structure is formed by overlapping the second polysilicon layer 11 and the source contact hole 12.
In the method according to the first embodiment of the present invention, the trench gate power device is a trench gate power MOSFET, the trench gate power MOSFET is an N-type device, the first conductivity type is an N-type device, and the second conductivity type is a P-type device. In other embodiments can also be: the trench gate power MOSFET is a P-type device, the first conduction type is P-type, and the second conduction type is N-type. The breakdown voltage of the trench gate power MOSFET is 30V-100V. The depth of the gate trench 102 is 0.4 to 1.5 microns.
In the fifth step, the implanted impurity of the charge balance region 6 is boron or boron difluoride. The ion implantation of the charge balance area 6 is single implantation; alternatively, the ion implantation of the charge balance region 6 includes multiple implantations, implantation energies are different between the respective implantations, and the distribution uniformity of the charge balance region 6 in the longitudinal direction is improved by the multiple implantations.
The method according to the first embodiment of the present invention is described in more detail below with specific process parameters:
since the trench gate power MOSFET in the method according to the first embodiment of the present invention is an NMOS, in the first step, the semiconductor substrate 1 is doped with N +, the doped impurity can be phosphorus or arsenic, and the resistivity of the semiconductor substrate 1 is 0.001 ohm cm to 0.003 ohm cm; in addition, in low voltage devices, Red P substrates (Red P substrates) can be used, and the resistivity can be less than 0.0017 ohm.
In the first step, the drift region 2 is formed by an N-type epitaxial layer formed on the semiconductor substrate 1, the doping impurities of the N-type epitaxial layer 2 can be phosphorus or arsenic, and the resistivity and the thickness of the N-type epitaxial layer 2 are selected according to the structure of the device and the breakdown voltage of the device, for example: the device with the breakdown voltage of 40-60V can obtain the N-type epitaxial layer 2 with the resistivity of 0.1-0.15 ohm-cm and the thickness of 3-4 microns.
In the second step, the depth of the gate trench 102 can be designed according to the characteristics required by the device, and can be 0.4 to 1 micron, and the width of the gate trench 102 is 0.1 to 1 micron; in one embodiment, the gate trench 102 has a depth of 0.45 microns and a width of 0.45 microns.
In the second step, the thickness of the gate dielectric layer 3 is 25nm to 100 nm.
In the second step, the polysilicon gate of the gate conductive material layer 4 is a high-concentration doped structure, and the impurity concentration is higher than 1E19cm-3。
In the sixth step, the ion-implanted impurity of the source region 7 can be phosphorus or arsenic, and the implantation dose is generally several E15cm-2。
In step seven, the metal layer filled in the opening of the contact hole, including the opening 110 of the source contact hole 12, comprises a Ti layer and a TiN layer which are sequentially deposited on the inner surface of the opening of the contact hole and a W layer which completely fills the opening, and the W layer outside the opening needs to be removed by adopting a back etching process.
In the eighth step, ALCu is adopted as the material of the front-side metal layer 13.
The device structure of the first embodiment of the present invention adopts 4 times of lithography, and forms a charge balance region 6 through lithography and etching of the charge balance trench 107 and ion implantation, and the P-type impurity of the charge balance region 6 and the adjacent N-type drift region 2 are mutually depleted, thereby ensuring that the impurity concentration of the N-type drift region 2 can be designed to be much higher than that of the device on the common trench, and reducing the on-resistance.
The device only adopts 4 times of photoetching, so that the cost is saved.
The device does not adopt the structure of a conventional shielding grid MOSFET, so that the process difficulty is reduced, an oxide film between the polysilicon of the isolated source electrode and the drain region in the shielding grid MOSFET is eliminated, a deep groove required by the formation of the shielding grid is eliminated, the process difficulty is reduced, and the consistency of the device is improved.
The second polysilicon layer 11 with high concentration of the device forms good ohmic contact with the channel region 5 and the source region 7 of the N +, thereby ensuring the reliability of the device
In the method according to the first embodiment of the present invention, the first contact region 10a is implanted with a larger distance from the channel region 5, and the energy and dose of the implantation of the first contact region 10a do not affect the impurity distribution of the channel region 5 of the device, so that the uniformity of the device can be improved. Thus, the implantation dosage of the first contact region 10a can be independently adjusted, and the flow impact resistance, i.e. the EAS resistance, of the device can be improved.
The depth of the gate trench 102 of the trench gate in the method according to the first embodiment of the present invention can be adjusted according to the requirements of the device, which is different from the structure of a common SGT device, in which the gate trench of the common SGT device contains both source polysilicon and polysilicon gate, and the depth of the source polysilicon is related to the voltage of the device, so that the depth of the whole gate trench is generally large, which causes the stress (stress) of the device after the whole gate trench process is completed to increase, and causes the problems of device performance consistency and reliability.
In the method of the first embodiment of the present invention, the thicknesses of the screen oxide layer (screen oxide) before the P-type well of the channel region 5 is implanted, that is, the thickness of the screen oxide before the oxide layer 3 and the N + source region 7 are implanted can be well controlled, and the uniformity of the device performance is ensured
In the method according to the first embodiment of the present invention, the polysilicon gate 4 in the trench gate is completed by CMP, and the polysilicon gate 4 does not have a gap (notch) in the top polysilicon of the conventional MOSFET at the top of the gate trench 102, thereby improving the uniformity of the device performance.
In the method according to the first embodiment of the present invention, the depth of the gate trench 102 may be adjusted according to the requirements of the device, and may be designed to be a short channel, for example, the depth is 0.4 to 0.5 micrometers, or the depth may be increased to 0.8 to 1.5 micrometers, so as to adjust the Cgd of the device.
In the method of the first embodiment of the present invention, the injection of the charge balance region 6 may be performed multiple times with different energies, so as to ensure that the concentration of the P-type impurity after injection is relatively uniformly distributed in the longitudinal direction; b can be injected, BF2 can also be injected, or the combination of the two can be injected, and the high-energy B injection with the injection energy of 1 Mev-6 Mev is adopted, so that the longitudinal depth of the charge balance area 6 can be increased, and the requirements of devices with different voltages can be met.
The manufacturing method of the trench gate power device of the second embodiment of the invention comprises the following steps:
the difference between the manufacturing method of the trench gate power device according to the second embodiment of the present invention and the manufacturing method of the trench gate power device according to the first embodiment of the present invention is that the eighth step in the manufacturing method of the trench gate power device according to the second embodiment of the present invention includes the following sub-steps:
performing ion implantation of second conductive type heavy doping and self-aligning to form a first contact region 10a and a second contact region 10 b; the first contact region 10a is located at the top surface of the charge balance region 6, and the second contact region 10b is located at the top corner of the charge balance trench 107 and the surface of the channel region 5 at the bottom of the opening 110 of the source contact hole 12 outside the charge balance trench 107.
Filling metal layers into the opening 110 of the source contact hole 12 and the charge balance groove 107 at the bottom of the opening 110 of the source contact hole 12 to form the source contact hole 12, wherein the conductive material layer of the source lead-out structure is directly composed of the metal layers composing the source contact hole 12.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A trench-gate power device, comprising: the trench gate power device is formed in the semiconductor substrate, and a current flowing area of the trench gate power device is formed by periodically arranging a plurality of original cells;
the drift region doped with the first conductive type is formed on the surface of the semiconductor substrate, and the trench gate of each primitive cell comprises a gate trench, a gate dielectric layer and a gate conductive material layer; the grid grooves are formed in the drift region, and the region between every two adjacent grid grooves is a semiconductor platform region;
the gate dielectric layer is formed on the bottom surface and the side surface of the gate groove, and the gate conductive material layer is filled in the gate groove;
a channel region doped with the second conduction type is formed in the drift region surface region of the semiconductor platform region in a self-alignment mode, the junction depth of the channel region is smaller than the depth of the grid groove, and the surface of the channel region covered by the side face of the grid conduction material layer is used for forming a channel;
a charge balance trench is formed in the drift region of the semiconductor platform region, the depth of the charge balance trench being greater than the depth of the gate trench;
a charge balance region composed of a second conductive type doped region is formed in the drift region at the bottom of the charge balance groove in a self-alignment mode, and the charge balance region and the adjacent drift region are mutually depleted, so that the voltage endurance of the device can be improved, and meanwhile, the doping concentration of the drift region is improved, so that the on-resistance of the device is reduced;
a source region with a first conductive type heavy doping is formed in a self-alignment mode on the surface region of the channel region outside the charge balance groove;
and a source contact hole penetrating through an interlayer film is formed at the top of the source region, the opening transverse dimension of the source contact hole is larger than the transverse dimension of the charge balance groove, the top of the charge balance groove is completely exposed, the opening of the source contact hole is communicated with the charge balance groove in the longitudinal direction, the bottom of the opening of the source contact hole penetrates through the source region in the longitudinal direction and exposes the surface of the channel region, a source leading-out structure composed of a conductive material is formed in the charge balance groove at the opening and the bottom of the source contact hole, the source leading-out structure and the charge balance region at the bottom, the channel region and the source region form ohmic contact, and the top of the source leading-out structure is connected with a source electrode composed of a front metal layer.
2. The trench-gate power device of claim 1 wherein: the semiconductor substrate is a silicon substrate; the gate dielectric layer is a gate oxide layer; the grid conductive material layer is a polysilicon grid.
3. The trench-gate power device of claim 2 wherein: the conductive material layer of the source leading-out structure comprises a second polycrystalline silicon layer, the second polycrystalline silicon layer is filled in the charge balance groove and extends into the opening of the source contact hole, and ohmic contact is formed between the second polycrystalline silicon layer and the charge balance area, the channel area and the source area at the bottom.
4. The trench-gate power device of claim 3 wherein: and a metal layer is filled in the opening of the source contact hole at the top of the second polycrystalline silicon layer, the source contact hole is formed by the metal layer filled in the opening of the source contact hole at the top of the second polycrystalline silicon layer, and the second polycrystalline silicon layer and the source contact hole are superposed to form the source lead-out structure.
5. The trench-gate power device of claim 3 wherein: the second polycrystalline silicon layer is heavily doped with a first conduction type; or, the second polysilicon layer is heavily doped with the second conductive type.
6. The trench-gate power device of claim 3 wherein: forming a second dielectric layer on the side surface of the charge balance groove in a self-alignment manner, and removing the second dielectric layer which is positioned at the bottom of the charge balance groove, at the top corner of the charge balance groove and at the bottom of the opening of the source contact hole outside the charge balance groove;
a first contact region and a second contact region which are composed of a second conductive type heavily doped injection region are formed in the region where the second medium layer is removed;
the first contact region is located on the top surface of the charge balance region, and the second contact region is located at the top corner of the charge balance groove and the surface of the channel region at the bottom of the opening of the source contact hole outside the charge balance groove.
7. The trench-gate power device of claim 2 wherein: the conductive material layer of the source lead-out structure is directly composed of a metal layer forming the source contact hole, and the metal layer of the source contact hole is simultaneously filled in the opening of the source contact hole and the charge balance groove at the bottom of the opening of the source contact hole.
8. The trench-gate power device of any of claims 1 to 7, wherein: the trench gate power device is a trench gate power MOSFET;
the trench gate power MOSFET is an N-type device, the first conduction type is an N-type device, and the second conduction type is a P-type device; or the trench gate power MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type;
the breakdown voltage of the trench gate power MOSFET is 30-100V;
the depth of the grid groove is 0.4-1.5 microns.
9. A manufacturing method of a trench gate power device is characterized by comprising the following steps:
providing a semiconductor substrate, and forming a drift region doped with a first conduction type on the surface of the semiconductor substrate;
forming a trench gate power device in a semiconductor substrate, wherein a current flowing area of the trench gate power device is formed by periodically arranging a plurality of original cells; forming a trench gate of each original cell, wherein the trench gate of each original cell comprises a gate trench, a gate dielectric layer and a gate conductive material layer, and the method comprises the following steps:
forming the grid grooves in the drift region by adopting a photoetching and etching process, wherein the region between every two adjacent grid grooves is a semiconductor platform region;
forming the gate dielectric layer on the bottom surface and the side surface of the gate groove;
filling an electric material layer in the grid groove to form the grid conductive material layer;
step three, injecting second conductive type doped ions into the surface area of the drift area of the semiconductor platform area by taking the trench gate as a self-alignment definition condition to form a channel area in a self-alignment manner; the junction depth of the channel region is smaller than the depth of the grid groove, and the surface of the channel region covered by the side surface of the grid conductive material layer is used for forming a channel;
forming a charge balance groove in the drift region of the semiconductor platform region by adopting a photoetching and etching process, wherein the depth of the charge balance groove is greater than that of the grid groove;
fifthly, self-aligned second conductive type doped ions are implanted into the drift region at the bottom of the charge balance groove to form a charge balance region; the charge balance region and the adjacent drift region are mutually depleted, so that the voltage endurance of the device can be improved, and the doping concentration of the drift region can be increased, so that the on-resistance of the device is reduced;
filling a third dielectric layer in the charge balance groove, and performing self-aligned ion implantation of first conduction type heavy doping on the surface area of the channel region outside the charge balance groove to form a source region;
forming an interlayer film, wherein the interlayer film covers the trench gate, the source region and the third dielectric layer; forming a contact hole penetrating through the interlayer film, the contact hole at the top of the source region being a source contact hole; the step of forming the contact hole comprises the steps of firstly forming an opening of the contact hole by adopting a photoetching and etching process, and then filling metal into the opening of the contact hole to form the contact hole;
the opening of the source contact hole is larger than the transverse size of the charge balance groove in the transverse direction, the top of the charge balance groove is completely exposed, and the step of removing the third dielectric layer in the charge balance groove is further included after the opening of the source contact hole is formed, so that the opening of the source contact hole is communicated with the charge balance groove in the longitudinal direction;
passing the source region through an opening bottom of the source contact hole in a longitudinal direction and exposing the channel region surface;
eighthly, forming a source leading-out structure made of a conductive material in the charge balance groove at the opening and the bottom of the source contact hole, wherein the source leading-out structure and the charge balance area at the bottom, the channel area and the source area form ohmic contact; and forming a front metal layer, imaging the front metal layer to form a source electrode, and connecting the top of the source lead-out structure with the source electrode.
10. The method of manufacturing a trench-gate power device of claim 9, wherein: the semiconductor substrate is a silicon substrate; the gate dielectric layer is a gate oxide layer; the grid conductive material layer is a polysilicon grid.
11. The method of manufacturing a trench-gate power device of claim 10, wherein: step eight comprises the following sub-steps:
growing a second dielectric layer, then carrying out overall etching on the second dielectric layer to form the second dielectric layer on the side surface of the charge balance groove in a self-alignment manner, and removing the second dielectric layer which is positioned at the bottom of the charge balance groove, at the top corner of the charge balance groove and at the opening bottom of the source contact hole outside the charge balance groove;
performing ion implantation of second conductive type heavy doping to form a first contact region and a second contact region in a self-alignment manner in the region where the second dielectric layer is removed; the first contact region is positioned on the top surface of the charge balance region, and the second contact region is positioned at the top corner of the charge balance groove and the surface of the channel region at the opening bottom of the source contact hole outside the charge balance groove;
growing a second polycrystalline silicon layer and carrying out back etching on the second polycrystalline silicon layer, wherein the second polycrystalline silicon layer after back etching is filled in the charge balance groove and extends into the opening of the source contact hole, the second polycrystalline silicon layer and the charge balance area at the bottom, the channel area and the source area form ohmic contact, and the second polycrystalline silicon layer is used as a component of a conductive material layer of the source leading-out structure;
and filling a metal layer in the opening of the source contact hole at the top of the second polysilicon layer, forming the source contact hole by the metal layer filled in the opening of the source contact hole at the top of the second polysilicon layer, and overlapping the second polysilicon layer and the source contact hole to form the source lead-out structure.
12. The method of manufacturing a trench-gate power device of claim 11, wherein: the second polycrystalline silicon layer is heavily doped with a first conduction type; or, the second polysilicon layer is heavily doped with the second conductive type.
13. The method of manufacturing a trench-gate power device of claim 9, wherein: step eight comprises the following sub-steps:
performing ion implantation self-alignment of second conductive type heavy doping to form a first contact region and a second contact region; the first contact region is positioned on the top surface of the charge balance region, and the second contact region is positioned at the top corner of the charge balance groove and the surface of the channel region at the opening bottom of the source contact hole outside the charge balance groove;
and filling metal layers in the openings of the source contact holes and the charge balance grooves at the bottoms of the openings of the source contact holes to form the source contact holes, wherein the conductive material layer of the source leading-out structure directly consists of the metal layers forming the source contact holes.
14. A method of manufacturing a trench-gate power device according to any of claims 1 to 13, wherein: the trench gate power device is a trench gate power MOSFET;
the trench gate power MOSFET is an N-type device, the first conduction type is an N-type device, and the second conduction type is a P-type device; or the trench gate power MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type;
the breakdown voltage of the trench gate power MOSFET is 30-100V;
the depth of the grid groove is 0.4-1.5 microns.
15. The method of manufacturing a trench-gate power device of claim 14, wherein: when the trench gate power MOSFET is an N-type device, the implanted impurity of the charge balance area in the fifth step is boron or boron difluoride;
the ion implantation of the charge balance area is single implantation; or, the ion implantation of the charge balance region comprises multiple implantation, the implantation energy is different between the multiple implantation, and the distribution uniformity of the charge balance region in the longitudinal direction is improved by the multiple implantation.
CN201910742228.0A 2019-08-13 2019-08-13 Trench gate power device and manufacturing method thereof Pending CN112397506A (en)

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